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Initial bootloader commit

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GClarkson
2025-04-12 13:34:38 +01:00
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292
EFR32MG24/Source/EFR32MG24_Startup.s Normal file
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/*********************************************************************
* SEGGER Microcontroller GmbH *
* The Embedded Experts *
**********************************************************************
* *
* (c) 2014 - 2022 SEGGER Microcontroller GmbH *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
* *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or *
* without modification, are permitted provided that the following *
* condition is met: *
* *
* - Redistributions of source code must retain the above copyright *
* notice, this condition and the following disclaimer. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
* DAMAGE. *
* *
**********************************************************************
-------------------------- END-OF-HEADER -----------------------------
File : EFR32MG24_Startup.s
Purpose : Startup and exception handlers for EFR32MG24 devices.
Additional information:
Preprocessor Definitions
__NO_SYSTEM_INIT
If defined,
SystemInit is not called.
If not defined,
SystemInit is called.
SystemInit is usually supplied by the CMSIS files.
This file declares a weak implementation as fallback.
__NO_SYSTEM_CLK_UPDATE
If defined,
SystemCoreClockUpdate is not automatically called.
Should be defined if SystemCoreClockUpdate must not be called before main().
If not defined,
SystemCoreClockUpdate is called before the application entry point.
__MEMORY_INIT
If defined,
MemoryInit is called after SystemInit.
void MemoryInit(void) can be implemented to enable external
memory controllers.
__VECTORS_IN_RAM
If defined,
the vector table will be copied from Flash to RAM,
and the vector table offset register is adjusted.
__VTOR_CONFIG
If defined,
the vector table offset register is set to point to the
application's vector table.
__NO_FPU_ENABLE
If defined, the FPU is explicitly not enabled,
even if the compiler could use floating point operations.
__SOFTFP__
Defined by the build system.
If not defined, the FPU is enabled for floating point operations.
*/
.syntax unified
/*********************************************************************
*
* Global functions
*
**********************************************************************
*/
/*********************************************************************
*
* Reset_Handler
*
* Function description
* Exception handler for reset.
* Generic bringup of a Cortex-M system.
*
* Additional information
* The stack pointer is expected to be initialized by hardware,
* i.e. read from vectortable[0].
* For manual initialization add
* ldr R0, =__stack_end__
* mov SP, R0
*/
.global bootloader_reset_handler
.global Bootloader_Reset_Handler
.equ bootloader_reset_handler, Bootloader_Reset_Handler
.section .init.Bootloader_Reset_Handler, "ax"
.balign 2
.thumb_func
Bootloader_Reset_Handler:
#ifndef __NO_SYSTEM_INIT
//
// Call SystemInit
//
bl btl_SystemInit
#endif
//
// Call bootloader Init
//
bl btl_init
#ifdef __MEMORY_INIT
//
// Call MemoryInit
//
bl MemoryInit
#endif
#ifdef __VECTORS_IN_RAM
//
// Copy vector table (from Flash) to RAM
//
ldr R0, =__vectors_start__
ldr R1, =__vectors_end__
ldr R2, =__vectors_ram_start__
1:
cmp R0, R1
beq 2f
ldr R3, [R0]
str R3, [R2]
adds R0, R0, #4
adds R2, R2, #4
b 1b
2:
#endif
#if defined(__VTOR_CONFIG) || defined(__VECTORS_IN_RAM)
//
// Configure vector table offset register
//
#ifdef __ARM_ARCH_6M__
ldr R0, =0xE000ED08 // VTOR_REG
#else
movw R0, 0xED08 // VTOR_REG
movt R0, 0xE000
#endif
#ifdef __VECTORS_IN_RAM
ldr R1, =_vectors_ram
#else
ldr R1, =_vectors
#endif
str R1, [R0]
#endif
#if !defined(__SOFTFP__) && !defined(__NO_FPU_ENABLE)
//
// Enable CP11 and CP10 with CPACR |= (0xf<<20)
//
movw R0, 0xED88 // CPACR
movt R0, 0xE000
ldr R1, [R0]
orrs R1, R1, #(0xf << 20)
str R1, [R0]
#endif
//
// Call runtime initialization, which calls main().
//
bl _start
//
// Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP,
// when there is no strong definition of SystemInit.
//
.weak btl_SystemInit
//
// Place SystemCoreClockUpdate in .init_array
// to be called after runtime initialization
//
#if !defined(__NO_SYSTEM_INIT) && !defined(__NO_SYSTEM_CLK_UPDATE)
.section .init_array, "aw"
.balign 4
.word SystemCoreClockUpdate
#endif
/*********************************************************************
*
* HardFault_Handler
*
* Function description
* Simple exception handler for HardFault.
* In case of a HardFault caused by BKPT instruction without
* debugger attached, return execution, otherwise stay in loop.
*
* Additional information
* The stack pointer is expected to be initialized by hardware,
* i.e. read from vectortable[0].
* For manual initialization add
* ldr R0, =__stack_end__
* mov SP, R0
*/
#undef L
#define L(label) .LHardFault_Handler_##label
.weak HardFault_Handler
.section .init.HardFault_Handler, "ax"
.balign 2
.thumb_func
HardFault_Handler:
//
// Check if HardFault is caused by BKPT instruction
//
ldr R1, =0xE000ED2C // Load NVIC_HFSR
ldr R2, [R1]
cmp R2, #0 // Check NVIC_HFSR[31]
L(hfLoop):
bmi L(hfLoop) // Not set? Stay in HardFault Handler.
//
// Continue execution after BKPT instruction
//
#if defined(__thumb__) && !defined(__thumb2__)
movs R0, #4
mov R1, LR
tst R0, R1 // Check EXC_RETURN in Link register bit 2.
bne L(Uses_PSP)
mrs R0, MSP // Stacking was using MSP.
b L(Pass_StackPtr)
L(Uses_PSP):
mrs R0, PSP // Stacking was using PSP.
L(Pass_StackPtr):
#else
tst LR, #4 // Check EXC_RETURN[2] in link register to get the return stack
ite eq
mrseq R0, MSP // Frame stored on MSP
mrsne R0, PSP // Frame stored on PSP
#endif
//
// Reset HardFault Status
//
#if defined(__thumb__) && !defined(__thumb2__)
movs R3, #1
lsls R3, R3, #31
orrs R2, R3
str R2, [R1]
#else
orr R2, R2, #0x80000000
str R2, [R1]
#endif
//
// Adjust return address
//
ldr R1, [R0, #24] // Get stored PC from stack
adds R1, #2 // Adjust PC by 2 to skip current BKPT
str R1, [R0, #24] // Write back adjusted PC to stack
//
bx LR // Return
/*********************************************************************
*
* SystemCoreClockUpdate
*
* Function description
* Set the SystemCoreClock variable.
*
* Additional information
* This is a weak implementation, as it is missing in the CMSIS files.
* It is recommended to supply your own implementation.
*/
.weak SystemCoreClockUpdate
.section .init.SystemCoreClockUpdate, "ax"
.balign 2
.thumb_func
SystemCoreClockUpdate:
push {LR}
sub SP, SP, #4
bl SystemHCLKGet
add SP, SP, #4
pop {PC}
/*************************** End of file ****************************/

301
EFR32MG24/Source/efr32mg24_Vectors.s Normal file
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/*********************************************************************
* SEGGER Microcontroller GmbH *
* The Embedded Experts *
**********************************************************************
* *
* (c) 2014 - 2022 SEGGER Microcontroller GmbH *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
* *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or *
* without modification, are permitted provided that the following *
* condition is met: *
* *
* - Redistributions of source code must retain the above copyright *
* notice, this condition and the following disclaimer. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
* DAMAGE. *
* *
**********************************************************************
-------------------------- END-OF-HEADER -----------------------------
File : efr32mg24_Vectors.s
Purpose : Exception and interrupt vectors for efr32mg24 devices.
Additional information:
Preprocessor Definitions
__NO_EXTERNAL_INTERRUPTS
If defined,
the vector table will contain only the internal exceptions
and interrupts.
__VECTORS_IN_RAM
If defined,
an area of RAM, large enough to store the vector table,
will be reserved.
__OPTIMIZATION_SMALL
If defined,
all weak definitions of interrupt handlers will share the
same implementation.
If not defined,
all weak definitions of interrupt handlers will be defined
with their own implementation.
*/
.syntax unified
/*********************************************************************
*
* Macros
*
**********************************************************************
*/
//
// Directly place a vector (word) in the vector table
//
.macro VECTOR Name=
.section .vectors, "ax"
.code 16
.word \Name
.endm
//
// Declare an exception handler with a weak definition
//
.macro EXC_HANDLER Name=
//
// Insert vector in vector table
//
.section .vectors, "ax"
.word \Name
//
// Insert dummy handler in init section
//
.section .init.\Name, "ax"
.thumb_func
.weak \Name
.balign 2
\Name:
1: b 1b // Endless loop
.endm
//
// Declare an interrupt handler with a weak definition
//
.macro ISR_HANDLER Name=
//
// Insert vector in vector table
//
.section .vectors, "ax"
.word \Name
//
// Insert dummy handler in init section
//
#if defined(__OPTIMIZATION_SMALL)
.section .init, "ax"
.weak \Name
.thumb_set \Name,Dummy_Handler
#else
.section .init.\Name, "ax"
.thumb_func
.weak \Name
.balign 2
\Name:
1: b 1b // Endless loop
#endif
.endm
//
// Place a reserved vector in vector table
//
.macro ISR_RESERVED
.section .vectors, "ax"
.word 0
.endm
//
// Place a reserved vector in vector table
//
.macro ISR_RESERVED_DUMMY
.section .vectors, "ax"
.word Dummy_Handler
.endm
/*********************************************************************
*
* Externals
*
**********************************************************************
*/
.extern __stack_end__
.extern Bootloader_Reset_Handler
.extern HardFault_Handler
/*********************************************************************
*
* Global functions
*
**********************************************************************
*/
/*********************************************************************
*
* Setup of the vector table and weak definition of interrupt handlers
*
*/
.section .vectors, "ax"
.code 16
.balign 512
.global _vectors
.global __Vectors
_vectors:
__Vectors:
//
// Internal exceptions and interrupts
//
VECTOR __stack_end__
VECTOR Bootloader_Reset_Handler
EXC_HANDLER NMI_Handler
VECTOR HardFault_Handler
ISR_RESERVED
ISR_RESERVED
ISR_RESERVED
ISR_RESERVED
ISR_RESERVED
ISR_RESERVED
ISR_RESERVED
EXC_HANDLER SVC_Handler
ISR_RESERVED
ISR_RESERVED
EXC_HANDLER PendSV_Handler
EXC_HANDLER SysTick_Handler
//
// External interrupts
//
#ifndef __NO_EXTERNAL_INTERRUPTS
ISR_HANDLER SMU_SECURE_IRQHandler
ISR_HANDLER SMU_S_PRIVILEGED_IRQHandler
ISR_HANDLER SMU_NS_PRIVILEGED_IRQHandler
ISR_HANDLER EMU_IRQHandler
ISR_HANDLER TIMER0_IRQHandler
ISR_HANDLER TIMER1_IRQHandler
ISR_HANDLER TIMER2_IRQHandler
ISR_HANDLER TIMER3_IRQHandler
ISR_HANDLER TIMER4_IRQHandler
ISR_HANDLER USART0_RX_IRQHandler
ISR_HANDLER USART0_TX_IRQHandler
ISR_HANDLER EUSART0_RX_IRQHandler
ISR_HANDLER EUSART0_TX_IRQHandler
ISR_HANDLER EUSART1_RX_IRQHandler
ISR_HANDLER EUSART1_TX_IRQHandler
ISR_HANDLER MVP_IRQHandler
ISR_HANDLER ICACHE0_IRQHandler
ISR_HANDLER BURTC_IRQHandler
ISR_HANDLER LETIMER0_IRQHandler
ISR_HANDLER SYSCFG_IRQHandler
ISR_HANDLER MPAHBRAM_IRQHandler
ISR_HANDLER LDMA_IRQHandler
ISR_HANDLER LFXO_IRQHandler
ISR_HANDLER LFRCO_IRQHandler
ISR_HANDLER ULFRCO_IRQHandler
ISR_HANDLER GPIO_ODD_IRQHandler
ISR_HANDLER GPIO_EVEN_IRQHandler
ISR_HANDLER I2C0_IRQHandler
ISR_HANDLER I2C1_IRQHandler
ISR_HANDLER EMUDG_IRQHandler
ISR_HANDLER AGC_IRQHandler
ISR_HANDLER BUFC_IRQHandler
ISR_HANDLER FRC_PRI_IRQHandler
ISR_HANDLER FRC_IRQHandler
ISR_HANDLER MODEM_IRQHandler
ISR_HANDLER PROTIMER_IRQHandler
ISR_HANDLER RAC_RSM_IRQHandler
ISR_HANDLER RAC_SEQ_IRQHandler
ISR_HANDLER HOSTMAILBOX_IRQHandler
ISR_HANDLER SYNTH_IRQHandler
ISR_HANDLER ACMP0_IRQHandler
ISR_HANDLER ACMP1_IRQHandler
ISR_HANDLER WDOG0_IRQHandler
ISR_HANDLER WDOG1_IRQHandler
ISR_HANDLER HFXO0_IRQHandler
ISR_HANDLER HFRCO0_IRQHandler
ISR_HANDLER HFRCOEM23_IRQHandler
ISR_HANDLER CMU_IRQHandler
ISR_HANDLER AES_IRQHandler
ISR_HANDLER IADC_IRQHandler
ISR_HANDLER MSC_IRQHandler
ISR_HANDLER DPLL0_IRQHandler
ISR_HANDLER EMUEFP_IRQHandler
ISR_HANDLER DCDC_IRQHandler
ISR_HANDLER PCNT0_IRQHandler
ISR_HANDLER SW0_IRQHandler
ISR_HANDLER SW1_IRQHandler
ISR_HANDLER SW2_IRQHandler
ISR_HANDLER SW3_IRQHandler
ISR_HANDLER KERNEL0_IRQHandler
ISR_HANDLER KERNEL1_IRQHandler
ISR_HANDLER M33CTI0_IRQHandler
ISR_HANDLER M33CTI1_IRQHandler
ISR_HANDLER FPUEXH_IRQHandler
ISR_HANDLER SETAMPERHOST_IRQHandler
ISR_HANDLER SEMBRX_IRQHandler
ISR_HANDLER SEMBTX_IRQHandler
ISR_HANDLER SYSRTC_APP_IRQHandler
ISR_HANDLER SYSRTC_SEQ_IRQHandler
ISR_HANDLER KEYSCAN_IRQHandler
ISR_HANDLER RFECA0_IRQHandler
ISR_HANDLER RFECA1_IRQHandler
ISR_HANDLER VDAC0_IRQHandler
ISR_HANDLER VDAC1_IRQHandler
ISR_HANDLER AHB2AHB0_IRQHandler
ISR_HANDLER AHB2AHB1_IRQHandler
#endif
//
.section .vectors, "ax"
_vectors_end:
#ifdef __VECTORS_IN_RAM
//
// Reserve space with the size of the vector table
// in the designated RAM section.
//
.section .vectors_ram, "ax"
.balign 512
.global _vectors_ram
_vectors_ram:
.space _vectors_end - _vectors, 0
#endif
/*********************************************************************
*
* Dummy handler to be used for reserved interrupt vectors
* and weak implementation of interrupts.
*
*/
.section .init.Dummy_Handler, "ax"
.thumb_func
.weak Dummy_Handler
.balign 2
Dummy_Handler:
1: b 1b // Endless loop
/*************************** End of file ****************************/