1387 lines
184 KiB
C
1387 lines
184 KiB
C
/**************************************************************************//**
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* @file
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* @brief EFR32MG24 MVP register and bit field definitions
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******************************************************************************
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* # License
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* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
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******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*****************************************************************************/
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#ifndef EFR32MG24_MVP_H
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#define EFR32MG24_MVP_H
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#define MVP_HAS_SET_CLEAR
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/**************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/**************************************************************************//**
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* @defgroup EFR32MG24_MVP MVP
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* @{
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* @brief EFR32MG24 MVP Register Declaration.
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*****************************************************************************/
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/** MVP PERF Register Group Declaration. */
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typedef struct {
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__IM uint32_t CNT; /**< Run Counter */
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} MVP_PERF_TypeDef;
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/** MVP ARRAYST Register Group Declaration. */
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typedef struct {
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__IOM uint32_t INDEXSTATE; /**< Index State */
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} MVP_ARRAYST_TypeDef;
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/** MVP LOOPST Register Group Declaration. */
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typedef struct {
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__IOM uint32_t STATE; /**< Loop State */
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} MVP_LOOPST_TypeDef;
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/** MVP ALU Register Group Declaration. */
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typedef struct {
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__IOM uint32_t REGSTATE; /**< ALU Rn Register */
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} MVP_ALU_TypeDef;
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/** MVP ARRAY Register Group Declaration. */
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typedef struct {
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__IOM uint32_t ADDRCFG; /**< Array Base Address */
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__IOM uint32_t DIM0CFG; /**< Dimension 0 Configuration */
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__IOM uint32_t DIM1CFG; /**< Dimension 1 Configuration */
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__IOM uint32_t DIM2CFG; /**< Dimension 2 Configuration */
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} MVP_ARRAY_TypeDef;
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/** MVP LOOP Register Group Declaration. */
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typedef struct {
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__IOM uint32_t CFG; /**< Loop Configuration */
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__IOM uint32_t RST; /**< Loop Reset */
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} MVP_LOOP_TypeDef;
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/** MVP INSTR Register Group Declaration. */
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typedef struct {
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__IOM uint32_t CFG0; /**< Instruction Configuration Word 0 */
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__IOM uint32_t CFG1; /**< Instruction Configuration Word 1 */
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__IOM uint32_t CFG2; /**< Instruction Configuration Word 2 */
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} MVP_INSTR_TypeDef;
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/** MVP Register Declaration. */
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typedef struct {
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__IM uint32_t IPVERSION; /**< IP Version */
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__IOM uint32_t EN; /**< Enable */
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__IOM uint32_t SWRST; /**< Software Reset */
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__IOM uint32_t CFG; /**< Configuration */
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__IM uint32_t STATUS; /**< Status */
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MVP_PERF_TypeDef PERF[2U]; /**< */
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__IOM uint32_t IF; /**< Interrupt Flags */
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__IOM uint32_t IEN; /**< Interrupt Enables */
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__IM uint32_t FAULTSTATUS; /**< Fault Status */
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__IM uint32_t FAULTADDR; /**< Fault Address */
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__IOM uint32_t PROGRAMSTATE; /**< Program State */
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MVP_ARRAYST_TypeDef ARRAYST[5U]; /**< */
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MVP_LOOPST_TypeDef LOOPST[8U]; /**< */
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MVP_ALU_TypeDef ALU[8U]; /**< */
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MVP_ARRAY_TypeDef ARRAY[5U]; /**< */
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MVP_LOOP_TypeDef LOOP[8U]; /**< */
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MVP_INSTR_TypeDef INSTR[8U]; /**< */
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__IOM uint32_t CMD; /**< Command Register */
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uint32_t RESERVED0[34U]; /**< Reserved for future use */
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__IOM uint32_t DEBUGEN; /**< Debug Enable Register */
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__IOM uint32_t DEBUGSTEPCNT; /**< Debug Step Register */
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uint32_t RESERVED1[894U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_SET; /**< IP Version */
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__IOM uint32_t EN_SET; /**< Enable */
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__IOM uint32_t SWRST_SET; /**< Software Reset */
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__IOM uint32_t CFG_SET; /**< Configuration */
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__IM uint32_t STATUS_SET; /**< Status */
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MVP_PERF_TypeDef PERF_SET[2U]; /**< */
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__IOM uint32_t IF_SET; /**< Interrupt Flags */
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__IOM uint32_t IEN_SET; /**< Interrupt Enables */
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__IM uint32_t FAULTSTATUS_SET; /**< Fault Status */
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__IM uint32_t FAULTADDR_SET; /**< Fault Address */
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__IOM uint32_t PROGRAMSTATE_SET; /**< Program State */
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MVP_ARRAYST_TypeDef ARRAYST_SET[5U]; /**< */
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MVP_LOOPST_TypeDef LOOPST_SET[8U]; /**< */
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MVP_ALU_TypeDef ALU_SET[8U]; /**< */
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MVP_ARRAY_TypeDef ARRAY_SET[5U]; /**< */
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MVP_LOOP_TypeDef LOOP_SET[8U]; /**< */
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MVP_INSTR_TypeDef INSTR_SET[8U]; /**< */
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__IOM uint32_t CMD_SET; /**< Command Register */
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uint32_t RESERVED2[34U]; /**< Reserved for future use */
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__IOM uint32_t DEBUGEN_SET; /**< Debug Enable Register */
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__IOM uint32_t DEBUGSTEPCNT_SET; /**< Debug Step Register */
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uint32_t RESERVED3[894U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_CLR; /**< IP Version */
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__IOM uint32_t EN_CLR; /**< Enable */
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__IOM uint32_t SWRST_CLR; /**< Software Reset */
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__IOM uint32_t CFG_CLR; /**< Configuration */
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__IM uint32_t STATUS_CLR; /**< Status */
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MVP_PERF_TypeDef PERF_CLR[2U]; /**< */
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__IOM uint32_t IF_CLR; /**< Interrupt Flags */
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__IOM uint32_t IEN_CLR; /**< Interrupt Enables */
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__IM uint32_t FAULTSTATUS_CLR; /**< Fault Status */
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__IM uint32_t FAULTADDR_CLR; /**< Fault Address */
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__IOM uint32_t PROGRAMSTATE_CLR; /**< Program State */
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MVP_ARRAYST_TypeDef ARRAYST_CLR[5U]; /**< */
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MVP_LOOPST_TypeDef LOOPST_CLR[8U]; /**< */
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MVP_ALU_TypeDef ALU_CLR[8U]; /**< */
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MVP_ARRAY_TypeDef ARRAY_CLR[5U]; /**< */
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MVP_LOOP_TypeDef LOOP_CLR[8U]; /**< */
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MVP_INSTR_TypeDef INSTR_CLR[8U]; /**< */
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__IOM uint32_t CMD_CLR; /**< Command Register */
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uint32_t RESERVED4[34U]; /**< Reserved for future use */
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__IOM uint32_t DEBUGEN_CLR; /**< Debug Enable Register */
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__IOM uint32_t DEBUGSTEPCNT_CLR; /**< Debug Step Register */
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uint32_t RESERVED5[894U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_TGL; /**< IP Version */
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__IOM uint32_t EN_TGL; /**< Enable */
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__IOM uint32_t SWRST_TGL; /**< Software Reset */
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__IOM uint32_t CFG_TGL; /**< Configuration */
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__IM uint32_t STATUS_TGL; /**< Status */
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MVP_PERF_TypeDef PERF_TGL[2U]; /**< */
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__IOM uint32_t IF_TGL; /**< Interrupt Flags */
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__IOM uint32_t IEN_TGL; /**< Interrupt Enables */
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__IM uint32_t FAULTSTATUS_TGL; /**< Fault Status */
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__IM uint32_t FAULTADDR_TGL; /**< Fault Address */
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__IOM uint32_t PROGRAMSTATE_TGL; /**< Program State */
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MVP_ARRAYST_TypeDef ARRAYST_TGL[5U]; /**< */
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MVP_LOOPST_TypeDef LOOPST_TGL[8U]; /**< */
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MVP_ALU_TypeDef ALU_TGL[8U]; /**< */
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MVP_ARRAY_TypeDef ARRAY_TGL[5U]; /**< */
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MVP_LOOP_TypeDef LOOP_TGL[8U]; /**< */
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MVP_INSTR_TypeDef INSTR_TGL[8U]; /**< */
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__IOM uint32_t CMD_TGL; /**< Command Register */
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uint32_t RESERVED6[34U]; /**< Reserved for future use */
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__IOM uint32_t DEBUGEN_TGL; /**< Debug Enable Register */
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__IOM uint32_t DEBUGSTEPCNT_TGL; /**< Debug Step Register */
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} MVP_TypeDef;
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/** @} End of group EFR32MG24_MVP */
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/**************************************************************************//**
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* @addtogroup EFR32MG24_MVP
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* @{
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* @defgroup EFR32MG24_MVP_BitFields MVP Bit Fields
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* @{
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*****************************************************************************/
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/* Bit fields for MVP IPVERSION */
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#define _MVP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for MVP_IPVERSION */
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#define _MVP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MVP_IPVERSION */
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#define _MVP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MVP_IPVERSION */
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#define _MVP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_IPVERSION */
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#define _MVP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_IPVERSION */
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#define MVP_IPVERSION_IPVERSION_DEFAULT (_MVP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IPVERSION */
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/* Bit fields for MVP EN */
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#define _MVP_EN_RESETVALUE 0x00000000UL /**< Default value for MVP_EN */
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#define _MVP_EN_MASK 0x00000003UL /**< Mask for MVP_EN */
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#define MVP_EN_EN (0x1UL << 0) /**< Enable */
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#define _MVP_EN_EN_SHIFT 0 /**< Shift value for MVP_EN */
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#define _MVP_EN_EN_MASK 0x1UL /**< Bit mask for MVP_EN */
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#define _MVP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */
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#define MVP_EN_EN_DEFAULT (_MVP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_EN */
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#define MVP_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */
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#define _MVP_EN_DISABLING_SHIFT 1 /**< Shift value for MVP_DISABLING */
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#define _MVP_EN_DISABLING_MASK 0x2UL /**< Bit mask for MVP_DISABLING */
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#define _MVP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */
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#define MVP_EN_DISABLING_DEFAULT (_MVP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_EN */
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/* Bit fields for MVP SWRST */
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#define _MVP_SWRST_RESETVALUE 0x00000000UL /**< Default value for MVP_SWRST */
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#define _MVP_SWRST_MASK 0x00000003UL /**< Mask for MVP_SWRST */
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#define MVP_SWRST_SWRST (0x1UL << 0) /**< Software Reset Command */
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#define _MVP_SWRST_SWRST_SHIFT 0 /**< Shift value for MVP_SWRST */
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#define _MVP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for MVP_SWRST */
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#define _MVP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */
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#define MVP_SWRST_SWRST_DEFAULT (_MVP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_SWRST */
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#define MVP_SWRST_RESETTING (0x1UL << 1) /**< Software Reset Busy Status */
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#define _MVP_SWRST_RESETTING_SHIFT 1 /**< Shift value for MVP_RESETTING */
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#define _MVP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for MVP_RESETTING */
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#define _MVP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */
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#define MVP_SWRST_RESETTING_DEFAULT (_MVP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_SWRST */
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/* Bit fields for MVP CFG */
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#define _MVP_CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_CFG */
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#define _MVP_CFG_MASK 0x00FF000FUL /**< Mask for MVP_CFG */
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#define MVP_CFG_PERFCNTEN (0x1UL << 0) /**< Performance Counter Enable */
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#define _MVP_CFG_PERFCNTEN_SHIFT 0 /**< Shift value for MVP_PERFCNTEN */
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#define _MVP_CFG_PERFCNTEN_MASK 0x1UL /**< Bit mask for MVP_PERFCNTEN */
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#define _MVP_CFG_PERFCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */
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#define MVP_CFG_PERFCNTEN_DEFAULT (_MVP_CFG_PERFCNTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CFG */
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#define MVP_CFG_OUTCOMPRESSDIS (0x1UL << 1) /**< ALU Output Stream Compression Disable */
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#define _MVP_CFG_OUTCOMPRESSDIS_SHIFT 1 /**< Shift value for MVP_OUTCOMPRESSDIS */
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#define _MVP_CFG_OUTCOMPRESSDIS_MASK 0x2UL /**< Bit mask for MVP_OUTCOMPRESSDIS */
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#define _MVP_CFG_OUTCOMPRESSDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */
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#define MVP_CFG_OUTCOMPRESSDIS_DEFAULT (_MVP_CFG_OUTCOMPRESSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CFG */
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#define MVP_CFG_INCACHEDIS (0x1UL << 2) /**< ALU Input Word Cache Disable */
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#define _MVP_CFG_INCACHEDIS_SHIFT 2 /**< Shift value for MVP_INCACHEDIS */
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#define _MVP_CFG_INCACHEDIS_MASK 0x4UL /**< Bit mask for MVP_INCACHEDIS */
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#define _MVP_CFG_INCACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */
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#define MVP_CFG_INCACHEDIS_DEFAULT (_MVP_CFG_INCACHEDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CFG */
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#define MVP_CFG_LOOPERRHALTDIS (0x1UL << 3) /**< Loop Error Halt Disable */
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#define _MVP_CFG_LOOPERRHALTDIS_SHIFT 3 /**< Shift value for MVP_LOOPERRHALTDIS */
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#define _MVP_CFG_LOOPERRHALTDIS_MASK 0x8UL /**< Bit mask for MVP_LOOPERRHALTDIS */
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#define _MVP_CFG_LOOPERRHALTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */
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#define MVP_CFG_LOOPERRHALTDIS_DEFAULT (_MVP_CFG_LOOPERRHALTDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_SHIFT 16 /**< Shift value for MVP_PERF0CNTSEL */
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#define _MVP_CFG_PERF0CNTSEL_MASK 0xF0000UL /**< Bit mask for MVP_PERF0CNTSEL */
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#define _MVP_CFG_PERF0CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */
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#define _MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_DEFAULT (_MVP_CFG_PERF0CNTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_RUN (_MVP_CFG_PERF0CNTSEL_RUN << 16) /**< Shifted mode RUN for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_CMD (_MVP_CFG_PERF0CNTSEL_CMD << 16) /**< Shifted mode CMD for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_STALL (_MVP_CFG_PERF0CNTSEL_STALL << 16) /**< Shifted mode STALL for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_NOOP (_MVP_CFG_PERF0CNTSEL_NOOP << 16) /**< Shifted mode NOOP for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_ALUACTIVE (_MVP_CFG_PERF0CNTSEL_ALUACTIVE << 16) /**< Shifted mode ALUACTIVE for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_PIPESTALL (_MVP_CFG_PERF0CNTSEL_PIPESTALL << 16) /**< Shifted mode PIPESTALL for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_IOFENCESTALL (_MVP_CFG_PERF0CNTSEL_IOFENCESTALL << 16) /**< Shifted mode IOFENCESTALL for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_LOAD0STALL (_MVP_CFG_PERF0CNTSEL_LOAD0STALL << 16) /**< Shifted mode LOAD0STALL for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_LOAD1STALL (_MVP_CFG_PERF0CNTSEL_LOAD1STALL << 16) /**< Shifted mode LOAD1STALL for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_STORESTALL (_MVP_CFG_PERF0CNTSEL_STORESTALL << 16) /**< Shifted mode STORESTALL for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_BUSSTALL (_MVP_CFG_PERF0CNTSEL_BUSSTALL << 16) /**< Shifted mode BUSSTALL for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL (_MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL << 16) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL (_MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL << 16) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL (_MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL << 16) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */
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#define MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL (_MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL << 16) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_SHIFT 20 /**< Shift value for MVP_PERF1CNTSEL */
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#define _MVP_CFG_PERF1CNTSEL_MASK 0xF00000UL /**< Bit mask for MVP_PERF1CNTSEL */
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#define _MVP_CFG_PERF1CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */
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#define _MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_DEFAULT (_MVP_CFG_PERF1CNTSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_RUN (_MVP_CFG_PERF1CNTSEL_RUN << 20) /**< Shifted mode RUN for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_CMD (_MVP_CFG_PERF1CNTSEL_CMD << 20) /**< Shifted mode CMD for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_STALL (_MVP_CFG_PERF1CNTSEL_STALL << 20) /**< Shifted mode STALL for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_NOOP (_MVP_CFG_PERF1CNTSEL_NOOP << 20) /**< Shifted mode NOOP for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_ALUACTIVE (_MVP_CFG_PERF1CNTSEL_ALUACTIVE << 20) /**< Shifted mode ALUACTIVE for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_PIPESTALL (_MVP_CFG_PERF1CNTSEL_PIPESTALL << 20) /**< Shifted mode PIPESTALL for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_IOFENCESTALL (_MVP_CFG_PERF1CNTSEL_IOFENCESTALL << 20) /**< Shifted mode IOFENCESTALL for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_LOAD0STALL (_MVP_CFG_PERF1CNTSEL_LOAD0STALL << 20) /**< Shifted mode LOAD0STALL for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_LOAD1STALL (_MVP_CFG_PERF1CNTSEL_LOAD1STALL << 20) /**< Shifted mode LOAD1STALL for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_STORESTALL (_MVP_CFG_PERF1CNTSEL_STORESTALL << 20) /**< Shifted mode STORESTALL for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_BUSSTALL (_MVP_CFG_PERF1CNTSEL_BUSSTALL << 20) /**< Shifted mode BUSSTALL for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL (_MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL << 20) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL (_MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL << 20) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL (_MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL << 20) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */
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#define MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL (_MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL << 20) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */
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/* Bit fields for MVP STATUS */
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#define _MVP_STATUS_RESETVALUE 0x00000004UL /**< Default value for MVP_STATUS */
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#define _MVP_STATUS_MASK 0x00000007UL /**< Mask for MVP_STATUS */
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#define MVP_STATUS_RUNNING (0x1UL << 0) /**< Running Status */
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#define _MVP_STATUS_RUNNING_SHIFT 0 /**< Shift value for MVP_RUNNING */
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#define _MVP_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for MVP_RUNNING */
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#define _MVP_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */
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#define MVP_STATUS_RUNNING_DEFAULT (_MVP_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_STATUS */
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#define MVP_STATUS_PAUSED (0x1UL << 1) /**< Paused Status */
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#define _MVP_STATUS_PAUSED_SHIFT 1 /**< Shift value for MVP_PAUSED */
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#define _MVP_STATUS_PAUSED_MASK 0x2UL /**< Bit mask for MVP_PAUSED */
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#define _MVP_STATUS_PAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */
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#define MVP_STATUS_PAUSED_DEFAULT (_MVP_STATUS_PAUSED_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_STATUS */
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#define MVP_STATUS_IDLE (0x1UL << 2) /**< Idle Status */
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#define _MVP_STATUS_IDLE_SHIFT 2 /**< Shift value for MVP_IDLE */
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#define _MVP_STATUS_IDLE_MASK 0x4UL /**< Bit mask for MVP_IDLE */
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#define _MVP_STATUS_IDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_STATUS */
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#define MVP_STATUS_IDLE_DEFAULT (_MVP_STATUS_IDLE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_STATUS */
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/* Bit fields for MVP PERFCNT */
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#define _MVP_PERFCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_PERFCNT */
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#define _MVP_PERFCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_PERFCNT */
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#define _MVP_PERFCNT_COUNT_SHIFT 0 /**< Shift value for MVP_COUNT */
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#define _MVP_PERFCNT_COUNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_COUNT */
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#define _MVP_PERFCNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PERFCNT */
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#define MVP_PERFCNT_COUNT_DEFAULT (_MVP_PERFCNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PERFCNT */
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/* Bit fields for MVP IF */
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#define _MVP_IF_RESETVALUE 0x00000000UL /**< Default value for MVP_IF */
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#define _MVP_IF_MASK 0x1F0FFDFFUL /**< Mask for MVP_IF */
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#define MVP_IF_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Flags */
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#define _MVP_IF_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */
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#define _MVP_IF_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */
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#define _MVP_IF_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_PROGDONE_DEFAULT (_MVP_IF_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Flag */
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#define _MVP_IF_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */
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#define _MVP_IF_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */
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#define _MVP_IF_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP0DONE_DEFAULT (_MVP_IF_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Flag */
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#define _MVP_IF_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */
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#define _MVP_IF_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */
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#define _MVP_IF_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP1DONE_DEFAULT (_MVP_IF_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Flag */
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#define _MVP_IF_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */
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#define _MVP_IF_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */
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#define _MVP_IF_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP2DONE_DEFAULT (_MVP_IF_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Flag */
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#define _MVP_IF_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */
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#define _MVP_IF_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */
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#define _MVP_IF_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP3DONE_DEFAULT (_MVP_IF_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Flag */
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#define _MVP_IF_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */
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#define _MVP_IF_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */
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#define _MVP_IF_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP4DONE_DEFAULT (_MVP_IF_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Flag */
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#define _MVP_IF_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */
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#define _MVP_IF_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */
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#define _MVP_IF_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP5DONE_DEFAULT (_MVP_IF_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Flag */
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#define _MVP_IF_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */
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#define _MVP_IF_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */
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#define _MVP_IF_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP6DONE_DEFAULT (_MVP_IF_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Flag */
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#define _MVP_IF_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */
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#define _MVP_IF_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */
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#define _MVP_IF_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOP7DONE_DEFAULT (_MVP_IF_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Flag */
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#define _MVP_IF_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */
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#define _MVP_IF_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */
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#define _MVP_IF_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_ALUNAN_DEFAULT (_MVP_IF_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_R0POSREAL (0x1UL << 11) /**< R0 non-zero Interrupt Flag */
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#define _MVP_IF_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */
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#define _MVP_IF_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */
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#define _MVP_IF_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_R0POSREAL_DEFAULT (_MVP_IF_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_ALUOF (0x1UL << 12) /**< ALU Overflow on result */
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#define _MVP_IF_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */
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#define _MVP_IF_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */
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#define _MVP_IF_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_ALUOF_DEFAULT (_MVP_IF_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_ALUUF (0x1UL << 13) /**< ALU Underflow on result */
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#define _MVP_IF_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */
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#define _MVP_IF_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */
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#define _MVP_IF_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_ALUUF_DEFAULT (_MVP_IF_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_STORECONVERTOF (0x1UL << 14) /**< Overflow during array store */
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#define _MVP_IF_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */
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#define _MVP_IF_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */
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#define _MVP_IF_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_STORECONVERTOF_DEFAULT (_MVP_IF_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_STORECONVERTUF (0x1UL << 15) /**< Underflow during array store conversion */
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#define _MVP_IF_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */
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#define _MVP_IF_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */
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#define _MVP_IF_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_STORECONVERTUF_DEFAULT (_MVP_IF_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_STORECONVERTINF (0x1UL << 16) /**< Infinity encountered during array store conversion*/
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#define _MVP_IF_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */
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#define _MVP_IF_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */
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#define _MVP_IF_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_STORECONVERTINF_DEFAULT (_MVP_IF_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_STORECONVERTNAN (0x1UL << 17) /**< NaN encountered during array store conversion*/
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#define _MVP_IF_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */
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#define _MVP_IF_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */
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#define _MVP_IF_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_STORECONVERTNAN_DEFAULT (_MVP_IF_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_PERFCNT0 (0x1UL << 18) /**< Run Count Overflow Interrupt Flag */
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#define _MVP_IF_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */
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#define _MVP_IF_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */
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#define _MVP_IF_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_PERFCNT0_DEFAULT (_MVP_IF_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_PERFCNT1 (0x1UL << 19) /**< Stall Count Overflow Interrupt Flag */
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#define _MVP_IF_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */
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#define _MVP_IF_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */
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#define _MVP_IF_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_PERFCNT1_DEFAULT (_MVP_IF_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Flag */
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#define _MVP_IF_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */
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#define _MVP_IF_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */
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#define _MVP_IF_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_LOOPFAULT_DEFAULT (_MVP_IF_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Flag */
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#define _MVP_IF_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */
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#define _MVP_IF_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */
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#define _MVP_IF_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_BUSERRFAULT_DEFAULT (_MVP_IF_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Flag */
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#define _MVP_IF_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */
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#define _MVP_IF_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */
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#define _MVP_IF_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_BUSALIGNFAULT_DEFAULT (_MVP_IF_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_ALUFAULT (0x1UL << 27) /**< ALU Fault Interrupt Flag */
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#define _MVP_IF_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */
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#define _MVP_IF_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */
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#define _MVP_IF_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_ALUFAULT_DEFAULT (_MVP_IF_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IF */
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#define MVP_IF_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Flag */
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#define _MVP_IF_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */
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#define _MVP_IF_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */
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#define _MVP_IF_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
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#define MVP_IF_ARRAYFAULT_DEFAULT (_MVP_IF_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IF */
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/* Bit fields for MVP IEN */
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#define _MVP_IEN_RESETVALUE 0x00000000UL /**< Default value for MVP_IEN */
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#define _MVP_IEN_MASK 0x1F0FFDFFUL /**< Mask for MVP_IEN */
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#define MVP_IEN_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Enable */
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#define _MVP_IEN_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */
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#define _MVP_IEN_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */
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#define _MVP_IEN_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_PROGDONE_DEFAULT (_MVP_IEN_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Enable */
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#define _MVP_IEN_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */
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#define _MVP_IEN_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */
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#define _MVP_IEN_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP0DONE_DEFAULT (_MVP_IEN_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Enable */
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#define _MVP_IEN_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */
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#define _MVP_IEN_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */
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#define _MVP_IEN_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP1DONE_DEFAULT (_MVP_IEN_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Enable */
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#define _MVP_IEN_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */
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#define _MVP_IEN_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */
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#define _MVP_IEN_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP2DONE_DEFAULT (_MVP_IEN_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Enable */
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#define _MVP_IEN_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */
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#define _MVP_IEN_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */
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#define _MVP_IEN_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP3DONE_DEFAULT (_MVP_IEN_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Enable */
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#define _MVP_IEN_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */
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#define _MVP_IEN_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */
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#define _MVP_IEN_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP4DONE_DEFAULT (_MVP_IEN_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Enable */
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#define _MVP_IEN_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */
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#define _MVP_IEN_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */
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#define _MVP_IEN_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP5DONE_DEFAULT (_MVP_IEN_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Enable */
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#define _MVP_IEN_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */
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#define _MVP_IEN_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */
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#define _MVP_IEN_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP6DONE_DEFAULT (_MVP_IEN_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Enable */
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#define _MVP_IEN_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */
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#define _MVP_IEN_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */
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#define _MVP_IEN_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOP7DONE_DEFAULT (_MVP_IEN_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Enable */
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#define _MVP_IEN_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */
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#define _MVP_IEN_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */
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#define _MVP_IEN_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_ALUNAN_DEFAULT (_MVP_IEN_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_R0POSREAL (0x1UL << 11) /**< R0 Non-Zero Interrupt Enable */
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#define _MVP_IEN_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */
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#define _MVP_IEN_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */
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#define _MVP_IEN_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_R0POSREAL_DEFAULT (_MVP_IEN_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_ALUOF (0x1UL << 12) /**< ALU Overflow Interrupt Enable */
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#define _MVP_IEN_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */
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#define _MVP_IEN_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */
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#define _MVP_IEN_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_ALUOF_DEFAULT (_MVP_IEN_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_ALUUF (0x1UL << 13) /**< ALU Underflow Interrupt Enable */
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#define _MVP_IEN_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */
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#define _MVP_IEN_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */
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#define _MVP_IEN_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_ALUUF_DEFAULT (_MVP_IEN_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_STORECONVERTOF (0x1UL << 14) /**< Store conversion Overflow Interrupt Enable */
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#define _MVP_IEN_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */
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#define _MVP_IEN_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */
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#define _MVP_IEN_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_STORECONVERTOF_DEFAULT (_MVP_IEN_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_STORECONVERTUF (0x1UL << 15) /**< Store Conversion Underflow Interrupt Enable */
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#define _MVP_IEN_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */
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#define _MVP_IEN_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */
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#define _MVP_IEN_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_STORECONVERTUF_DEFAULT (_MVP_IEN_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_STORECONVERTINF (0x1UL << 16) /**< Store Conversion Infinity Interrupt Enable */
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#define _MVP_IEN_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */
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#define _MVP_IEN_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */
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#define _MVP_IEN_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_STORECONVERTINF_DEFAULT (_MVP_IEN_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_STORECONVERTNAN (0x1UL << 17) /**< Store Conversion NaN Interrupt Enable */
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#define _MVP_IEN_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */
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#define _MVP_IEN_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */
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#define _MVP_IEN_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_STORECONVERTNAN_DEFAULT (_MVP_IEN_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_PERFCNT0 (0x1UL << 18) /**< Perf Counter 0 Overflow Interrupt Enable */
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#define _MVP_IEN_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */
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#define _MVP_IEN_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */
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#define _MVP_IEN_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_PERFCNT0_DEFAULT (_MVP_IEN_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_PERFCNT1 (0x1UL << 19) /**< Perf Counter 1 Overflow Interrupt Enable */
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#define _MVP_IEN_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */
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#define _MVP_IEN_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */
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#define _MVP_IEN_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_PERFCNT1_DEFAULT (_MVP_IEN_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Enable */
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#define _MVP_IEN_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */
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#define _MVP_IEN_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */
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#define _MVP_IEN_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_LOOPFAULT_DEFAULT (_MVP_IEN_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Enable */
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#define _MVP_IEN_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */
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#define _MVP_IEN_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */
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#define _MVP_IEN_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_BUSERRFAULT_DEFAULT (_MVP_IEN_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Enable */
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#define _MVP_IEN_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */
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#define _MVP_IEN_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */
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#define _MVP_IEN_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_BUSALIGNFAULT_DEFAULT (_MVP_IEN_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_ALUFAULT (0x1UL << 27) /**< ALU Input Fault Interrupt Enable */
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#define _MVP_IEN_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */
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#define _MVP_IEN_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */
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#define _MVP_IEN_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_ALUFAULT_DEFAULT (_MVP_IEN_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IEN */
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#define MVP_IEN_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Enable */
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#define _MVP_IEN_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */
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#define _MVP_IEN_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */
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#define _MVP_IEN_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
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#define MVP_IEN_ARRAYFAULT_DEFAULT (_MVP_IEN_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IEN */
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/* Bit fields for MVP FAULTSTATUS */
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#define _MVP_FAULTSTATUS_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTSTATUS */
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#define _MVP_FAULTSTATUS_MASK 0x000F3707UL /**< Mask for MVP_FAULTSTATUS */
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#define _MVP_FAULTSTATUS_FAULTPC_SHIFT 0 /**< Shift value for MVP_FAULTPC */
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#define _MVP_FAULTSTATUS_FAULTPC_MASK 0x7UL /**< Bit mask for MVP_FAULTPC */
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#define _MVP_FAULTSTATUS_FAULTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */
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#define MVP_FAULTSTATUS_FAULTPC_DEFAULT (_MVP_FAULTSTATUS_FAULTPC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */
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#define _MVP_FAULTSTATUS_FAULTARRAY_SHIFT 8 /**< Shift value for MVP_FAULTARRAY */
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#define _MVP_FAULTSTATUS_FAULTARRAY_MASK 0x700UL /**< Bit mask for MVP_FAULTARRAY */
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#define _MVP_FAULTSTATUS_FAULTARRAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */
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#define MVP_FAULTSTATUS_FAULTARRAY_DEFAULT (_MVP_FAULTSTATUS_FAULTARRAY_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */
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#define _MVP_FAULTSTATUS_FAULTBUS_SHIFT 12 /**< Shift value for MVP_FAULTBUS */
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#define _MVP_FAULTSTATUS_FAULTBUS_MASK 0x3000UL /**< Bit mask for MVP_FAULTBUS */
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#define _MVP_FAULTSTATUS_FAULTBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */
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#define _MVP_FAULTSTATUS_FAULTBUS_NONE 0x00000000UL /**< Mode NONE for MVP_FAULTSTATUS */
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#define _MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM 0x00000001UL /**< Mode LOAD0STREAM for MVP_FAULTSTATUS */
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#define _MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM 0x00000002UL /**< Mode LOAD1STREAM for MVP_FAULTSTATUS */
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#define _MVP_FAULTSTATUS_FAULTBUS_STORESTREAM 0x00000003UL /**< Mode STORESTREAM for MVP_FAULTSTATUS */
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#define MVP_FAULTSTATUS_FAULTBUS_DEFAULT (_MVP_FAULTSTATUS_FAULTBUS_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */
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#define MVP_FAULTSTATUS_FAULTBUS_NONE (_MVP_FAULTSTATUS_FAULTBUS_NONE << 12) /**< Shifted mode NONE for MVP_FAULTSTATUS */
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#define MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM (_MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM << 12) /**< Shifted mode LOAD0STREAM for MVP_FAULTSTATUS*/
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#define MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM (_MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM << 12) /**< Shifted mode LOAD1STREAM for MVP_FAULTSTATUS*/
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#define MVP_FAULTSTATUS_FAULTBUS_STORESTREAM (_MVP_FAULTSTATUS_FAULTBUS_STORESTREAM << 12) /**< Shifted mode STORESTREAM for MVP_FAULTSTATUS*/
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#define _MVP_FAULTSTATUS_FAULTLOOP_SHIFT 16 /**< Shift value for MVP_FAULTLOOP */
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#define _MVP_FAULTSTATUS_FAULTLOOP_MASK 0xF0000UL /**< Bit mask for MVP_FAULTLOOP */
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#define _MVP_FAULTSTATUS_FAULTLOOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */
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#define MVP_FAULTSTATUS_FAULTLOOP_DEFAULT (_MVP_FAULTSTATUS_FAULTLOOP_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */
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/* Bit fields for MVP FAULTADDR */
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#define _MVP_FAULTADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTADDR */
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#define _MVP_FAULTADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_FAULTADDR */
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#define _MVP_FAULTADDR_FAULTADDR_SHIFT 0 /**< Shift value for MVP_FAULTADDR */
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#define _MVP_FAULTADDR_FAULTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_FAULTADDR */
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#define _MVP_FAULTADDR_FAULTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTADDR */
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#define MVP_FAULTADDR_FAULTADDR_DEFAULT (_MVP_FAULTADDR_FAULTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTADDR */
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/* Bit fields for MVP PROGRAMSTATE */
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#define _MVP_PROGRAMSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_PROGRAMSTATE */
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#define _MVP_PROGRAMSTATE_MASK 0x00000007UL /**< Mask for MVP_PROGRAMSTATE */
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#define _MVP_PROGRAMSTATE_PC_SHIFT 0 /**< Shift value for MVP_PC */
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#define _MVP_PROGRAMSTATE_PC_MASK 0x7UL /**< Bit mask for MVP_PC */
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#define _MVP_PROGRAMSTATE_PC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PROGRAMSTATE */
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#define MVP_PROGRAMSTATE_PC_DEFAULT (_MVP_PROGRAMSTATE_PC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PROGRAMSTATE */
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/* Bit fields for MVP ARRAYINDEXSTATE */
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#define _MVP_ARRAYINDEXSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYINDEXSTATE */
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#define _MVP_ARRAYINDEXSTATE_MASK 0x3FFFFFFFUL /**< Mask for MVP_ARRAYINDEXSTATE */
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#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_SHIFT 0 /**< Shift value for MVP_DIM0INDEX */
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#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_MASK 0x3FFUL /**< Bit mask for MVP_DIM0INDEX */
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#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */
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#define MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/
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#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_SHIFT 10 /**< Shift value for MVP_DIM1INDEX */
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#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_MASK 0xFFC00UL /**< Bit mask for MVP_DIM1INDEX */
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#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */
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#define MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/
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#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_SHIFT 20 /**< Shift value for MVP_DIM2INDEX */
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#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_MASK 0x3FF00000UL /**< Bit mask for MVP_DIM2INDEX */
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#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */
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#define MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/
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/* Bit fields for MVP LOOPSTATE */
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#define _MVP_LOOPSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPSTATE */
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#define _MVP_LOOPSTATE_MASK 0x000713FFUL /**< Mask for MVP_LOOPSTATE */
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#define _MVP_LOOPSTATE_CNT_SHIFT 0 /**< Shift value for MVP_CNT */
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#define _MVP_LOOPSTATE_CNT_MASK 0x3FFUL /**< Bit mask for MVP_CNT */
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#define _MVP_LOOPSTATE_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */
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#define MVP_LOOPSTATE_CNT_DEFAULT (_MVP_LOOPSTATE_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */
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#define MVP_LOOPSTATE_ACTIVE (0x1UL << 12) /**< Loop Active */
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#define _MVP_LOOPSTATE_ACTIVE_SHIFT 12 /**< Shift value for MVP_ACTIVE */
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#define _MVP_LOOPSTATE_ACTIVE_MASK 0x1000UL /**< Bit mask for MVP_ACTIVE */
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#define _MVP_LOOPSTATE_ACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */
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#define MVP_LOOPSTATE_ACTIVE_DEFAULT (_MVP_LOOPSTATE_ACTIVE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */
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#define _MVP_LOOPSTATE_PCBEGIN_SHIFT 16 /**< Shift value for MVP_PCBEGIN */
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#define _MVP_LOOPSTATE_PCBEGIN_MASK 0x70000UL /**< Bit mask for MVP_PCBEGIN */
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#define _MVP_LOOPSTATE_PCBEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */
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#define MVP_LOOPSTATE_PCBEGIN_DEFAULT (_MVP_LOOPSTATE_PCBEGIN_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */
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/* Bit fields for MVP ALUREGSTATE */
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#define _MVP_ALUREGSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ALUREGSTATE */
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#define _MVP_ALUREGSTATE_MASK 0xFFFFFFFFUL /**< Mask for MVP_ALUREGSTATE */
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#define _MVP_ALUREGSTATE_FREAL_SHIFT 0 /**< Shift value for MVP_FREAL */
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#define _MVP_ALUREGSTATE_FREAL_MASK 0xFFFFUL /**< Bit mask for MVP_FREAL */
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#define _MVP_ALUREGSTATE_FREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */
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#define MVP_ALUREGSTATE_FREAL_DEFAULT (_MVP_ALUREGSTATE_FREAL_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */
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#define _MVP_ALUREGSTATE_FIMAG_SHIFT 16 /**< Shift value for MVP_FIMAG */
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#define _MVP_ALUREGSTATE_FIMAG_MASK 0xFFFF0000UL /**< Bit mask for MVP_FIMAG */
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#define _MVP_ALUREGSTATE_FIMAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */
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#define MVP_ALUREGSTATE_FIMAG_DEFAULT (_MVP_ALUREGSTATE_FIMAG_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */
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/* Bit fields for MVP ARRAYADDRCFG */
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#define _MVP_ARRAYADDRCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYADDRCFG */
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#define _MVP_ARRAYADDRCFG_MASK 0xFFFFFFFFUL /**< Mask for MVP_ARRAYADDRCFG */
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#define _MVP_ARRAYADDRCFG_BASE_SHIFT 0 /**< Shift value for MVP_BASE */
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#define _MVP_ARRAYADDRCFG_BASE_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_BASE */
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#define _MVP_ARRAYADDRCFG_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYADDRCFG */
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#define MVP_ARRAYADDRCFG_BASE_DEFAULT (_MVP_ARRAYADDRCFG_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYADDRCFG */
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/* Bit fields for MVP ARRAYDIM0CFG */
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#define _MVP_ARRAYDIM0CFG_RESETVALUE 0x00002000UL /**< Default value for MVP_ARRAYDIM0CFG */
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#define _MVP_ARRAYDIM0CFG_MASK 0x0FFF73FFUL /**< Mask for MVP_ARRAYDIM0CFG */
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#define _MVP_ARRAYDIM0CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */
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#define _MVP_ARRAYDIM0CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */
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#define _MVP_ARRAYDIM0CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */
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#define MVP_ARRAYDIM0CFG_SIZE_DEFAULT (_MVP_ARRAYDIM0CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */
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#define _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT 12 /**< Shift value for MVP_BASETYPE */
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#define _MVP_ARRAYDIM0CFG_BASETYPE_MASK 0x3000UL /**< Bit mask for MVP_BASETYPE */
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#define _MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */
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#define _MVP_ARRAYDIM0CFG_BASETYPE_UINT8 0x00000000UL /**< Mode UINT8 for MVP_ARRAYDIM0CFG */
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#define _MVP_ARRAYDIM0CFG_BASETYPE_INT8 0x00000001UL /**< Mode INT8 for MVP_ARRAYDIM0CFG */
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#define _MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 0x00000002UL /**< Mode BINARY16 for MVP_ARRAYDIM0CFG */
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#define _MVP_ARRAYDIM0CFG_BASETYPE_RESERVED 0x00000003UL /**< Mode RESERVED for MVP_ARRAYDIM0CFG */
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#define MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT (_MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */
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#define MVP_ARRAYDIM0CFG_BASETYPE_UINT8 (_MVP_ARRAYDIM0CFG_BASETYPE_UINT8 << 12) /**< Shifted mode UINT8 for MVP_ARRAYDIM0CFG */
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#define MVP_ARRAYDIM0CFG_BASETYPE_INT8 (_MVP_ARRAYDIM0CFG_BASETYPE_INT8 << 12) /**< Shifted mode INT8 for MVP_ARRAYDIM0CFG */
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#define MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 (_MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 << 12) /**< Shifted mode BINARY16 for MVP_ARRAYDIM0CFG */
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#define MVP_ARRAYDIM0CFG_COMPLEX (0x1UL << 14) /**< Complex Data Type */
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#define _MVP_ARRAYDIM0CFG_COMPLEX_SHIFT 14 /**< Shift value for MVP_COMPLEX */
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#define _MVP_ARRAYDIM0CFG_COMPLEX_MASK 0x4000UL /**< Bit mask for MVP_COMPLEX */
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#define _MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */
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#define _MVP_ARRAYDIM0CFG_COMPLEX_SCALAR 0x00000000UL /**< Mode SCALAR for MVP_ARRAYDIM0CFG */
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#define _MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX 0x00000001UL /**< Mode COMPLEX for MVP_ARRAYDIM0CFG */
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#define MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT (_MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */
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#define MVP_ARRAYDIM0CFG_COMPLEX_SCALAR (_MVP_ARRAYDIM0CFG_COMPLEX_SCALAR << 14) /**< Shifted mode SCALAR for MVP_ARRAYDIM0CFG */
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#define MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX (_MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX << 14) /**< Shifted mode COMPLEX for MVP_ARRAYDIM0CFG */
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#define _MVP_ARRAYDIM0CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */
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#define _MVP_ARRAYDIM0CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */
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#define _MVP_ARRAYDIM0CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */
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#define MVP_ARRAYDIM0CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM0CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */
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/* Bit fields for MVP ARRAYDIM1CFG */
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#define _MVP_ARRAYDIM1CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM1CFG */
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#define _MVP_ARRAYDIM1CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM1CFG */
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#define _MVP_ARRAYDIM1CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */
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#define _MVP_ARRAYDIM1CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */
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#define _MVP_ARRAYDIM1CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */
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#define MVP_ARRAYDIM1CFG_SIZE_DEFAULT (_MVP_ARRAYDIM1CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */
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#define _MVP_ARRAYDIM1CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */
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#define _MVP_ARRAYDIM1CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */
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#define _MVP_ARRAYDIM1CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */
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#define MVP_ARRAYDIM1CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM1CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */
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/* Bit fields for MVP ARRAYDIM2CFG */
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#define _MVP_ARRAYDIM2CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM2CFG */
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#define _MVP_ARRAYDIM2CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM2CFG */
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#define _MVP_ARRAYDIM2CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */
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#define _MVP_ARRAYDIM2CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */
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#define _MVP_ARRAYDIM2CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */
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#define MVP_ARRAYDIM2CFG_SIZE_DEFAULT (_MVP_ARRAYDIM2CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */
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#define _MVP_ARRAYDIM2CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */
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#define _MVP_ARRAYDIM2CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */
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#define _MVP_ARRAYDIM2CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */
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#define MVP_ARRAYDIM2CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM2CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */
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/* Bit fields for MVP LOOPCFG */
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#define _MVP_LOOPCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPCFG */
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#define _MVP_LOOPCFG_MASK 0x777773FFUL /**< Mask for MVP_LOOPCFG */
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#define _MVP_LOOPCFG_NUMITERS_SHIFT 0 /**< Shift value for MVP_NUMITERS */
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#define _MVP_LOOPCFG_NUMITERS_MASK 0x3FFUL /**< Bit mask for MVP_NUMITERS */
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#define _MVP_LOOPCFG_NUMITERS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_NUMITERS_DEFAULT (_MVP_LOOPCFG_NUMITERS_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY0INCRDIM0 (0x1UL << 12) /**< Increment Dimension 0 */
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#define _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0INCRDIM0 */
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#define _MVP_LOOPCFG_ARRAY0INCRDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0INCRDIM0 */
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#define _MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY0INCRDIM1 (0x1UL << 13) /**< Increment Dimension 1 */
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#define _MVP_LOOPCFG_ARRAY0INCRDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0INCRDIM1 */
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#define _MVP_LOOPCFG_ARRAY0INCRDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0INCRDIM1 */
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#define _MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY0INCRDIM2 (0x1UL << 14) /**< Increment Dimension 2 */
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#define _MVP_LOOPCFG_ARRAY0INCRDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0INCRDIM2 */
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#define _MVP_LOOPCFG_ARRAY0INCRDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0INCRDIM2 */
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#define _MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY1INCRDIM0 (0x1UL << 16) /**< Increment Dimension 0 */
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#define _MVP_LOOPCFG_ARRAY1INCRDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1INCRDIM0 */
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#define _MVP_LOOPCFG_ARRAY1INCRDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1INCRDIM0 */
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#define _MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY1INCRDIM1 (0x1UL << 17) /**< Increment Dimension 1 */
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#define _MVP_LOOPCFG_ARRAY1INCRDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1INCRDIM1 */
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#define _MVP_LOOPCFG_ARRAY1INCRDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1INCRDIM1 */
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#define _MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY1INCRDIM2 (0x1UL << 18) /**< Increment Dimension 2 */
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#define _MVP_LOOPCFG_ARRAY1INCRDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1INCRDIM2 */
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#define _MVP_LOOPCFG_ARRAY1INCRDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1INCRDIM2 */
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#define _MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY2INCRDIM0 (0x1UL << 20) /**< Increment Dimension 0 */
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#define _MVP_LOOPCFG_ARRAY2INCRDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2INCRDIM0 */
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#define _MVP_LOOPCFG_ARRAY2INCRDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2INCRDIM0 */
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#define _MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY2INCRDIM1 (0x1UL << 21) /**< Increment Dimension 1 */
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#define _MVP_LOOPCFG_ARRAY2INCRDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2INCRDIM1 */
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#define _MVP_LOOPCFG_ARRAY2INCRDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2INCRDIM1 */
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#define _MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY2INCRDIM2 (0x1UL << 22) /**< Increment Dimension 2 */
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#define _MVP_LOOPCFG_ARRAY2INCRDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2INCRDIM2 */
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#define _MVP_LOOPCFG_ARRAY2INCRDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2INCRDIM2 */
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#define _MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY3INCRDIM0 (0x1UL << 24) /**< Increment Dimension 0 */
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#define _MVP_LOOPCFG_ARRAY3INCRDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3INCRDIM0 */
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#define _MVP_LOOPCFG_ARRAY3INCRDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3INCRDIM0 */
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#define _MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY3INCRDIM1 (0x1UL << 25) /**< Increment Dimension 1 */
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#define _MVP_LOOPCFG_ARRAY3INCRDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3INCRDIM1 */
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#define _MVP_LOOPCFG_ARRAY3INCRDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3INCRDIM1 */
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#define _MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY3INCRDIM2 (0x1UL << 26) /**< Increment Dimension 2 */
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#define _MVP_LOOPCFG_ARRAY3INCRDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3INCRDIM2 */
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#define _MVP_LOOPCFG_ARRAY3INCRDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3INCRDIM2 */
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#define _MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY4INCRDIM0 (0x1UL << 28) /**< Increment Dimension 0 */
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#define _MVP_LOOPCFG_ARRAY4INCRDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4INCRDIM0 */
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#define _MVP_LOOPCFG_ARRAY4INCRDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4INCRDIM0 */
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#define _MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY4INCRDIM1 (0x1UL << 29) /**< Increment Dimension 1 */
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#define _MVP_LOOPCFG_ARRAY4INCRDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4INCRDIM1 */
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#define _MVP_LOOPCFG_ARRAY4INCRDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4INCRDIM1 */
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#define _MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY4INCRDIM2 (0x1UL << 30) /**< Increment Dimension 2 */
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#define _MVP_LOOPCFG_ARRAY4INCRDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4INCRDIM2 */
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#define _MVP_LOOPCFG_ARRAY4INCRDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4INCRDIM2 */
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#define _MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
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#define MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
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/* Bit fields for MVP LOOPRST */
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#define _MVP_LOOPRST_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPRST */
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#define _MVP_LOOPRST_MASK 0x77777000UL /**< Mask for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY0RESETDIM0 (0x1UL << 12) /**< Reset Dimension 0 */
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#define _MVP_LOOPRST_ARRAY0RESETDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0RESETDIM0 */
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#define _MVP_LOOPRST_ARRAY0RESETDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0RESETDIM0 */
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#define _MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY0RESETDIM1 (0x1UL << 13) /**< Reset Dimension 1 */
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#define _MVP_LOOPRST_ARRAY0RESETDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0RESETDIM1 */
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#define _MVP_LOOPRST_ARRAY0RESETDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0RESETDIM1 */
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#define _MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY0RESETDIM2 (0x1UL << 14) /**< Reset Dimension 2 */
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#define _MVP_LOOPRST_ARRAY0RESETDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0RESETDIM2 */
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#define _MVP_LOOPRST_ARRAY0RESETDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0RESETDIM2 */
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#define _MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY1RESETDIM0 (0x1UL << 16) /**< Reset Dimension 0 */
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#define _MVP_LOOPRST_ARRAY1RESETDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1RESETDIM0 */
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#define _MVP_LOOPRST_ARRAY1RESETDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1RESETDIM0 */
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#define _MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY1RESETDIM1 (0x1UL << 17) /**< Reset Dimension 1 */
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#define _MVP_LOOPRST_ARRAY1RESETDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1RESETDIM1 */
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#define _MVP_LOOPRST_ARRAY1RESETDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1RESETDIM1 */
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#define _MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY1RESETDIM2 (0x1UL << 18) /**< Reset Dimension 2 */
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#define _MVP_LOOPRST_ARRAY1RESETDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1RESETDIM2 */
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#define _MVP_LOOPRST_ARRAY1RESETDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1RESETDIM2 */
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#define _MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY2RESETDIM0 (0x1UL << 20) /**< Reset Dimension 0 */
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#define _MVP_LOOPRST_ARRAY2RESETDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2RESETDIM0 */
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#define _MVP_LOOPRST_ARRAY2RESETDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2RESETDIM0 */
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#define _MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY2RESETDIM1 (0x1UL << 21) /**< Reset Dimension 1 */
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#define _MVP_LOOPRST_ARRAY2RESETDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2RESETDIM1 */
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#define _MVP_LOOPRST_ARRAY2RESETDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2RESETDIM1 */
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#define _MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY2RESETDIM2 (0x1UL << 22) /**< Reset Dimension 2 */
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#define _MVP_LOOPRST_ARRAY2RESETDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2RESETDIM2 */
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#define _MVP_LOOPRST_ARRAY2RESETDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2RESETDIM2 */
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#define _MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY3RESETDIM0 (0x1UL << 24) /**< Reset Dimension 0 */
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#define _MVP_LOOPRST_ARRAY3RESETDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3RESETDIM0 */
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#define _MVP_LOOPRST_ARRAY3RESETDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3RESETDIM0 */
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#define _MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY3RESETDIM1 (0x1UL << 25) /**< Reset Dimension 1 */
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#define _MVP_LOOPRST_ARRAY3RESETDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3RESETDIM1 */
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#define _MVP_LOOPRST_ARRAY3RESETDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3RESETDIM1 */
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#define _MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY3RESETDIM2 (0x1UL << 26) /**< Reset Dimension 2 */
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#define _MVP_LOOPRST_ARRAY3RESETDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3RESETDIM2 */
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#define _MVP_LOOPRST_ARRAY3RESETDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3RESETDIM2 */
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#define _MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY4RESETDIM0 (0x1UL << 28) /**< Reset Dimension 0 */
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#define _MVP_LOOPRST_ARRAY4RESETDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4RESETDIM0 */
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#define _MVP_LOOPRST_ARRAY4RESETDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4RESETDIM0 */
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#define _MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY4RESETDIM1 (0x1UL << 29) /**< Reset Dimension 1 */
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#define _MVP_LOOPRST_ARRAY4RESETDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4RESETDIM1 */
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#define _MVP_LOOPRST_ARRAY4RESETDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4RESETDIM1 */
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#define _MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY4RESETDIM2 (0x1UL << 30) /**< Reset Dimension 2 */
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#define _MVP_LOOPRST_ARRAY4RESETDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4RESETDIM2 */
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#define _MVP_LOOPRST_ARRAY4RESETDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4RESETDIM2 */
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#define _MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
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#define MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPRST */
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/* Bit fields for MVP INSTRCFG0 */
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#define _MVP_INSTRCFG0_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG0 */
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#define _MVP_INSTRCFG0_MASK 0x70F7F7F7UL /**< Mask for MVP_INSTRCFG0 */
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#define _MVP_INSTRCFG0_ALUIN0REGID_SHIFT 0 /**< Shift value for MVP_ALUIN0REGID */
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#define _MVP_INSTRCFG0_ALUIN0REGID_MASK 0x7UL /**< Bit mask for MVP_ALUIN0REGID */
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#define _MVP_INSTRCFG0_ALUIN0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN0REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN0REALZERO (0x1UL << 4) /**< Real Zero */
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#define _MVP_INSTRCFG0_ALUIN0REALZERO_SHIFT 4 /**< Shift value for MVP_ALUIN0REALZERO */
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#define _MVP_INSTRCFG0_ALUIN0REALZERO_MASK 0x10UL /**< Bit mask for MVP_ALUIN0REALZERO */
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#define _MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN0REALNEGATE (0x1UL << 5) /**< Real Negate */
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#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_SHIFT 5 /**< Shift value for MVP_ALUIN0REALNEGATE */
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#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_MASK 0x20UL /**< Bit mask for MVP_ALUIN0REALNEGATE */
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#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN0IMAGZERO (0x1UL << 6) /**< Imaginary Not Zero */
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#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_SHIFT 6 /**< Shift value for MVP_ALUIN0IMAGZERO */
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#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_MASK 0x40UL /**< Bit mask for MVP_ALUIN0IMAGZERO */
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#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE (0x1UL << 7) /**< Imaginary Negate */
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#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_SHIFT 7 /**< Shift value for MVP_ALUIN0IMAGNEGATE */
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#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_MASK 0x80UL /**< Bit mask for MVP_ALUIN0IMAGNEGATE */
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#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define _MVP_INSTRCFG0_ALUIN1REGID_SHIFT 8 /**< Shift value for MVP_ALUIN1REGID */
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#define _MVP_INSTRCFG0_ALUIN1REGID_MASK 0x700UL /**< Bit mask for MVP_ALUIN1REGID */
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#define _MVP_INSTRCFG0_ALUIN1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN1REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN1REGID_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN1REALZERO (0x1UL << 12) /**< Real Zero */
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#define _MVP_INSTRCFG0_ALUIN1REALZERO_SHIFT 12 /**< Shift value for MVP_ALUIN1REALZERO */
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#define _MVP_INSTRCFG0_ALUIN1REALZERO_MASK 0x1000UL /**< Bit mask for MVP_ALUIN1REALZERO */
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#define _MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN1REALNEGATE (0x1UL << 13) /**< Real Negate */
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#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_SHIFT 13 /**< Shift value for MVP_ALUIN1REALNEGATE */
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#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_MASK 0x2000UL /**< Bit mask for MVP_ALUIN1REALNEGATE */
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#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN1IMAGZERO (0x1UL << 14) /**< Imaginary Not Zero */
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#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_SHIFT 14 /**< Shift value for MVP_ALUIN1IMAGZERO */
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#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_MASK 0x4000UL /**< Bit mask for MVP_ALUIN1IMAGZERO */
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#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE (0x1UL << 15) /**< Imaginary Negate */
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#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_SHIFT 15 /**< Shift value for MVP_ALUIN1IMAGNEGATE */
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#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_MASK 0x8000UL /**< Bit mask for MVP_ALUIN1IMAGNEGATE */
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#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define _MVP_INSTRCFG0_ALUIN2REGID_SHIFT 16 /**< Shift value for MVP_ALUIN2REGID */
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#define _MVP_INSTRCFG0_ALUIN2REGID_MASK 0x70000UL /**< Bit mask for MVP_ALUIN2REGID */
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#define _MVP_INSTRCFG0_ALUIN2REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN2REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN2REGID_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN2REALZERO (0x1UL << 20) /**< Real Zero */
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#define _MVP_INSTRCFG0_ALUIN2REALZERO_SHIFT 20 /**< Shift value for MVP_ALUIN2REALZERO */
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#define _MVP_INSTRCFG0_ALUIN2REALZERO_MASK 0x100000UL /**< Bit mask for MVP_ALUIN2REALZERO */
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#define _MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN2REALNEGATE (0x1UL << 21) /**< Real Negate */
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#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_SHIFT 21 /**< Shift value for MVP_ALUIN2REALNEGATE */
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#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_MASK 0x200000UL /**< Bit mask for MVP_ALUIN2REALNEGATE */
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#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN2IMAGZERO (0x1UL << 22) /**< Imaginary Not Zero */
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#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_SHIFT 22 /**< Shift value for MVP_ALUIN2IMAGZERO */
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#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_MASK 0x400000UL /**< Bit mask for MVP_ALUIN2IMAGZERO */
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#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE (0x1UL << 23) /**< Imaginary Negate */
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#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_SHIFT 23 /**< Shift value for MVP_ALUIN2IMAGNEGATE */
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#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_MASK 0x800000UL /**< Bit mask for MVP_ALUIN2IMAGNEGATE */
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#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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#define _MVP_INSTRCFG0_ALUOUTREGID_SHIFT 28 /**< Shift value for MVP_ALUOUTREGID */
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#define _MVP_INSTRCFG0_ALUOUTREGID_MASK 0x70000000UL /**< Bit mask for MVP_ALUOUTREGID */
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#define _MVP_INSTRCFG0_ALUOUTREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
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#define MVP_INSTRCFG0_ALUOUTREGID_DEFAULT (_MVP_INSTRCFG0_ALUOUTREGID_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
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/* Bit fields for MVP INSTRCFG1 */
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#define _MVP_INSTRCFG1_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG1 */
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#define _MVP_INSTRCFG1_MASK 0x3FFFFFFFUL /**< Mask for MVP_INSTRCFG1 */
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#define _MVP_INSTRCFG1_ISTREAM0REGID_SHIFT 0 /**< Shift value for MVP_ISTREAM0REGID */
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#define _MVP_INSTRCFG1_ISTREAM0REGID_MASK 0x7UL /**< Bit mask for MVP_ISTREAM0REGID */
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#define _MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT (_MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM0LOAD (0x1UL << 3) /**< Load register */
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#define _MVP_INSTRCFG1_ISTREAM0LOAD_SHIFT 3 /**< Shift value for MVP_ISTREAM0LOAD */
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#define _MVP_INSTRCFG1_ISTREAM0LOAD_MASK 0x8UL /**< Bit mask for MVP_ISTREAM0LOAD */
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#define _MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT (_MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_SHIFT 4 /**< Shift value for MVP_ISTREAM0ARRAYID */
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#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_MASK 0x70UL /**< Bit mask for MVP_ISTREAM0ARRAYID */
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#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0 (0x1UL << 7) /**< Increment Array Dimension 0 */
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#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_SHIFT 7 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM0 */
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#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_MASK 0x80UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM0 */
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#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1 (0x1UL << 8) /**< Increment Array Dimension 1 */
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#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_SHIFT 8 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM1 */
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#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_MASK 0x100UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM1 */
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#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2 (0x1UL << 9) /**< Increment Array Dimension 2 */
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#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_SHIFT 9 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM2 */
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#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_MASK 0x200UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM2 */
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#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define _MVP_INSTRCFG1_ISTREAM1REGID_SHIFT 10 /**< Shift value for MVP_ISTREAM1REGID */
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#define _MVP_INSTRCFG1_ISTREAM1REGID_MASK 0x1C00UL /**< Bit mask for MVP_ISTREAM1REGID */
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#define _MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT (_MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM1LOAD (0x1UL << 13) /**< Load register */
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#define _MVP_INSTRCFG1_ISTREAM1LOAD_SHIFT 13 /**< Shift value for MVP_ISTREAM1LOAD */
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#define _MVP_INSTRCFG1_ISTREAM1LOAD_MASK 0x2000UL /**< Bit mask for MVP_ISTREAM1LOAD */
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#define _MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT (_MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_SHIFT 14 /**< Shift value for MVP_ISTREAM1ARRAYID */
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#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_MASK 0x1C000UL /**< Bit mask for MVP_ISTREAM1ARRAYID */
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#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0 (0x1UL << 17) /**< Increment Array Dimension 0 */
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#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_SHIFT 17 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM0 */
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#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_MASK 0x20000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM0 */
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#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1 (0x1UL << 18) /**< Increment Array Dimension 1 */
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#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_SHIFT 18 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM1 */
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#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_MASK 0x40000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM1 */
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#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2 (0x1UL << 19) /**< Increment Array Dimension 2 */
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#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_SHIFT 19 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM2 */
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#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_MASK 0x80000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM2 */
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#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define _MVP_INSTRCFG1_OSTREAMREGID_SHIFT 20 /**< Shift value for MVP_OSTREAMREGID */
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#define _MVP_INSTRCFG1_OSTREAMREGID_MASK 0x700000UL /**< Bit mask for MVP_OSTREAMREGID */
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#define _MVP_INSTRCFG1_OSTREAMREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_OSTREAMREGID_DEFAULT (_MVP_INSTRCFG1_OSTREAMREGID_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_OSTREAMSTORE (0x1UL << 23) /**< Store to Register */
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#define _MVP_INSTRCFG1_OSTREAMSTORE_SHIFT 23 /**< Shift value for MVP_OSTREAMSTORE */
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#define _MVP_INSTRCFG1_OSTREAMSTORE_MASK 0x800000UL /**< Bit mask for MVP_OSTREAMSTORE */
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#define _MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT (_MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define _MVP_INSTRCFG1_OSTREAMARRAYID_SHIFT 24 /**< Shift value for MVP_OSTREAMARRAYID */
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#define _MVP_INSTRCFG1_OSTREAMARRAYID_MASK 0x7000000UL /**< Bit mask for MVP_OSTREAMARRAYID */
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#define _MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0 (0x1UL << 27) /**< Increment Array Dimension 0 */
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#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_SHIFT 27 /**< Shift value for MVP_OSTREAMARRAYINCRDIM0 */
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#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_MASK 0x8000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM0 */
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#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1 (0x1UL << 28) /**< Increment Array Dimension 1 */
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#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_SHIFT 28 /**< Shift value for MVP_OSTREAMARRAYINCRDIM1 */
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#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_MASK 0x10000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM1 */
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#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2 (0x1UL << 29) /**< Increment Array Dimension 2 */
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#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_SHIFT 29 /**< Shift value for MVP_OSTREAMARRAYINCRDIM2 */
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#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_MASK 0x20000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM2 */
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#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
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#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
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/* Bit fields for MVP INSTRCFG2 */
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#define _MVP_INSTRCFG2_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_MASK 0x9FF0FFFFUL /**< Mask for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP0BEGIN (0x1UL << 0) /**< Loop Begin */
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#define _MVP_INSTRCFG2_LOOP0BEGIN_SHIFT 0 /**< Shift value for MVP_LOOP0BEGIN */
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#define _MVP_INSTRCFG2_LOOP0BEGIN_MASK 0x1UL /**< Bit mask for MVP_LOOP0BEGIN */
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#define _MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP0END (0x1UL << 1) /**< Loop End */
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#define _MVP_INSTRCFG2_LOOP0END_SHIFT 1 /**< Shift value for MVP_LOOP0END */
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#define _MVP_INSTRCFG2_LOOP0END_MASK 0x2UL /**< Bit mask for MVP_LOOP0END */
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#define _MVP_INSTRCFG2_LOOP0END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP0END_DEFAULT (_MVP_INSTRCFG2_LOOP0END_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP1BEGIN (0x1UL << 2) /**< Loop Begin */
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#define _MVP_INSTRCFG2_LOOP1BEGIN_SHIFT 2 /**< Shift value for MVP_LOOP1BEGIN */
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#define _MVP_INSTRCFG2_LOOP1BEGIN_MASK 0x4UL /**< Bit mask for MVP_LOOP1BEGIN */
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#define _MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP1END (0x1UL << 3) /**< Loop End */
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#define _MVP_INSTRCFG2_LOOP1END_SHIFT 3 /**< Shift value for MVP_LOOP1END */
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#define _MVP_INSTRCFG2_LOOP1END_MASK 0x8UL /**< Bit mask for MVP_LOOP1END */
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#define _MVP_INSTRCFG2_LOOP1END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP1END_DEFAULT (_MVP_INSTRCFG2_LOOP1END_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP2BEGIN (0x1UL << 4) /**< Loop Begin */
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#define _MVP_INSTRCFG2_LOOP2BEGIN_SHIFT 4 /**< Shift value for MVP_LOOP2BEGIN */
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#define _MVP_INSTRCFG2_LOOP2BEGIN_MASK 0x10UL /**< Bit mask for MVP_LOOP2BEGIN */
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#define _MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP2END (0x1UL << 5) /**< Loop End */
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#define _MVP_INSTRCFG2_LOOP2END_SHIFT 5 /**< Shift value for MVP_LOOP2END */
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#define _MVP_INSTRCFG2_LOOP2END_MASK 0x20UL /**< Bit mask for MVP_LOOP2END */
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#define _MVP_INSTRCFG2_LOOP2END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP2END_DEFAULT (_MVP_INSTRCFG2_LOOP2END_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP3BEGIN (0x1UL << 6) /**< Loop Begin */
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#define _MVP_INSTRCFG2_LOOP3BEGIN_SHIFT 6 /**< Shift value for MVP_LOOP3BEGIN */
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#define _MVP_INSTRCFG2_LOOP3BEGIN_MASK 0x40UL /**< Bit mask for MVP_LOOP3BEGIN */
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#define _MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP3END (0x1UL << 7) /**< Loop End */
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#define _MVP_INSTRCFG2_LOOP3END_SHIFT 7 /**< Shift value for MVP_LOOP3END */
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#define _MVP_INSTRCFG2_LOOP3END_MASK 0x80UL /**< Bit mask for MVP_LOOP3END */
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#define _MVP_INSTRCFG2_LOOP3END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP3END_DEFAULT (_MVP_INSTRCFG2_LOOP3END_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP4BEGIN (0x1UL << 8) /**< Loop Begin */
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#define _MVP_INSTRCFG2_LOOP4BEGIN_SHIFT 8 /**< Shift value for MVP_LOOP4BEGIN */
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#define _MVP_INSTRCFG2_LOOP4BEGIN_MASK 0x100UL /**< Bit mask for MVP_LOOP4BEGIN */
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#define _MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP4END (0x1UL << 9) /**< Loop End */
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#define _MVP_INSTRCFG2_LOOP4END_SHIFT 9 /**< Shift value for MVP_LOOP4END */
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#define _MVP_INSTRCFG2_LOOP4END_MASK 0x200UL /**< Bit mask for MVP_LOOP4END */
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#define _MVP_INSTRCFG2_LOOP4END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP4END_DEFAULT (_MVP_INSTRCFG2_LOOP4END_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP5BEGIN (0x1UL << 10) /**< Loop Begin */
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#define _MVP_INSTRCFG2_LOOP5BEGIN_SHIFT 10 /**< Shift value for MVP_LOOP5BEGIN */
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#define _MVP_INSTRCFG2_LOOP5BEGIN_MASK 0x400UL /**< Bit mask for MVP_LOOP5BEGIN */
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#define _MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP5END (0x1UL << 11) /**< Loop End */
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#define _MVP_INSTRCFG2_LOOP5END_SHIFT 11 /**< Shift value for MVP_LOOP5END */
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#define _MVP_INSTRCFG2_LOOP5END_MASK 0x800UL /**< Bit mask for MVP_LOOP5END */
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#define _MVP_INSTRCFG2_LOOP5END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP5END_DEFAULT (_MVP_INSTRCFG2_LOOP5END_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP6BEGIN (0x1UL << 12) /**< Loop Begin */
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#define _MVP_INSTRCFG2_LOOP6BEGIN_SHIFT 12 /**< Shift value for MVP_LOOP6BEGIN */
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#define _MVP_INSTRCFG2_LOOP6BEGIN_MASK 0x1000UL /**< Bit mask for MVP_LOOP6BEGIN */
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#define _MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP6END (0x1UL << 13) /**< Loop End */
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#define _MVP_INSTRCFG2_LOOP6END_SHIFT 13 /**< Shift value for MVP_LOOP6END */
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#define _MVP_INSTRCFG2_LOOP6END_MASK 0x2000UL /**< Bit mask for MVP_LOOP6END */
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#define _MVP_INSTRCFG2_LOOP6END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP6END_DEFAULT (_MVP_INSTRCFG2_LOOP6END_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP7BEGIN (0x1UL << 14) /**< Loop Begin */
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#define _MVP_INSTRCFG2_LOOP7BEGIN_SHIFT 14 /**< Shift value for MVP_LOOP7BEGIN */
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#define _MVP_INSTRCFG2_LOOP7BEGIN_MASK 0x4000UL /**< Bit mask for MVP_LOOP7BEGIN */
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#define _MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP7END (0x1UL << 15) /**< Loop End */
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#define _MVP_INSTRCFG2_LOOP7END_SHIFT 15 /**< Shift value for MVP_LOOP7END */
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#define _MVP_INSTRCFG2_LOOP7END_MASK 0x8000UL /**< Bit mask for MVP_LOOP7END */
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#define _MVP_INSTRCFG2_LOOP7END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_LOOP7END_DEFAULT (_MVP_INSTRCFG2_LOOP7END_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_SHIFT 20 /**< Shift value for MVP_ALUOP */
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#define _MVP_INSTRCFG2_ALUOP_MASK 0x1FF00000UL /**< Bit mask for MVP_ALUOP */
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#define _MVP_INSTRCFG2_ALUOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_NOOP 0x00000000UL /**< Mode NOOP for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_CLEAR 0x00000001UL /**< Mode CLEAR for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_COPY 0x00000041UL /**< Mode COPY for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_SWAP 0x00000042UL /**< Mode SWAP for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_DBL 0x00000043UL /**< Mode DBL for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_FANA 0x00000044UL /**< Mode FANA for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_FANB 0x00000045UL /**< Mode FANB for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_RELU2 0x00000046UL /**< Mode RELU2 for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_NRELU2 0x00000047UL /**< Mode NRELU2 for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_INC2 0x00000048UL /**< Mode INC2 for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_DEC2 0x00000049UL /**< Mode DEC2 for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_ADDR 0x0000004AUL /**< Mode ADDR for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MAX 0x0000004BUL /**< Mode MAX for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MIN 0x0000004CUL /**< Mode MIN for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_RSQR2B 0x00000124UL /**< Mode RSQR2B for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_ADDC 0x0000014EUL /**< Mode ADDC for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MAX2A 0x00000153UL /**< Mode MAX2A for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MIN2A 0x00000154UL /**< Mode MIN2A for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_XREALC2 0x0000015EUL /**< Mode XREALC2 for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_XIMAGC2 0x0000015FUL /**< Mode XIMAGC2 for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_ADDR2B 0x00000161UL /**< Mode ADDR2B for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MAX2B 0x00000162UL /**< Mode MAX2B for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MIN2B 0x00000163UL /**< Mode MIN2B for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MULC 0x0000018DUL /**< Mode MULC for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MULR2A 0x00000197UL /**< Mode MULR2A for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MULR2B 0x00000198UL /**< Mode MULR2B for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_ADDR4 0x0000019AUL /**< Mode ADDR4 for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MAX4 0x0000019BUL /**< Mode MAX4 for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MIN4 0x0000019CUL /**< Mode MIN4 for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_SQRMAGC2 0x0000019DUL /**< Mode SQRMAGC2 for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_PRELU2B 0x000001A0UL /**< Mode PRELU2B for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MACC 0x000001CDUL /**< Mode MACC for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_AACC 0x000001CEUL /**< Mode AACC for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_ELU2A 0x000001CFUL /**< Mode ELU2A for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_ELU2B 0x000001D0UL /**< Mode ELU2B for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_IFR2A 0x000001D1UL /**< Mode IFR2A for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_IFR2B 0x000001D2UL /**< Mode IFR2B for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MAXAC2 0x000001D3UL /**< Mode MAXAC2 for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MINAC2 0x000001D4UL /**< Mode MINAC2 for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_CLIP2A 0x000001D5UL /**< Mode CLIP2A for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_CLIP2B 0x000001D6UL /**< Mode CLIP2B for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MACR2A 0x000001D7UL /**< Mode MACR2A for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_MACR2B 0x000001D8UL /**< Mode MACR2B for MVP_INSTRCFG2 */
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#define _MVP_INSTRCFG2_ALUOP_IFC 0x000001D9UL /**< Mode IFC for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_DEFAULT (_MVP_INSTRCFG2_ALUOP_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_NOOP (_MVP_INSTRCFG2_ALUOP_NOOP << 20) /**< Shifted mode NOOP for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_CLEAR (_MVP_INSTRCFG2_ALUOP_CLEAR << 20) /**< Shifted mode CLEAR for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_COPY (_MVP_INSTRCFG2_ALUOP_COPY << 20) /**< Shifted mode COPY for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_SWAP (_MVP_INSTRCFG2_ALUOP_SWAP << 20) /**< Shifted mode SWAP for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_DBL (_MVP_INSTRCFG2_ALUOP_DBL << 20) /**< Shifted mode DBL for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_FANA (_MVP_INSTRCFG2_ALUOP_FANA << 20) /**< Shifted mode FANA for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_FANB (_MVP_INSTRCFG2_ALUOP_FANB << 20) /**< Shifted mode FANB for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_RELU2 (_MVP_INSTRCFG2_ALUOP_RELU2 << 20) /**< Shifted mode RELU2 for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_NRELU2 (_MVP_INSTRCFG2_ALUOP_NRELU2 << 20) /**< Shifted mode NRELU2 for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_INC2 (_MVP_INSTRCFG2_ALUOP_INC2 << 20) /**< Shifted mode INC2 for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_DEC2 (_MVP_INSTRCFG2_ALUOP_DEC2 << 20) /**< Shifted mode DEC2 for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_ADDR (_MVP_INSTRCFG2_ALUOP_ADDR << 20) /**< Shifted mode ADDR for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MAX (_MVP_INSTRCFG2_ALUOP_MAX << 20) /**< Shifted mode MAX for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MIN (_MVP_INSTRCFG2_ALUOP_MIN << 20) /**< Shifted mode MIN for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_RSQR2B (_MVP_INSTRCFG2_ALUOP_RSQR2B << 20) /**< Shifted mode RSQR2B for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_ADDC (_MVP_INSTRCFG2_ALUOP_ADDC << 20) /**< Shifted mode ADDC for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MAX2A (_MVP_INSTRCFG2_ALUOP_MAX2A << 20) /**< Shifted mode MAX2A for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MIN2A (_MVP_INSTRCFG2_ALUOP_MIN2A << 20) /**< Shifted mode MIN2A for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_XREALC2 (_MVP_INSTRCFG2_ALUOP_XREALC2 << 20) /**< Shifted mode XREALC2 for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_XIMAGC2 (_MVP_INSTRCFG2_ALUOP_XIMAGC2 << 20) /**< Shifted mode XIMAGC2 for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_ADDR2B (_MVP_INSTRCFG2_ALUOP_ADDR2B << 20) /**< Shifted mode ADDR2B for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MAX2B (_MVP_INSTRCFG2_ALUOP_MAX2B << 20) /**< Shifted mode MAX2B for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MIN2B (_MVP_INSTRCFG2_ALUOP_MIN2B << 20) /**< Shifted mode MIN2B for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MULC (_MVP_INSTRCFG2_ALUOP_MULC << 20) /**< Shifted mode MULC for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MULR2A (_MVP_INSTRCFG2_ALUOP_MULR2A << 20) /**< Shifted mode MULR2A for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MULR2B (_MVP_INSTRCFG2_ALUOP_MULR2B << 20) /**< Shifted mode MULR2B for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_ADDR4 (_MVP_INSTRCFG2_ALUOP_ADDR4 << 20) /**< Shifted mode ADDR4 for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MAX4 (_MVP_INSTRCFG2_ALUOP_MAX4 << 20) /**< Shifted mode MAX4 for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MIN4 (_MVP_INSTRCFG2_ALUOP_MIN4 << 20) /**< Shifted mode MIN4 for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_SQRMAGC2 (_MVP_INSTRCFG2_ALUOP_SQRMAGC2 << 20) /**< Shifted mode SQRMAGC2 for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_PRELU2B (_MVP_INSTRCFG2_ALUOP_PRELU2B << 20) /**< Shifted mode PRELU2B for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MACC (_MVP_INSTRCFG2_ALUOP_MACC << 20) /**< Shifted mode MACC for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_AACC (_MVP_INSTRCFG2_ALUOP_AACC << 20) /**< Shifted mode AACC for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_ELU2A (_MVP_INSTRCFG2_ALUOP_ELU2A << 20) /**< Shifted mode ELU2A for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_ELU2B (_MVP_INSTRCFG2_ALUOP_ELU2B << 20) /**< Shifted mode ELU2B for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_IFR2A (_MVP_INSTRCFG2_ALUOP_IFR2A << 20) /**< Shifted mode IFR2A for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_IFR2B (_MVP_INSTRCFG2_ALUOP_IFR2B << 20) /**< Shifted mode IFR2B for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MAXAC2 (_MVP_INSTRCFG2_ALUOP_MAXAC2 << 20) /**< Shifted mode MAXAC2 for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MINAC2 (_MVP_INSTRCFG2_ALUOP_MINAC2 << 20) /**< Shifted mode MINAC2 for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_CLIP2A (_MVP_INSTRCFG2_ALUOP_CLIP2A << 20) /**< Shifted mode CLIP2A for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_CLIP2B (_MVP_INSTRCFG2_ALUOP_CLIP2B << 20) /**< Shifted mode CLIP2B for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MACR2A (_MVP_INSTRCFG2_ALUOP_MACR2A << 20) /**< Shifted mode MACR2A for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_MACR2B (_MVP_INSTRCFG2_ALUOP_MACR2B << 20) /**< Shifted mode MACR2B for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ALUOP_IFC (_MVP_INSTRCFG2_ALUOP_IFC << 20) /**< Shifted mode IFC for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ENDPROG (0x1UL << 31) /**< End of Program */
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#define _MVP_INSTRCFG2_ENDPROG_SHIFT 31 /**< Shift value for MVP_ENDPROG */
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#define _MVP_INSTRCFG2_ENDPROG_MASK 0x80000000UL /**< Bit mask for MVP_ENDPROG */
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#define _MVP_INSTRCFG2_ENDPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
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#define MVP_INSTRCFG2_ENDPROG_DEFAULT (_MVP_INSTRCFG2_ENDPROG_DEFAULT << 31) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
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/* Bit fields for MVP CMD */
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#define _MVP_CMD_RESETVALUE 0x00000000UL /**< Default value for MVP_CMD */
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#define _MVP_CMD_MASK 0x0000000FUL /**< Mask for MVP_CMD */
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#define MVP_CMD_START (0x1UL << 0) /**< Start Command */
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#define _MVP_CMD_START_SHIFT 0 /**< Shift value for MVP_START */
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#define _MVP_CMD_START_MASK 0x1UL /**< Bit mask for MVP_START */
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#define _MVP_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */
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#define MVP_CMD_START_DEFAULT (_MVP_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CMD */
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#define MVP_CMD_HALT (0x1UL << 1) /**< Halt Command */
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#define _MVP_CMD_HALT_SHIFT 1 /**< Shift value for MVP_HALT */
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#define _MVP_CMD_HALT_MASK 0x2UL /**< Bit mask for MVP_HALT */
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#define _MVP_CMD_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */
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#define MVP_CMD_HALT_DEFAULT (_MVP_CMD_HALT_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CMD */
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#define MVP_CMD_STEP (0x1UL << 2) /**< Step Command */
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#define _MVP_CMD_STEP_SHIFT 2 /**< Shift value for MVP_STEP */
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#define _MVP_CMD_STEP_MASK 0x4UL /**< Bit mask for MVP_STEP */
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#define _MVP_CMD_STEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */
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#define MVP_CMD_STEP_DEFAULT (_MVP_CMD_STEP_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CMD */
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#define MVP_CMD_INIT (0x1UL << 3) /**< Initialization Command/Qualifier */
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#define _MVP_CMD_INIT_SHIFT 3 /**< Shift value for MVP_INIT */
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#define _MVP_CMD_INIT_MASK 0x8UL /**< Bit mask for MVP_INIT */
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#define _MVP_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */
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#define MVP_CMD_INIT_DEFAULT (_MVP_CMD_INIT_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CMD */
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/* Bit fields for MVP DEBUGEN */
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#define _MVP_DEBUGEN_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGEN */
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#define _MVP_DEBUGEN_MASK 0x7003FDFEUL /**< Mask for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP0DONE (0x1UL << 1) /**< Enable Breakpoint on Loop Done */
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#define _MVP_DEBUGEN_BKPTLOOP0DONE_SHIFT 1 /**< Shift value for MVP_BKPTLOOP0DONE */
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#define _MVP_DEBUGEN_BKPTLOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_BKPTLOOP0DONE */
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#define _MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP1DONE (0x1UL << 2) /**< Enable Breakpoint on Loop Done */
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#define _MVP_DEBUGEN_BKPTLOOP1DONE_SHIFT 2 /**< Shift value for MVP_BKPTLOOP1DONE */
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#define _MVP_DEBUGEN_BKPTLOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_BKPTLOOP1DONE */
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#define _MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP2DONE (0x1UL << 3) /**< Enable Breakpoint on Loop Done */
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#define _MVP_DEBUGEN_BKPTLOOP2DONE_SHIFT 3 /**< Shift value for MVP_BKPTLOOP2DONE */
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#define _MVP_DEBUGEN_BKPTLOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_BKPTLOOP2DONE */
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#define _MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP3DONE (0x1UL << 4) /**< Enable Breakpoint on Loop Done */
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#define _MVP_DEBUGEN_BKPTLOOP3DONE_SHIFT 4 /**< Shift value for MVP_BKPTLOOP3DONE */
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#define _MVP_DEBUGEN_BKPTLOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_BKPTLOOP3DONE */
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#define _MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP4DONE (0x1UL << 5) /**< Enable Breakpoint on Loop Done */
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#define _MVP_DEBUGEN_BKPTLOOP4DONE_SHIFT 5 /**< Shift value for MVP_BKPTLOOP4DONE */
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#define _MVP_DEBUGEN_BKPTLOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_BKPTLOOP4DONE */
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#define _MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP5DONE (0x1UL << 6) /**< Enable Breakpoint on Loop Done */
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#define _MVP_DEBUGEN_BKPTLOOP5DONE_SHIFT 6 /**< Shift value for MVP_BKPTLOOP5DONE */
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#define _MVP_DEBUGEN_BKPTLOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_BKPTLOOP5DONE */
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#define _MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP6DONE (0x1UL << 7) /**< Enable Breakpoint on Loop Done */
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#define _MVP_DEBUGEN_BKPTLOOP6DONE_SHIFT 7 /**< Shift value for MVP_BKPTLOOP6DONE */
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#define _MVP_DEBUGEN_BKPTLOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_BKPTLOOP6DONE */
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#define _MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP7DONE (0x1UL << 8) /**< Enable Breakpoint on Loop Done */
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#define _MVP_DEBUGEN_BKPTLOOP7DONE_SHIFT 8 /**< Shift value for MVP_BKPTLOOP7DONE */
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#define _MVP_DEBUGEN_BKPTLOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_BKPTLOOP7DONE */
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#define _MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTALUNAN (0x1UL << 10) /**< Enable Breakpoint on ALUNAN */
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#define _MVP_DEBUGEN_BKPTALUNAN_SHIFT 10 /**< Shift value for MVP_BKPTALUNAN */
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#define _MVP_DEBUGEN_BKPTALUNAN_MASK 0x400UL /**< Bit mask for MVP_BKPTALUNAN */
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#define _MVP_DEBUGEN_BKPTALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTALUNAN_DEFAULT (_MVP_DEBUGEN_BKPTALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTR0POSREAL (0x1UL << 11) /**< Enable Breakpoint on R0POSREAL */
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#define _MVP_DEBUGEN_BKPTR0POSREAL_SHIFT 11 /**< Shift value for MVP_BKPTR0POSREAL */
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#define _MVP_DEBUGEN_BKPTR0POSREAL_MASK 0x800UL /**< Bit mask for MVP_BKPTR0POSREAL */
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#define _MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT (_MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTALUOF (0x1UL << 12) /**< Enable Breakpoint on ALUOF */
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#define _MVP_DEBUGEN_BKPTALUOF_SHIFT 12 /**< Shift value for MVP_BKPTALUOF */
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#define _MVP_DEBUGEN_BKPTALUOF_MASK 0x1000UL /**< Bit mask for MVP_BKPTALUOF */
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#define _MVP_DEBUGEN_BKPTALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTALUOF_DEFAULT (_MVP_DEBUGEN_BKPTALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTALUUF (0x1UL << 13) /**< Enable Breakpoint on ALUUF */
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#define _MVP_DEBUGEN_BKPTALUUF_SHIFT 13 /**< Shift value for MVP_BKPTALUUF */
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#define _MVP_DEBUGEN_BKPTALUUF_MASK 0x2000UL /**< Bit mask for MVP_BKPTALUUF */
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#define _MVP_DEBUGEN_BKPTALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTALUUF_DEFAULT (_MVP_DEBUGEN_BKPTALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTSTORECONVERTOF (0x1UL << 14) /**< Enable Breakpoint on STORECONVERTOF */
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#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_SHIFT 14 /**< Shift value for MVP_BKPTSTORECONVERTOF */
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#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_BKPTSTORECONVERTOF */
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#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTSTORECONVERTUF (0x1UL << 15) /**< Enable Breakpoint on STORECONVERTUF */
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#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_SHIFT 15 /**< Shift value for MVP_BKPTSTORECONVERTUF */
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#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_BKPTSTORECONVERTUF */
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#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTSTORECONVERTINF (0x1UL << 16) /**< Enable Breakpoint on STORECONVERTINF */
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#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_SHIFT 16 /**< Shift value for MVP_BKPTSTORECONVERTINF */
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#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_BKPTSTORECONVERTINF */
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#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTSTORECONVERTNAN (0x1UL << 17) /**< Enable Breakpoint on STORECONVERTNAN */
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#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_BKPTSTORECONVERTNAN */
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#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_BKPTSTORECONVERTNAN */
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#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_DEBUGSTEPCNTEN (0x1UL << 28) /**< Debug Step Count Enable */
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#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_SHIFT 28 /**< Shift value for MVP_DEBUGSTEPCNTEN */
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#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_MASK 0x10000000UL /**< Bit mask for MVP_DEBUGSTEPCNTEN */
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#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT (_MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_DEBUGBKPTALLEN (0x1UL << 29) /**< Trigger Breakpoint when ALL conditions match*/
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#define _MVP_DEBUGEN_DEBUGBKPTALLEN_SHIFT 29 /**< Shift value for MVP_DEBUGBKPTALLEN */
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#define _MVP_DEBUGEN_DEBUGBKPTALLEN_MASK 0x20000000UL /**< Bit mask for MVP_DEBUGBKPTALLEN */
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#define _MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT (_MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_DEBUGBKPTANYEN (0x1UL << 30) /**< Enable Breakpoint when ANY conditions match */
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#define _MVP_DEBUGEN_DEBUGBKPTANYEN_SHIFT 30 /**< Shift value for MVP_DEBUGBKPTANYEN */
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#define _MVP_DEBUGEN_DEBUGBKPTANYEN_MASK 0x40000000UL /**< Bit mask for MVP_DEBUGBKPTANYEN */
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#define _MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
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#define MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT (_MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
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/* Bit fields for MVP DEBUGSTEPCNT */
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#define _MVP_DEBUGSTEPCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGSTEPCNT */
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#define _MVP_DEBUGSTEPCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_DEBUGSTEPCNT */
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#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_SHIFT 0 /**< Shift value for MVP_DEBUGSTEPCNT */
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#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_DEBUGSTEPCNT */
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#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGSTEPCNT */
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#define MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT (_MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_DEBUGSTEPCNT */
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/** @} End of group EFR32MG24_MVP_BitFields */
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/** @} End of group EFR32MG24_MVP */
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/** @} End of group Parts */
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#endif /* EFR32MG24_MVP_H */
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