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Libs/platform/bootloader/api/application_properties.h

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+/***************************************************************************//**
+ * @file
+ * @brief Representation of Application Properties
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * The licensor of this software is Silicon Laboratories Inc.  Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement.  This
+ * software is distributed to you in Source Code format and is governed by the
+ * sections of the MSLA applicable to Source Code.
+ *
+ ******************************************************************************/
+#ifndef APPLICATION_PROPERTIES_H
+#define APPLICATION_PROPERTIES_H
+
+#include <stdint.h>
+
+/***************************************************************************//**
+ * @addtogroup Interface
+ * @{
+ * @addtogroup ApplicationProperties Application Properties
+ * @brief Properties of the application that can be accessed by the bootloader
+ * @details
+ *   Applications must contain an @ref ApplicationProperties_t struct declaring
+ *   the application version and capabilities, and so on. The metadata contained
+ *   in this struct will be extracted from the application by the Simplicity
+ *   Commander tool and placed in the GBL upgrade file. If this struct is not
+ *   in the application image, it will be added to the GBL file by the
+ *   Simplicity Commander.
+ *
+ *   The struct is also used to declare whether the application image is signed
+ *   and what type of signature is used. If no @ref ApplicationProperties_t
+ *   struct is present, the bootloader will assume that the application image
+ *   is signed using @ref APPLICATION_SIGNATURE_ECDSA_P256.
+ *
+ *   To ensure that the bootloader can easily locate the ApplicationProperties_t
+ *   struct, if not already done by the linker, Simplicity Commander will modify
+ *   word 13 of the application to insert a pointer to the
+ *   ApplicationProperties_t struct.
+ * @{
+ ******************************************************************************/
+
+/// Magic value declaring the existence of an ApplicationProperties_t struct
+#define APPLICATION_PROPERTIES_MAGIC     { \
+    0x13, 0xb7, 0x79, 0xfa,                \
+    0xc9, 0x25, 0xdd, 0xb7,                \
+    0xad, 0xf3, 0xcf, 0xe0,                \
+    0xf1, 0xb6, 0x14, 0xb8                 \
+}
+
+/// Byte-reversed version of ::APPLICATION_PROPERTIES_MAGIC
+#define APPLICATION_PROPERTIES_REVERSED  { \
+    0xb8, 0x14, 0xb6, 0xf1,                \
+    0xe0, 0xcf, 0xf3, 0xad,                \
+    0xb7, 0xdd, 0x25, 0xc9,                \
+    0xfa, 0x79, 0xb7, 0x13                 \
+}
+
+/// Major version number of the AppliationProperties_t struct
+#define APPLICATION_PROPERTIES_VERSION_MAJOR (1UL)
+/// Minor version number of the AppliationProperties_t struct
+#define APPLICATION_PROPERTIES_VERSION_MINOR (2UL)
+/// Version number of the ApplicationCertificate_t struct
+#define APPLICATION_CERTIFICATE_VERSION  (1UL)
+/// The application is not signed
+#define APPLICATION_SIGNATURE_NONE       (0UL)
+/// @brief The SHA-256 digest of the application is signed using ECDSA with the
+///        NIST P-256 curve.
+#define APPLICATION_SIGNATURE_ECDSA_P256 (1UL << 0UL)
+/// @brief The application is not signed, but has a CRC-32 checksum
+#define APPLICATION_SIGNATURE_CRC32      (1UL << 1UL)
+
+/// The application contains a Zigbee wireless stack
+#define APPLICATION_TYPE_ZIGBEE          (1UL << 0UL)
+/// The application contains a Thread wireless stack
+#define APPLICATION_TYPE_THREAD          (1UL << 1UL)
+/// The application contains a Flex wireless stack
+#define APPLICATION_TYPE_FLEX            (1UL << 2UL)
+/// The application contains a Bluetooth wireless stack
+#define APPLICATION_TYPE_BLUETOOTH       (1UL << 3UL)
+/// The application is an MCU application
+#define APPLICATION_TYPE_MCU             (1UL << 4UL)
+/// The application contains a Bluetooth application
+#define APPLICATION_TYPE_BLUETOOTH_APP   (1UL << 5UL)
+/// The application contains a bootloader
+#define APPLICATION_TYPE_BOOTLOADER      (1UL << 6UL)
+/// The application contains a Zwave wireless stack
+#define APPLICATION_TYPE_ZWAVE           (1UL << 7UL)
+
+/// Application Data
+typedef struct ApplicationData {
+  /// @brief Bitfield representing type of application, e.g.,
+  /// @ref APPLICATION_TYPE_ZIGBEE
+  uint32_t type;
+  /// Version number for this application
+  uint32_t version;
+  /// Capabilities of this application
+  uint32_t capabilities;
+  /// Unique ID (UUID or GUID) for the product this application is built for
+  uint8_t productId[16];
+} ApplicationData_t;
+
+/// Application Certificate
+typedef struct ApplicationCertificate {
+  /// Version of the certificate structure
+  uint8_t structVersion;
+  /// Reserved flags
+  uint8_t flags[3];
+  /// Public key
+  uint8_t key[64];
+  /// The version number of this certificate
+  uint32_t version;
+  /// Signature of the certificate
+  uint8_t signature[64];
+} ApplicationCertificate_t;
+
+/// Application Properties struct
+typedef struct {
+  /// @brief Magic value indicating this is an ApplicationProperties_t struct.
+  /// Must equal @ref APPLICATION_PROPERTIES_MAGIC
+  uint8_t magic[16];
+  /// Version number of this struct
+  uint32_t structVersion;
+  /// Type of signature this application is signed with
+  uint32_t signatureType;
+  /// Location of the signature. Typically points to the end of the application
+  uint32_t signatureLocation;
+  /// Information about the application
+  ApplicationData_t app;
+  /// Pointer to information about the certificate
+  ApplicationCertificate_t *cert;
+  /// Pointer to Long Token Data Section
+  uint8_t *longTokenSectionAddress;
+  /// Parser Decryption Key
+  const uint8_t decryptKey[16];
+} ApplicationProperties_t;
+
+/** @} (end addtogroup ApplicationProperties) */
+/** @} (end addtogroup Interface) */
+
+/// Application Properties major version shift value
+#define APPLICATION_PROPERTIES_VERSION_MAJOR_SHIFT (0U)
+/// Application Properties minor version shift value
+#define APPLICATION_PROPERTIES_VERSION_MINOR_SHIFT (8U)
+
+/// Application Properties major version mask
+#define APPLICATION_PROPERTIES_VERSION_MAJOR_MASK (0x000000FFU)
+/// Application Properties minor version mask
+#define APPLICATION_PROPERTIES_VERSION_MINOR_MASK (0xFFFFFF00U)
+
+/// Version number of the AppliationProperties_t struct
+#define APPLICATION_PROPERTIES_VERSION ((APPLICATION_PROPERTIES_VERSION_MINOR           \
+                                         << APPLICATION_PROPERTIES_VERSION_MINOR_SHIFT) \
+                                        | (APPLICATION_PROPERTIES_VERSION_MAJOR         \
+                                           << APPLICATION_PROPERTIES_VERSION_MAJOR_SHIFT))
+
+#if (APPLICATION_PROPERTIES_VERSION_MAJOR \
+     > (APPLICATION_PROPERTIES_VERSION_MAJOR_MASK >> APPLICATION_PROPERTIES_VERSION_MAJOR_SHIFT))
+|| (APPLICATION_PROPERTIES_VERSION_MINOR \
+    > (APPLICATION_PROPERTIES_VERSION_MINOR_MASK >> APPLICATION_PROPERTIES_VERSION_MINOR_SHIFT))
+#error "Invalid application properties version"
+#endif
+
+#endif // APPLICATION_PROPERTIES_H

Libs/platform/bootloader/api/btl_errorcode.h

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+/***************************************************************************//**
+ * @file
+ * @brief Error codes used and exposed by the bootloader.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * The licensor of this software is Silicon Laboratories Inc.  Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement.  This
+ * software is distributed to you in Source Code format and is governed by the
+ * sections of the MSLA applicable to Source Code.
+ *
+ ******************************************************************************/
+#ifndef BTL_ERRORCODE_H
+#define BTL_ERRORCODE_H
+
+/**
+ * @addtogroup ErrorCodes Error Codes
+ * @brief Bootloader error codes
+ * @details
+ * @{
+ */
+
+/// No error, operation OK
+#define BOOTLOADER_OK                               0L
+
+/**
+ * @addtogroup ErrorBases Error Code Base Values
+ * @brief Bootloader error code base values, per logical function
+ * @details
+ * @{
+ */
+/// Initialization errors
+#define BOOTLOADER_ERROR_INIT_BASE                  0x0100L
+/// Image verification errors
+#define BOOTLOADER_ERROR_PARSE_BASE                 0x0200L
+/// Storage errors
+#define BOOTLOADER_ERROR_STORAGE_BASE               0x0400L
+/// Bootload errors
+#define BOOTLOADER_ERROR_BOOTLOAD_BASE              0x0500L
+/// Security errors
+#define BOOTLOADER_ERROR_SECURITY_BASE              0x0600L
+/// Communication component errors
+#define BOOTLOADER_ERROR_COMMUNICATION_BASE         0x0700L
+/// XMODEM parser errors
+#define BOOTLOADER_ERROR_XMODEM_BASE                0x0900L
+/// Image file parser errors
+#define BOOTLOADER_ERROR_PARSER_BASE                0x1000L
+/// SPI Peripheral driver errors
+#define BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE        0x1100L
+/// UART driver errors
+#define BOOTLOADER_ERROR_UART_BASE                  0x1200L
+/// Compression errors
+#define BOOTLOADER_ERROR_COMPRESSION_BASE           0x1300L
+
+/** @} addtogroup ErrorBases */
+
+/**
+ * @addtogroup InitError Initialization Error Codes
+ * @brief Bootloader error codes returned by initialization code.
+ * @details
+ *    Offset from @ref BOOTLOADER_ERROR_INIT_BASE
+ * @{
+ */
+/// Storage initialization error
+#define BOOTLOADER_ERROR_INIT_STORAGE \
+  (BOOTLOADER_ERROR_INIT_BASE | 0x01L)
+/// Bootloader table invalid
+#define BOOTLOADER_ERROR_INIT_TABLE \
+  (BOOTLOADER_ERROR_INIT_BASE | 0x02L)
+/// Bootloader SFDP not supported
+#define BOOTLOADER_ERROR_INIT_SFDP \
+  (BOOTLOADER_ERROR_INIT_BASE | 0x03L)
+
+/** @} addtogroup InitError */
+
+/**
+ * @addtogroup ParseErrpr Parse Error Codes
+ * @brief Bootloader error codes returned by image parsing.
+ * @details
+ *    Offset from @ref BOOTLOADER_ERROR_PARSE_BASE
+ * @{
+ */
+/// Parse not complete, continue calling the
+/// parsing function
+#define BOOTLOADER_ERROR_PARSE_CONTINUE   (BOOTLOADER_ERROR_PARSE_BASE | 0x01L)
+/// Verification failed
+#define BOOTLOADER_ERROR_PARSE_FAILED     (BOOTLOADER_ERROR_PARSE_BASE | 0x02L)
+/// Verification successfully completed. Image is valid.
+#define BOOTLOADER_ERROR_PARSE_SUCCESS    (BOOTLOADER_ERROR_PARSE_BASE | 0x03L)
+/// Bootloader has no storage, and cannot parse images.
+#define BOOTLOADER_ERROR_PARSE_STORAGE    (BOOTLOADER_ERROR_PARSE_BASE | 0x04L)
+/// Parse context incompatible with parse function
+#define BOOTLOADER_ERROR_PARSE_CONTEXT    (BOOTLOADER_ERROR_PARSE_BASE | 0x05L)
+
+/** @} addtogroup VerificationError */
+
+/**
+ * @addtogroup StorageError Storage Driver Error Codes
+ * @brief Bootloader error codes returned by a storage driver.
+ * @details
+ *    Offset from @ref BOOTLOADER_ERROR_STORAGE_BASE
+ * @{
+ */
+/// Invalid slot
+#define BOOTLOADER_ERROR_STORAGE_INVALID_SLOT \
+  (BOOTLOADER_ERROR_STORAGE_BASE | 0x01L)
+/// Invalid address. Address not aligned/out of range
+#define BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS \
+  (BOOTLOADER_ERROR_STORAGE_BASE | 0x02L)
+/// The storage area needs to be erased before it can be used
+#define BOOTLOADER_ERROR_STORAGE_NEEDS_ERASE \
+  (BOOTLOADER_ERROR_STORAGE_BASE | 0x03L)
+/// The address or length needs to be aligned
+#define BOOTLOADER_ERROR_STORAGE_NEEDS_ALIGN \
+  (BOOTLOADER_ERROR_STORAGE_BASE | 0x04L)
+/// An error occured during bootload from storage
+#define BOOTLOADER_ERROR_STORAGE_BOOTLOAD \
+  (BOOTLOADER_ERROR_STORAGE_BASE | 0x05L)
+/// There is no image in this storage slot
+#define BOOTLOADER_ERROR_STORAGE_NO_IMAGE \
+  (BOOTLOADER_ERROR_STORAGE_BASE | 0x06L)
+/// Continue calling function
+#define BOOTLOADER_ERROR_STORAGE_CONTINUE \
+  (BOOTLOADER_ERROR_STORAGE_BASE | 0x07L)
+/// Generic storage error
+#define BOOTLOADER_ERROR_STORAGE_GENERIC \
+  (BOOTLOADER_ERROR_STORAGE_BASE | 0x08L)
+
+/** @} addtogroup StorageError */
+
+/**
+ * @addtogroup BootloadError Bootloading Error Codes
+ * @brief Bootloader error codes returned by the bootloading process.
+ * @details
+ *    Offset from @ref BOOTLOADER_ERROR_BOOTLOAD_BASE
+ * @{
+ */
+/// No images marked for bootload
+#define BOOTLOADER_ERROR_BOOTLOAD_LIST_EMPTY \
+  (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x01L)
+/// List of images marked for bootload is full
+#define BOOTLOADER_ERROR_BOOTLOAD_LIST_FULL \
+  (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x02L)
+/// Image already marked for bootload
+#define BOOTLOADER_ERROR_BOOTLOAD_LIST_ENTRY_EXISTS \
+  (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x03L)
+/// Bootload list overflowed, requested length too large
+#define BOOTLOADER_ERROR_BOOTLOAD_LIST_OVERFLOW \
+  (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x04L)
+/// No bootload list found at the base of storage
+#define BOOTLOADER_ERROR_BOOTLOAD_LIST_NO_LIST \
+  (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x05L)
+/// Bootload list found but with invalid CRC
+#define BOOTLOADER_ERROR_BOOTLOAD_LIST_INVALID \
+  (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x06L)
+
+/** @} addtogroup BootloadError */
+
+/**
+ * @addtogroup SecurityError Security Error Codes
+ * @brief Bootloader error codes returned by security algorithms.
+ * @details
+ *    Offset from @ref BOOTLOADER_ERROR_SECURITY_BASE
+ * @{
+ */
+/// Invalid input parameter to security algorithm
+#define BOOTLOADER_ERROR_SECURITY_INVALID_PARAM \
+  (BOOTLOADER_ERROR_SECURITY_BASE | 0x01L)
+/// Input parameter to security algorithm is out of range
+#define BOOTLOADER_ERROR_SECURITY_PARAM_OUT_RANGE \
+  (BOOTLOADER_ERROR_SECURITY_BASE | 0x02L)
+/// Invalid option for security algorithm
+#define BOOTLOADER_ERROR_SECURITY_INVALID_OPTION \
+  (BOOTLOADER_ERROR_SECURITY_BASE | 0x03L)
+/// Authentication did not check out
+#define BOOTLOADER_ERROR_SECURITY_REJECTED \
+  (BOOTLOADER_ERROR_SECURITY_BASE | 0x04L)
+
+/** @} addtogroup SecurityError */
+
+/**
+ * @addtogroup CommunicationError Communication Component Error Codes
+ * @brief Bootloader error codes returned by communication components.
+ * @details
+ *    Offset from @ref BOOTLOADER_ERROR_COMMUNICATION_BASE
+ * @{
+ */
+/// Invalid input parameter to security algorithm
+/// Could not initialize hardware resources for communication protocol
+#define BOOTLOADER_ERROR_COMMUNICATION_INIT \
+  (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x01L)
+/// @brief Could not start communication with host (timeout, sync error,
+///        version mismatch, ...)
+#define BOOTLOADER_ERROR_COMMUNICATION_START \
+  (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x02L)
+/// Host closed communication, no image received
+#define BOOTLOADER_ERROR_COMMUNICATION_DONE \
+  (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x03L)
+/// Unrecoverable error in host-bootloader communication
+#define BOOTLOADER_ERROR_COMMUNICATION_ERROR \
+  (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x04L)
+/// Host closed communication, no valid image received
+#define BOOTLOADER_ERROR_COMMUNICATION_IMAGE_ERROR \
+  (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x05L)
+/// Communication aborted, no response from host
+#define BOOTLOADER_ERROR_COMMUNICATION_TIMEOUT \
+  (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x06L)
+
+/** @} addtogroup CommunicationError */
+
+/**
+ * @addtogroup XmodemError XMODEM Error Codes
+ * @brief Bootloader error codes returned by the XMODEM parser.
+ * @details
+ *    Offset from @ref BOOTLOADER_ERROR_XMODEM_BASE
+ * @{
+ */
+/// Could not verify lower CRC byte
+#define BOOTLOADER_ERROR_XMODEM_CRCL \
+  (BOOTLOADER_ERROR_XMODEM_BASE | 0x01L)
+/// Could not verify upper CRC byte
+#define BOOTLOADER_ERROR_XMODEM_CRCH \
+  (BOOTLOADER_ERROR_XMODEM_BASE | 0x02L)
+/// No start of header found
+#define BOOTLOADER_ERROR_XMODEM_NO_SOH \
+  (BOOTLOADER_ERROR_XMODEM_BASE | 0x03L)
+/// Packet number doesn't match its inverse
+#define BOOTLOADER_ERROR_XMODEM_PKTNUM \
+  (BOOTLOADER_ERROR_XMODEM_BASE | 0x04L)
+/// Packet number error (unexpected sequence)
+#define BOOTLOADER_ERROR_XMODEM_PKTSEQ \
+  (BOOTLOADER_ERROR_XMODEM_BASE | 0x05L)
+/// Packet number error (duplicate)
+#define BOOTLOADER_ERROR_XMODEM_PKTDUP \
+  (BOOTLOADER_ERROR_XMODEM_BASE | 0x06L)
+/// Transfer is done (Technically not an error)
+#define BOOTLOADER_ERROR_XMODEM_DONE \
+  (BOOTLOADER_ERROR_XMODEM_BASE | 0x07L)
+/// Transfer is canceled
+#define BOOTLOADER_ERROR_XMODEM_CANCEL \
+  (BOOTLOADER_ERROR_XMODEM_BASE | 0x08L)
+
+/** @} addtogroup XmodemError */
+
+/**
+ * @addtogroup ParserError Image Parser Error Codes
+ * @brief Bootloader error codes returned by the image file parser.
+ * @details
+ *    Offset from @ref BOOTLOADER_ERROR_PARSER_BASE
+ * @{
+ */
+/// Encountered unexpected data/option
+#define BOOTLOADER_ERROR_PARSER_UNEXPECTED \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x01L)
+/// Ran out of internal buffer space.
+/// Please increase internal buffer size to match biggest header
+#define BOOTLOADER_ERROR_PARSER_BUFFER \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x02L)
+/// Internal state: done parsing the current input buffer
+#define BOOTLOADER_ERROR_PARSER_PARSED \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x03L)
+/// Invalid encryption key or no key not present
+#define BOOTLOADER_ERROR_PARSER_KEYERROR \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x04L)
+/// Invalid checksum
+#define BOOTLOADER_ERROR_PARSER_CRC \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x05L)
+/// Invalid signature
+#define BOOTLOADER_ERROR_PARSER_SIGNATURE \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x06L)
+/// Image parsing is already done (or has previously errored out)
+#define BOOTLOADER_ERROR_PARSER_EOF \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x07L)
+/// Unknown data type in image file
+#define BOOTLOADER_ERROR_PARSER_UNKNOWN_TAG \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x08L)
+/// Image file version doesn't match with parser
+#define BOOTLOADER_ERROR_PARSER_VERSION \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x09L)
+/// Image file type doesn't match with parser
+#define BOOTLOADER_ERROR_PARSER_FILETYPE \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x0AL)
+/// Initialization failed
+#define BOOTLOADER_ERROR_PARSER_INIT \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x0BL)
+/// Upgrade file was rejected
+#define BOOTLOADER_ERROR_PARSER_REJECTED \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x0CL)
+/// Upgrade file overlaps with the upgrade location
+#define BOOTLOADER_ERROR_PARSER_OVERLAP \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x0DL)
+/// A GBL tag occurred in an order forbidden by the GBL format spec
+#define BOOTLOADER_ERROR_PARSER_INVALID_TAG_ORDER \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x0EL)
+/// OOB write in the storage slot while parsing the GBL file
+#define BOOTLOADER_ERROR_PARSER_OOB_WRITE \
+  (BOOTLOADER_ERROR_PARSER_BASE | 0x0FL)
+
+/** @} addtogroup ParserError */
+
+/**
+ * @addtogroup SpiPeripheralError SPI Peripheral Driver Error Codes
+ * @brief Bootloader error codes returned by the SPI Peripheral driver.
+ * @details
+ *    Offset from @ref BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE
+ * @{
+ */
+/// Operation not allowed because hardware has not been initialized
+#define BOOTLOADER_ERROR_SPI_PERIPHERAL_UNINIT \
+  (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x01)
+/// Hardware fail during initialization
+#define BOOTLOADER_ERROR_SPI_PERIPHERAL_INIT \
+  (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x02)
+/// Invalid argument
+#define BOOTLOADER_ERROR_SPI_PERIPHERAL_ARGUMENT \
+  (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x03)
+/// Timeout
+#define BOOTLOADER_ERROR_SPI_PERIPHERAL_TIMEOUT \
+  (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x04)
+/// Buffer overflow condition
+#define BOOTLOADER_ERROR_SPI_PERIPHERAL_OVERFLOW \
+  (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x05)
+/// Busy condition
+#define BOOTLOADER_ERROR_SPI_PERIPHERAL_BUSY \
+  (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x06)
+
+/** @} addtogroup SpiPeripheralError */
+
+/**
+ * @addtogroup UartError UART Driver Error Codes
+ * @brief Bootloader error codes returned by the UART driver.
+ * @details
+ *    Offset from @ref BOOTLOADER_ERROR_UART_BASE
+ * @{
+ */
+/// Operation not allowed because hardware has not been initialized
+#define BOOTLOADER_ERROR_UART_UNINIT        (BOOTLOADER_ERROR_UART_BASE | 0x01)
+/// Hardware fail during initialization
+#define BOOTLOADER_ERROR_UART_INIT          (BOOTLOADER_ERROR_UART_BASE | 0x02)
+/// Invalid argument
+#define BOOTLOADER_ERROR_UART_ARGUMENT      (BOOTLOADER_ERROR_UART_BASE | 0x03)
+/// Operation timed out
+#define BOOTLOADER_ERROR_UART_TIMEOUT       (BOOTLOADER_ERROR_UART_BASE | 0x04)
+/// Buffer overflow condition
+#define BOOTLOADER_ERROR_UART_OVERFLOW      (BOOTLOADER_ERROR_UART_BASE | 0x05)
+/// Busy condition
+#define BOOTLOADER_ERROR_UART_BUSY          (BOOTLOADER_ERROR_UART_BASE | 0x06)
+
+/** @} addtogroup UartError */
+
+/**
+ * @addtogroup CompressionError Compression Error Codes
+ * @brief Bootloader error codes returned by the decompressor
+ * @details
+ *    Offset from @ref BOOTLOADER_ERROR_COMPRESSION_BASE
+ * @{
+ */
+/// Could not initialize decompressor
+#define BOOTLOADER_ERROR_COMPRESSION_INIT \
+  (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x01)
+/// Invalid decompressor state -- possible invalid input
+#define BOOTLOADER_ERROR_COMPRESSION_STATE \
+  (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x02)
+/// Data error
+#define BOOTLOADER_ERROR_COMPRESSION_DATA \
+  (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x03)
+/// Data length error
+#define BOOTLOADER_ERROR_COMPRESSION_DATALEN \
+  (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x04)
+/// Memory error
+#define BOOTLOADER_ERROR_COMPRESSION_MEM \
+  (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x05)
+
+/** @} addtogroup CompressionError */
+
+/** @} addtogroup ErrorCodes */
+
+#endif // BTL_ERRORCODE_H

Libs/platform/bootloader/api/btl_interface.c

@@ -0,0 +1,944 @@
+/***************************************************************************//**
+ * @file
+ * @brief Application interface to the bootloader.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * The licensor of this software is Silicon Laboratories Inc.  Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement.  This
+ * software is distributed to you in Source Code format and is governed by the
+ * sections of the MSLA applicable to Source Code.
+ *
+ ******************************************************************************/
+
+#include "btl_interface.h"
+#include "em_core.h"
+#include "btl_interface_cfg.h"
+#if defined(__GNUC__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
+#endif
+
+#if defined(SL_COMPONENT_CATALOG_PRESENT)
+#include "sl_component_catalog.h"
+#endif
+
+#if defined(__GNUC__)
+extern uint32_t __ResetReasonStart__;
+#elif defined(__ICCARM__)
+#pragma section = "BOOTLOADER_RESET_REASON"
+#endif
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+
+// -----------------------------------------------------------------------------
+// Configurations
+
+#if ((!defined(BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING) \
+  || (defined(BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING)  \
+  && (BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING == 0))) && defined(SL_CATALOG_NVM3_PRESENT))
+#define BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING
+#endif // BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING && SL_CATALOG_NVM3_PRESENT
+
+#if !defined(BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE)  \
+  || (defined(BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE) \
+  && (BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE == 0))
+#define BOOTLOADER_ENABLE_USART_AUTO_DETECTION
+#endif // BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE
+
+#if (defined(BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION) \
+  && (BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION == 1))
+#define BOOTLOADER_DISABLE_MULTI_TIERED_FALLBACK
+#undef BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING
+#undef BOOTLOADER_ENABLE_USART_AUTO_DETECTION
+#endif // BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION
+
+#if defined(SL_TRUSTZONE_SECURE)
+#undef BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING
+#endif // SL_TRUSTZONE_SECURE
+
+// -----------------------------------------------------------------------------
+// Configuration spesifics
+
+#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING)
+// Allocated range of NVM3 IDs for bootloader usage */
+#define BL_NVM3_RESERVED_ID  (0x87100UL)
+
+#include <string.h>
+#include "nvm3_default.h"
+
+static bool blPPUSATDnStateCacheSet = false;
+static uint32_t blPPUSATDnStateCache[2] = { 0 };
+#endif // BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING
+
+#if defined(BOOTLOADER_ENABLE_USART_AUTO_DETECTION)
+static void preConfigureUsartPPUSATD(void);
+static void storeUsartInUse(void);
+static int32_t usartNumberSpi = -1;
+#endif // BOOTLOADER_ENABLE_USART_AUTO_DETECTION
+
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+// -----------------------------------------------------------------------------
+// Static variables
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+#if !defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS)
+static CORE_DECLARE_IRQ_STATE;
+#endif
+static Bootloader_PPUSATDnCLKENnState_t blPPUSATDnCLKENnState = { 0 };
+
+typedef enum {
+  IDLE, SAVE, TIERED
+} ppusatdConfigurationState_t;
+
+static ppusatdConfigurationState_t bootloader_ppusatdConfigstate = IDLE;
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+// -----------------------------------------------------------------------------
+// Enums
+
+typedef enum {
+  RESET, INITIALIZED, DEINITIALIZED
+} initState_t;
+
+static initState_t bootloader_InitState = RESET;
+
+// -----------------------------------------------------------------------------
+// Test helpers
+
+#if defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS)
+extern bool enabled;
+extern void enterUnprivilegedMode(bool);
+extern void exitUnprivilegedMode(void);
+#endif // BOOTLOADER_TEST_UNPRIVILEGED_ACCESS
+
+// -----------------------------------------------------------------------------
+// Functions
+
+void bootloader_getInfo(BootloaderInformation_t *info)
+{
+#if defined(BOOTLOADER_HAS_FIRST_STAGE)
+  if (!bootloader_pointerToFirstStageValid(firstBootloaderTable)
+      || !bootloader_pointerValid(mainBootloaderTable)) {
+    // No bootloader is present (first stage or main stage invalid)
+    info->type = NO_BOOTLOADER;
+    info->capabilities = 0;
+  } else if ((firstBootloaderTable->header.type == BOOTLOADER_MAGIC_FIRST_STAGE)
+             && (mainBootloaderTable->header.type == BOOTLOADER_MAGIC_MAIN)) {
+    info->type = SL_BOOTLOADER;
+    info->version = mainBootloaderTable->header.version;
+    info->capabilities = mainBootloaderTable->capabilities;
+  } else {
+    info->type = NO_BOOTLOADER;
+    info->capabilities = 0;
+  }
+#else
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    // No bootloader is present (first stage or main stage invalid)
+    info->type = NO_BOOTLOADER;
+    info->capabilities = 0;
+  } else if (mainBootloaderTable->header.type == BOOTLOADER_MAGIC_MAIN) {
+    info->type = SL_BOOTLOADER;
+    info->version = mainBootloaderTable->header.version;
+    info->capabilities = mainBootloaderTable->capabilities;
+  } else {
+    info->type = NO_BOOTLOADER;
+    info->capabilities = 0;
+  }
+#endif
+}
+
+int32_t bootloader_init(void)
+{
+  int32_t retVal;
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return BOOTLOADER_ERROR_INIT_TABLE;
+  }
+  if (mainBootloaderTable->header.type != BOOTLOADER_MAGIC_MAIN) {
+    return BOOTLOADER_ERROR_INIT_TABLE;
+  }
+
+  if (bootloader_InitState == RESET || bootloader_InitState == DEINITIALIZED) {
+#if defined(SL_TRUSTZONE_SECURE)
+    if (bootloader_InitState == RESET) {
+      // Enable SMU bus clock at the start-up of the TZ secure application
+      // to make it possible to configure the SMU peripheral. Since the CMU address
+      // is known. Otherwise, delegate the SMU bus clock enablement to the NS application.
+#if defined(_CMU_CLKEN1_SMU_MASK)
+      CMU->CLKEN1_SET = CMU_CLKEN1_SMU;
+#endif // _CMU_CLKEN1_SMU_MASK
+    }
+#endif // SL_TRUSTZONE_SECURE
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif
+
+#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING)
+    NVIC_ClearPendingIRQ(SMU_SECURE_IRQn);
+    SMU->IF_CLR = SMU_IEN_PPUSEC;
+    NVIC_EnableIRQ(SMU_SECURE_IRQn);
+    SMU->IEN_SET = SMU_IEN_PPUSEC;
+#endif
+    retVal = mainBootloaderTable->init();
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif
+
+    if (retVal == BOOTLOADER_OK) {
+      bootloader_InitState = INITIALIZED;
+    }
+  } else {
+    retVal = BOOTLOADER_OK;
+  }
+  return retVal;
+}
+
+int32_t bootloader_deinit(void)
+{
+  int32_t retVal;
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return BOOTLOADER_ERROR_INIT_TABLE;
+  }
+  if (mainBootloaderTable->header.type != BOOTLOADER_MAGIC_MAIN) {
+    return BOOTLOADER_ERROR_INIT_TABLE;
+  }
+
+  if (bootloader_InitState == INITIALIZED) {
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING)
+    SMU->IF_CLR = SMU_IEN_PPUSEC;
+    SMU->IEN_CLR = SMU_IEN_PPUSEC;
+    NVIC_ClearPendingIRQ(SMU_SECURE_IRQn);
+    NVIC_DisableIRQ(SMU_SECURE_IRQn);
+#endif
+
+    retVal = mainBootloaderTable->deinit();
+    if (retVal == BOOTLOADER_OK) {
+      bootloader_InitState = DEINITIALIZED;
+    }
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+  } else {
+    retVal = BOOTLOADER_OK;
+  }
+  return retVal;
+}
+
+BootloaderResetCause_t bootloader_getResetReason(void)
+{
+#if defined(__GNUC__)
+  uint32_t resetReasonBase = (uint32_t)&__ResetReasonStart__;
+#elif defined(__ICCARM__)
+  void *resetReasonBase =   __section_begin("BOOTLOADER_RESET_REASON");
+#endif
+
+  volatile BootloaderResetCause_t *resetCause = (BootloaderResetCause_t *)(resetReasonBase);
+  return *resetCause;
+}
+
+void bootloader_rebootAndInstall(void)
+{
+  // Set reset reason to bootloader entry
+#if defined(__GNUC__)
+  uint32_t resetReasonBase = (uint32_t)&__ResetReasonStart__;
+#elif defined(__ICCARM__)
+  void *resetReasonBase =   __section_begin("BOOTLOADER_RESET_REASON");
+#endif
+  BootloaderResetCause_t *resetCause = (BootloaderResetCause_t *) (resetReasonBase);
+  resetCause->reason = BOOTLOADER_RESET_REASON_BOOTLOAD;
+  resetCause->signature = BOOTLOADER_RESET_SIGNATURE_VALID;
+#if defined(RMU_PRESENT)
+  // Clear resetcause
+  RMU->CMD = RMU_CMD_RCCLR;
+  // Trigger a software system reset
+  RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_SYSRMODE_MASK) | RMU_CTRL_SYSRMODE_FULL;
+#endif
+  NVIC_SystemReset();
+}
+
+int32_t bootloader_initParser(BootloaderParserContext_t *context,
+                              size_t                    contextSize)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return BOOTLOADER_ERROR_PARSE_FAILED;
+  }
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  int32_t retVal = mainBootloaderTable->initParser(context, contextSize);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  return retVal;
+}
+
+int32_t bootloader_parseBuffer(BootloaderParserContext_t   *context,
+                               BootloaderParserCallbacks_t *callbacks,
+                               uint8_t                     data[],
+                               size_t                      numBytes)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return BOOTLOADER_ERROR_PARSE_FAILED;
+  }
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  int32_t retVal = mainBootloaderTable->parseBuffer(context, callbacks, data, numBytes);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  return retVal;
+}
+
+int32_t bootloader_parseImageInfo(BootloaderParserContext_t *context,
+                                  uint8_t                   data[],
+                                  size_t                    numBytes,
+                                  ApplicationData_t         *appInfo,
+                                  uint32_t                  *bootloaderVersion)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return BOOTLOADER_ERROR_PARSE_FAILED;
+  }
+
+  BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U };
+  bootloader_getInfo(&info);
+
+  uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK)
+                             >> BOOTLOADER_VERSION_MAJOR_SHIFT);
+  uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK)
+                             >> BOOTLOADER_VERSION_MINOR_SHIFT);
+
+  if ((blMajorVersion < 1UL) || (blMajorVersion == 1UL && blMinorVersion < 11UL)) {
+    return BOOTLOADER_ERROR_PARSE_FAILED;
+  }
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  int32_t retVal = mainBootloaderTable->parseImageInfo(context, data, numBytes, appInfo, bootloaderVersion);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  return retVal;
+}
+
+uint32_t bootloader_parserContextSize(void)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return 0UL;
+  }
+
+  BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U };
+  bootloader_getInfo(&info);
+
+  uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK)
+                             >> BOOTLOADER_VERSION_MAJOR_SHIFT);
+  uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK)
+                             >> BOOTLOADER_VERSION_MINOR_SHIFT);
+
+  if (blMajorVersion < 1UL) {
+    return 384UL;
+  }
+
+  if (blMajorVersion == 1UL && blMinorVersion < 11UL) {
+#if defined(_SILICON_LABS_32B_SERIES_2)
+    if (blMinorVersion == 10UL) {
+      return 524UL;
+    } else {
+      return 384UL;
+    }
+#else
+    return 384UL;
+#endif
+  }
+
+  return (uint32_t)mainBootloaderTable->parserContextSize();
+}
+
+bool bootloader_verifyApplication(uint32_t startAddress)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return false;
+  }
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  bool retVal = mainBootloaderTable->verifyApplication(startAddress);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  return retVal;
+}
+
+bool bootloader_secureBootEnforced(void)
+{
+  BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U };
+  bootloader_getInfo(&info);
+
+  if (info.capabilities & BOOTLOADER_CAPABILITY_ENFORCE_SECURE_BOOT) {
+    return true;
+  }
+  return false;
+}
+
+bool bootloader_getUpgradeLocation(uint32_t *location)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return false;
+  }
+
+  BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U };
+  bootloader_getInfo(&info);
+
+  uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK)
+                             >> BOOTLOADER_VERSION_MAJOR_SHIFT);
+  uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK)
+                             >> BOOTLOADER_VERSION_MINOR_SHIFT);
+
+  if (blMajorVersion > 2UL || (blMajorVersion == 2UL && blMinorVersion >= 1UL)) {
+    *location = mainBootloaderTable->getUpgradeLocation();
+    return true;
+  }
+
+  return false;
+}
+
+#if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
+uint32_t bootloader_remainingApplicationUpgrades(void)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return 0UL;
+  }
+
+  BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U };
+  bootloader_getInfo(&info);
+
+  uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK)
+                             >> BOOTLOADER_VERSION_MAJOR_SHIFT);
+  uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK)
+                             >> BOOTLOADER_VERSION_MINOR_SHIFT);
+
+  if ((blMajorVersion < 1UL) || (blMajorVersion == 1UL && blMinorVersion < 11UL)) {
+    return 0UL;
+  }
+
+  return (uint32_t)mainBootloaderTable->remainingApplicationUpgrades();
+}
+#endif
+
+#if defined(_SILICON_LABS_32B_SERIES_2)
+bool bootloader_getCertificateVersion(uint32_t *version)
+{
+  // Access word 13 to read sl_app_properties of the bootloader.
+  ApplicationProperties_t *blProperties =
+    (ApplicationProperties_t *)(*(uint32_t *)(BTL_MAIN_STAGE_BASE + 52UL));
+
+  if (!bootloader_pointerValid(blProperties)) {
+    return false;
+  }
+
+  // Compatibility check of the application properties struct.
+  if (((blProperties->structVersion & APPLICATION_PROPERTIES_VERSION_MAJOR_MASK)
+       >> APPLICATION_PROPERTIES_VERSION_MAJOR_SHIFT) < 1UL) {
+    return false;
+  }
+  if (((blProperties->structVersion & APPLICATION_PROPERTIES_VERSION_MINOR_MASK)
+       >> APPLICATION_PROPERTIES_VERSION_MINOR_SHIFT) < 1UL) {
+    return false;
+  }
+
+  if (blProperties->cert == NULL) {
+    return false;
+  }
+
+  *version = blProperties->cert->version;
+  return true;
+}
+#endif // _SILICON_LABS_32B_SERIES_2
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+void bootloader_getPeripheralList(uint32_t *ppusatd0, uint32_t *ppusatd1, uint32_t *ppusatd2)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return;
+  }
+
+  BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U };
+  bootloader_getInfo(&info);
+
+  if (info.capabilities & BOOTLOADER_CAPABILITY_PERIPHERAL_LIST) {
+    mainBootloaderTable->getPeripheralList(ppusatd0, ppusatd1, ppusatd2);
+  }
+}
+#else
+void bootloader_getPeripheralList(uint32_t *ppusatd0, uint32_t *ppusatd1)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return;
+  }
+
+  BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U };
+  bootloader_getInfo(&info);
+
+  if (info.capabilities & BOOTLOADER_CAPABILITY_PERIPHERAL_LIST) {
+    mainBootloaderTable->getPeripheralList(ppusatd0, ppusatd1);
+  }
+}
+#endif
+
+void bootloader_ppusatdnSaveReconfigureState(Bootloader_PPUSATDnCLKENnState_t *ctx)
+{
+  if (bootloader_ppusatdConfigstate != IDLE) {
+    // This function is called from a bootloader callback function
+    bootloader_ppusatdConfigstate = TIERED;
+    return;
+  }
+  uint32_t ppusatd0 = 0u;
+  uint32_t ppusatd1 = 0u;
+  #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+  uint32_t ppusatd2 = 0u;
+  #endif
+
+  if (ctx == NULL) {
+    return;
+  }
+
+  bootloader_ppusatdConfigstate = SAVE;
+
+  // Enter ATOMIC section. The ATOMIC section is exited when
+  // the restore function is called.
+#if !defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS)
+  CORE_ENTER_ATOMIC();
+#endif
+
+  sli_bootloader_preHook();
+
+#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING)
+  // Read the stored PPUSATD state from NVM3
+  if (!blPPUSATDnStateCacheSet) {
+    Ecode_t status;
+    status = nvm3_initDefault();
+    if (status == ECODE_NVM3_OK) {
+      nvm3_ObjectKey_t object_id = BL_NVM3_RESERVED_ID;
+      status = nvm3_readData(nvm3_defaultHandle,
+                             object_id,
+                             blPPUSATDnStateCache,
+                             sizeof(blPPUSATDnStateCache));
+      if (status == ECODE_NVM3_OK) {
+        blPPUSATDnStateCacheSet = true;
+      }
+    }
+  }
+#endif // BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING
+
+  // Store the CLKENn states
+#if defined(_CMU_CLKEN0_MASK)
+  ctx->CLKEN0 = CMU->CLKEN0;
+  ctx->CLKEN1 = CMU->CLKEN1;
+#endif
+
+#if defined(_CMU_CLKEN1_SMU_MASK)
+  CMU->CLKEN1_SET = CMU_CLKEN1_SMU;
+#endif // _CMU_CLKEN1_SMU_MASK
+  ctx->SMU_STATUS = SMU->STATUS;
+
+  // Unlock SMU before re-configuration
+  SMU->LOCK = SMU_LOCK_SMULOCKKEY_UNLOCK;
+
+  // Store the PPUSATDn states
+  ctx->PPUSATD0 = SMU->PPUSATD0;
+  ctx->PPUSATD1 = SMU->PPUSATD1;
+  #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+  ctx->PPUSATD2 = SMU->PPUSATD2;
+  #endif
+  ctx->BMPUSATD0 = SMU->BMPUSATD0;
+
+#if defined(SMU_NS_CFGNS_BASE)
+  // Store the PPUPATDn states
+  ctx->PPUPATD0 = SMU->PPUPATD0;
+  ctx->PPUPATD1 = SMU->PPUPATD1;
+  #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+  ctx->PPUPATD2 = SMU->PPUPATD2;
+  #endif
+  SMU->PPUPATD0 = SMU_NS_CFGNS->PPUNSPATD0;
+  SMU->PPUPATD1 = SMU_NS_CFGNS->PPUNSPATD1;
+  #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+  SMU->PPUPATD2 = SMU_NS_CFGNS->PPUNSPATD2;
+  #endif
+#endif // SMU_NS_CFGNS_BASE
+
+#if defined(CMU_CLKEN0_LDMA)
+  CMU->CLKEN0_SET = CMU_CLKEN0_LDMA;
+#endif // CMU_CLKEN0_LDMA
+#if defined(CRYPTOACC_PRESENT)
+  CMU->CLKEN1_SET = CMU_CLKEN1_CRYPTOACC;
+#endif
+
+  // Wait for any active transition of other busmasters to finish
+  if (SMU->PPUSATD0 & SMU_PPUSATD0_LDMA) {
+    while (LDMA_S->STATUS & LDMA_STATUS_ANYBUSY) ;
+  } else {
+    while (LDMA_NS->STATUS & LDMA_STATUS_ANYBUSY) ;
+  }
+#if defined(CRYPTOACC_PRESENT)
+  if (SMU->PPUSATD1 & SMU_PPUSATD1_CRYPTOACC) {
+    #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_230)
+    while (CRYPTOACC_S->DMACTRL_STATUS & (CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY | CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY | CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY)) ;
+    #else
+    while (CRYPTOACC_S->STATUS & (CRYPTOACC_STATUS_FETCHERBSY | CRYPTOACC_STATUS_PUSHERBSY | CRYPTOACC_STATUS_SOFTRSTBSY)) ;
+    #endif
+  } else {
+    #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_230)
+    while (CRYPTOACC_NS->DMACTRL_STATUS & (CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY | CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY | CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY)) ;
+    #else
+    while (CRYPTOACC_NS->STATUS & (CRYPTOACC_STATUS_FETCHERBSY | CRYPTOACC_STATUS_PUSHERBSY | CRYPTOACC_STATUS_SOFTRSTBSY)) ;
+    #endif
+  }
+#endif // CRYPTOACC_PRESENT
+
+  // Configure the peripheral secure access state before calling into the bootloader.
+#if !defined(BOOTLOADER_DISABLE_MULTI_TIERED_FALLBACK)
+#if defined(BOOTLOADER_ENABLE_USART_AUTO_DETECTION)
+  // If we do not know which USART is used by the bootloader,
+  // and the bootloader is not initialized,
+  // Configure PPUSATDn bits for all the USART not in use.
+  preConfigureUsartPPUSATD();
+#else
+  SMU->PPUSATD0_SET = BOOTLOADER_PPUSATD0_MASK;
+  SMU->PPUSATD1_SET = BOOTLOADER_PPUSATD1_MASK;
+#endif // BOOTLOADER_ENABLE_USART_AUTO_DETECTION
+
+  SMU->PPUSATD0_SET = SMU_PPUSATD0_CMU;
+  SMU->PPUSATD0_SET = SMU_PPUSATD0_MSC;
+  if (bootloader_getAllocatedDMAChannel() != -1
+      && bootloader_getAllocatedDMAChannel() != BOOTLOADER_ERROR_INIT_STORAGE) {
+    SMU->PPUSATD0_SET = SMU_PPUSATD0_LDMA;
+    SMU->PPUSATD0_SET = SMU_PPUSATD0_LDMAXBAR;
+    SMU->BMPUSATD0_SET = SMU_BMPUSATD0_LDMA;
+  }
+
+  SMU->PPUSATD0_SET = SMU_PPUSATD0_HFRCO0;
+#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) && !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \
+  && !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) && !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)
+  SMU->PPUSATD0_SET = SMU_PPUSATD0_GPIO;
+#endif
+#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+  SMU->PPUSATD1_SET = SMU_PPUSATD1_GPCRC;
+#else
+  SMU->PPUSATD0_SET = SMU_PPUSATD0_GPCRC;
+#endif
+#if defined(SMU_PPUSATD1_CRYPTOACC)
+  SMU->PPUSATD1_SET = SMU_PPUSATD1_CRYPTOACC;
+#endif // SMU_PPUSATD1_CRYPTOACC
+#if defined(SMU_PPUSATD1_SEMAILBOX)
+  SMU->PPUSATD1_SET = SMU_PPUSATD1_SEMAILBOX;
+#elif defined(SMU_PPUSATD2_SEMAILBOX)
+  SMU->PPUSATD2_SET = SMU_PPUSATD2_SEMAILBOX;
+#endif // SMU_PPUSATD1_SEMAILBOX
+#elif defined(SL_TRUSTZONE_SECURE)
+  #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
+  SMU->BMPUSATD0_SET = SMU_BMPUSATD0_LDMA0;
+  SMU->BMPUSATD0_SET = SMU_BMPUSATD0_LDMA1;
+  #else
+  SMU->BMPUSATD0_SET = SMU_BMPUSATD0_LDMA;
+  #endif
+#endif // BOOTLOADER_DISABLE_MULTI_TIERED_FALLBACK
+
+#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+  bootloader_getPeripheralList(&ppusatd0, &ppusatd1, &ppusatd2);
+  SMU->PPUSATD0_SET = ppusatd0;
+  SMU->PPUSATD1_SET = ppusatd1;
+  SMU->PPUSATD2_SET = ppusatd2;
+#else
+  bootloader_getPeripheralList(&ppusatd0, &ppusatd1);
+  SMU->PPUSATD0_SET = ppusatd0;
+  SMU->PPUSATD1_SET = ppusatd1;
+#endif
+
+#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING)
+  // Update the peripheral secure access state of
+  // the "unknown" peripheral that triggered a fault earlier
+  if (blPPUSATDnStateCacheSet == true) {
+    SMU->PPUSATD0_SET = blPPUSATDnStateCache[0];
+    SMU->PPUSATD1_SET = blPPUSATDnStateCache[1];
+  }
+#endif // BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING
+#if defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS)
+  enterUnprivilegedMode(enabled);
+#endif
+}
+
+void bootloader_ppusatdnRestoreState(Bootloader_PPUSATDnCLKENnState_t *ctx)
+{
+#if defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS)
+  exitUnprivilegedMode();
+#endif
+
+  if (bootloader_ppusatdConfigstate != SAVE) {
+    // This function is called from a bootloader callback function
+    bootloader_ppusatdConfigstate = SAVE;
+    return;
+  }
+
+  if (ctx == NULL) {
+    return;
+  }
+
+  // Wait for any active transition of other busmasters to finish
+  if (bootloader_getAllocatedDMAChannel() != -1
+      && bootloader_getAllocatedDMAChannel() != BOOTLOADER_ERROR_INIT_STORAGE) {
+#if defined(CMU_CLKEN0_LDMA)
+    CMU_S->CLKEN0_SET = CMU_CLKEN0_LDMA;
+#endif // CMU_CLKEN0_LDMA
+    while (LDMA_S->STATUS & LDMA_STATUS_ANYBUSY) ;
+  }
+#if defined(CRYPTOACC_PRESENT)
+  if (SMU->PPUSATD0 & SMU_PPUSATD0_CMU) {
+    CMU_S->CLKEN1_SET = CMU_CLKEN1_CRYPTOACC;
+  } else {
+    CMU_NS->CLKEN1_SET = CMU_CLKEN1_CRYPTOACC;
+  }
+  #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_230)
+  while (CRYPTOACC_S->DMACTRL_STATUS & (CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY | CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY | CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY)) ;
+    #else
+  while (CRYPTOACC_S->STATUS & (CRYPTOACC_STATUS_FETCHERBSY | CRYPTOACC_STATUS_PUSHERBSY | CRYPTOACC_STATUS_SOFTRSTBSY)) ;
+    #endif
+#endif // CRYPTOACC_PRESENT
+
+  SMU->PPUSATD0 = ctx->PPUSATD0;
+  SMU->PPUSATD1 = ctx->PPUSATD1;
+  #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+  SMU->PPUSATD2 = ctx->PPUSATD2;
+  #endif
+  SMU->BMPUSATD0 = ctx->BMPUSATD0;
+#if defined(SMU_NS_CFGNS_BASE)
+  SMU->PPUPATD0 = ctx->PPUPATD0;
+  SMU->PPUPATD1 = ctx->PPUPATD1;
+  #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+  SMU->PPUPATD2 = ctx->PPUPATD2;
+  #endif
+#endif // SMU_NS_CFGNS_BASE
+  if (ctx->SMU_STATUS & SMU_STATUS_SMULOCK) {
+    SMU->LOCK = 0u;
+  }
+
+#if defined(BOOTLOADER_ENABLE_USART_AUTO_DETECTION)
+  storeUsartInUse();
+#endif // BOOTLOADER_ENABLE_USART_AUTO_DETECTION
+
+  // Restore the CLKENn states
+#if defined(_CMU_CLKEN0_MASK)
+  CMU->CLKEN0 = ctx->CLKEN0;
+  CMU->CLKEN1 = ctx->CLKEN1;
+#endif
+
+  sli_bootloader_postHook();
+
+#if !defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS)
+  CORE_EXIT_ATOMIC();
+#endif
+
+  // Update the state after the critical section has been
+  // exited to ensure that the SMU interrupt gets fired,
+  // before the state change happens.
+  bootloader_ppusatdConfigstate = IDLE;
+}
+
+__attribute__ ((weak)) void sli_bootloader_preHook(void)
+{
+}
+
+__attribute__ ((weak)) void sli_bootloader_postHook(void)
+{
+}
+
+#if defined(BOOTLOADER_ENABLE_USART_AUTO_DETECTION)
+static void preConfigureUsartPPUSATD(void)
+{
+  if (usartNumberSpi != -1) {
+    #if defined(SMU_PPUSATD1_USART0)
+    SMU->PPUSATD1_SET = (SMU_PPUSATD1_USART0 << usartNumberSpi);
+    #else
+    SMU->PPUSATD0_SET = (SMU_PPUSATD0_USART0 << usartNumberSpi);
+    #endif
+    return;
+  }
+
+  if (bootloader_InitState != RESET) {
+    // The USART taken by the bootloader
+    // is still unknown, do nothing.
+    return;
+  }
+#if defined(USART0_BASE)
+#if defined(CMU_CLKEN0_USART0)
+  CMU->CLKEN0_SET = CMU_CLKEN0_USART0;
+#endif // CMU_CLKEN0_USART0
+#if defined(SL_TRUSTZONE_SECURE)
+  if (USART0_NS->EN == _USART_EN_RESETVALUE) {
+#else
+  if (USART0->EN == _USART_EN_RESETVALUE) {
+#endif // SL_TRUSTZONE_SECURE
+    #if defined(SMU_PPUSATD1_USART0)
+    SMU->PPUSATD1_SET = SMU_PPUSATD1_USART0;
+    #else
+    SMU->PPUSATD0_SET = SMU_PPUSATD0_USART0;
+    #endif
+  }
+#endif // USART0_BASE
+
+#if defined(USART1_BASE)
+#if defined(CMU_CLKEN0_USART1)
+  CMU->CLKEN0_SET = CMU_CLKEN0_USART1;
+#elif defined(CMU_CLKEN2_USART1)
+  CMU->CLKEN2_SET = CMU_CLKEN2_USART1;
+#endif
+#if defined(SL_TRUSTZONE_SECURE)
+  if (USART1_NS->EN == _USART_EN_RESETVALUE) {
+#else
+  if (USART1->EN == _USART_EN_RESETVALUE) {
+#endif // SL_TRUSTZONE_SECURE
+    #if defined(SMU_PPUSATD1_USART1)
+    SMU->PPUSATD1_SET = SMU_PPUSATD1_USART1;
+    #else
+    SMU->PPUSATD0_SET = SMU_PPUSATD0_USART1;
+    #endif
+  }
+#endif // USART1_BASE
+
+#if defined(USART2_BASE)
+#if defined(CMU_CLKEN0_USART2)
+  CMU->CLKEN0_SET = CMU_CLKEN0_USART2;
+#elif defined(CMU_CLKEN2_USART2)
+  CMU->CLKEN2_SET = CMU_CLKEN2_USART2;
+#endif
+#if defined(SL_TRUSTZONE_SECURE)
+  if (USART2_NS->EN == _USART_EN_RESETVALUE) {
+#else
+  if (USART2->EN == _USART_EN_RESETVALUE) {
+#endif // SL_TRUSTZONE_SECURE
+    #if defined(SMU_PPUSATD1_USART2)
+    SMU->PPUSATD1_SET = SMU_PPUSATD1_USART2;
+    #else
+    SMU->PPUSATD0_SET = SMU_PPUSATD0_USART2;
+    #endif
+  }
+#endif // USART2_BASE
+}
+
+static void storeUsartInUse(void)
+{
+  if ((usartNumberSpi != -1) || (bootloader_InitState != RESET)) {
+    return;
+  }
+#if defined(USART0_BASE)
+#if defined(SL_TRUSTZONE_SECURE)
+  if (USART0_NS->EN & USART_EN_EN) {
+#else
+  if (USART0->EN & USART_EN_EN) {
+#endif // SL_TRUSTZONE_SECURE
+    usartNumberSpi = 0;
+  }
+#endif // USART0_BASE
+
+#if defined(USART1_BASE)
+#if defined(SL_TRUSTZONE_SECURE)
+  if (USART1_NS->EN & USART_EN_EN) {
+#else
+  if (USART1->EN & USART_EN_EN) {
+#endif // SL_TRUSTZONE_SECURE
+    usartNumberSpi = 1;
+  }
+#endif // USART1_BASE
+
+#if defined(USART2_BASE)
+#if defined(SL_TRUSTZONE_SECURE)
+  if (USART2_NS->EN & USART_EN_EN) {
+#else
+  if (USART2->EN & USART_EN_EN) {
+#endif // SL_TRUSTZONE_SECURE
+    usartNumberSpi = 2;
+  }
+#endif // USART2_BASE
+}
+#endif // BOOTLOADER_ENABLE_USART_AUTO_DETECTION
+
+#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING)
+void SMU_SECURE_IRQHandler(void)
+{
+#if !defined(BOOTLOADER_TEST_FAULT_HANDLING)
+  if (bootloader_ppusatdConfigstate == IDLE) {
+    // If none of the bootloader interface operations are active,
+    // the fault is not caused by the bootloader. Just park in the while loop.
+    while (true) ;
+  }
+#endif // BOOTLOADER_TEST_FAULT_HANDLING
+
+  Ecode_t status;
+  uint32_t PPUSATDn_state[2] = { 0 };
+  nvm3_ObjectKey_t object_id = BL_NVM3_RESERVED_ID;
+
+  // First read the pre-existing configuration
+  status = nvm3_readData(nvm3_defaultHandle, object_id, PPUSATDn_state, sizeof(PPUSATDn_state));
+  if (status == ECODE_NVM3_OK) {
+    if (SMU->PPUFS > 31) {
+      PPUSATDn_state[1] |= 1 << (SMU->PPUFS - 32);
+    } else {
+      PPUSATDn_state[0] |= 1 << SMU->PPUFS;
+    }
+    // Nothing to do to recover if this fails, just continue and perform a reset.
+    (void)nvm3_writeData(nvm3_defaultHandle, object_id, PPUSATDn_state, sizeof(PPUSATDn_state));
+  } else if (status == ECODE_NVM3_ERR_KEY_NOT_FOUND) {
+    if (SMU->PPUFS > 31) {
+      PPUSATDn_state[1] = 1 << (SMU->PPUFS - 32);
+    } else {
+      PPUSATDn_state[0] = 1 << SMU->PPUFS;
+    }
+    (void)nvm3_writeData(nvm3_defaultHandle, object_id, PPUSATDn_state, sizeof(PPUSATDn_state));
+  } else {
+    // Do nothing. If NVM3 read fails for an unknown reason,
+    // perform a reset to recover from the failure state.
+  }
+
+#if defined(__GNUC__)
+  uint32_t resetReasonBase = (uint32_t)&__ResetReasonStart__;
+#elif defined(__ICCARM__)
+  void *resetReasonBase =   __section_begin("BOOTLOADER_RESET_REASON");
+#endif
+  BootloaderResetCause_t *resetCause = (BootloaderResetCause_t *) (resetReasonBase);
+  resetCause->reason = BOOTLOADER_RESET_REASON_FAULT;
+  resetCause->signature = BOOTLOADER_RESET_SIGNATURE_VALID;
+  NVIC_SystemReset();
+}
+#endif // BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING
+
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+#if defined(__GNUC__)
+#pragma GCC diagnostic pop
+#endif

Libs/platform/bootloader/api/btl_interface.h

@@ -0,0 +1,773 @@
+/***************************************************************************//**
+ * @file
+ * @brief Application interface to the bootloader.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * The licensor of this software is Silicon Laboratories Inc.  Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement.  This
+ * software is distributed to you in Source Code format and is governed by the
+ * sections of the MSLA applicable to Source Code.
+ *
+ ******************************************************************************/
+#ifndef BTL_INTERFACE_H
+#define BTL_INTERFACE_H
+
+#include <stddef.h>
+
+#include "btl_errorcode.h"
+#include "btl_reset_info.h"
+#include "application_properties.h"
+
+// Include component-specific interfaces
+#include "btl_interface_parser.h"
+#include "btl_interface_storage.h"
+
+// Get flash page size
+#include "em_device.h"
+
+#if defined(SL_TRUSTZONE_NONSECURE)
+#include "sli_tz_ns_interface.h"
+#endif
+
+#if defined(__GNUC__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
+#endif
+/***************************************************************************//**
+ * @addtogroup Interface Application Interface
+ * @brief Application interface to the bootloader
+ * @details
+ *   The application interface consists of functions that can be included
+ *   in the customer application that and will communicate with the
+ *   bootloader through the @ref MainBootloaderTable_t. This table
+ *   contains function pointers to the bootloader. The 10th word of the
+ *   bootloader contains a pointer to this struct, allowing any application to
+ *   easily locate it.
+ *   To access the bootloader table, use wrapper functions. Avoid
+ *   accessing the bootloader table directly.
+ *
+ * @{
+ * @addtogroup CommonInterface Common Application Interface
+ * @brief Generic application interface available on all versions of the
+ *        bootloader, regardless of the available components.
+ * @note These Bootloader APIs are not reentrant and should be wrapped in critical section
+ *       where needed.
+ * @details
+ * @{
+ ******************************************************************************/
+
+/// Bare boot table. Can be mapped on top of vector table to access contents.
+typedef struct {
+  /// Pointer to top of stack
+  uint32_t *stackTop;
+  /// Pointer to reset vector
+  void     (*resetVector)(void);
+  /// Reserved pointers to fault handlers
+  uint32_t reserved0[5];
+  /// Reserved pointers to RESERVED fields
+  uint32_t reserved1[3];
+  /// Pointer to bootloader table
+  void     *table;
+  /// Reserved pointers to SVC and DebugMon interrupts
+  uint32_t reserved2[2];
+  /// Pointer to application signature
+  void     *signature;
+} BareBootTable_t;
+
+// --------------------------------
+// Bootloader defines
+
+/// Bootloader version major version shift value
+#define BOOTLOADER_VERSION_MAJOR_SHIFT (24U)
+/// Bootloader version minor version shift value
+#define BOOTLOADER_VERSION_MINOR_SHIFT (16U)
+/// Bootloader version major version mask
+#define BOOTLOADER_VERSION_MAJOR_MASK (0xFF000000U)
+/// Bootloader version minor version mask
+#define BOOTLOADER_VERSION_MINOR_MASK (0x00FF0000U)
+
+/// Bootloader interface APIs are trust zone aware
+#if defined(BOOTLOADER_SECURE)
+#define BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+#elif defined(_SILICON_LABS_32B_SERIES_2) && !defined(BOOTLOADER_APPLOADER)
+// The bootloader with AppLoader as the communication interface will not
+// re-configure the SMU since it is using the NS peripherals by default.
+#define BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+#endif
+
+// --------------------------------
+// Bootloader information typedefs
+
+/// Type of bootloader
+typedef enum {
+  /// No bootloader present.
+  NO_BOOTLOADER = 0,
+  /// Bootloader is a Silicon Labs bootloader.
+  SL_BOOTLOADER = 1
+} BootloaderType_t;
+
+/// Information about the current bootloader
+typedef struct {
+  /// The type of bootloader.
+  BootloaderType_t type;
+  /// Version number of the bootloader
+  uint32_t version;
+  /// Capability mask for the bootloader.
+  uint32_t capabilities;
+} BootloaderInformation_t;
+
+/// Common header for bootloader tables
+typedef struct {
+  /// Type of image
+  uint32_t type;
+  /// Version number of the bootloader/application table
+  uint32_t layout;
+  /// Version number of the image
+  uint32_t version;
+} BootloaderHeader_t;
+
+/// Address table for the First Stage Bootloader
+typedef struct {
+  /// Header of the First Stage Bootloader table
+  BootloaderHeader_t header;
+  /// Start address of the Main Bootloader
+  BareBootTable_t *mainBootloader;
+  /// Location of the Main Bootloader upgrade image
+  BareBootTable_t *upgradeLocation;
+} FirstBootloaderTable_t;
+
+/// Address table for the Main Bootloader
+typedef struct {
+  /// Header of the Main Bootloader table
+  BootloaderHeader_t header;
+  /// Size of the Main Bootloader
+  uint32_t size;
+  /// Start address of the application
+  BareBootTable_t *startOfAppSpace;
+  /// End address of the allocated application space
+  uint32_t *endOfAppSpace;
+  /// Capabilities of the bootloader
+  uint32_t capabilities;
+  // ------------------------------
+  /// Initialize bootloader for use from application
+  int32_t (*init)(void);
+  /// Deinitialize bootloader after use from application
+  int32_t (*deinit)(void);
+  // ------------------------------
+  /// Verify application
+  bool (*verifyApplication)(uint32_t startAddress);
+  // ------------------------------
+  /// Initialize parser
+  int32_t (*initParser)(BootloaderParserContext_t *context, size_t contextSize);
+  /// Parse a buffer
+  int32_t (*parseBuffer)(BootloaderParserContext_t         *context,
+                         const BootloaderParserCallbacks_t *callbacks,
+                         uint8_t                           data[],
+                         size_t                            numBytes);
+  // ------------------------------
+  /// Function table for storage component
+  const BootloaderStorageFunctions_t *storage;
+  // ------------------------------
+  /// Parse a buffer and get application and bootloader upgrade metadata from the buffer.
+  int32_t (*parseImageInfo)(BootloaderParserContext_t *context,
+                            uint8_t                    data[],
+                            size_t                     numBytes,
+                            ApplicationData_t          *appInfo,
+                            uint32_t                   *bootloaderVersion);
+  // ------------------------------
+  /// Size of context buffer used by bootloader image parser to store parser state
+  uint32_t (*parserContextSize)(void);
+  // ------------------------------
+  /// Remaining number of application upgrades
+  uint32_t (*remainingApplicationUpgrades)(void);
+  // ------------------------------
+  /// Get the list of the peripheral that is used by the bootloader
+  #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+  void (*getPeripheralList)(uint32_t *ppusatd0, uint32_t *ppusatd1, uint32_t *ppusatd2);
+  #else
+  void (*getPeripheralList)(uint32_t *ppusatd0, uint32_t *ppusatd1);
+  #endif
+  // ------------------------------
+  /// Get base address of bootloader upgrade image
+  uint32_t (*getUpgradeLocation)(void);
+} MainBootloaderTable_t;
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+/// Struct that represents the state of the PPUSATDn, PPUPATDn and CLKENn registers
+typedef struct {
+  uint32_t PPUSATD0;
+  uint32_t PPUSATD1;
+  #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+  uint32_t PPUSATD2;
+  #endif
+  uint32_t BMPUSATD0;
+#if defined(SMU_NS_CFGNS_BASE)
+  uint32_t PPUPATD0;
+  uint32_t PPUPATD1;
+  #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+  uint32_t PPUPATD2;
+  #endif
+#endif
+#if defined(_CMU_CLKEN0_MASK)
+  uint32_t CLKEN0;
+  uint32_t CLKEN1;
+#endif
+  uint32_t SMU_STATUS;
+} Bootloader_PPUSATDnCLKENnState_t;
+
+/// Struct containing function arguments
+typedef struct Bootloader_inOutVec {
+  void *base;   /// the start address of the memory buffer
+  size_t len;   /// the size in bytes
+} Bootloader_inOutVec_t;
+
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+// --------------------------------
+// Bootloader capabilities
+
+/// Bootloader enforces signed application upgrade images
+#define BOOTLOADER_CAPABILITY_ENFORCE_UPGRADE_SIGNATURE        (1 << 0)
+/// Bootloader enforces encrypted application upgrade images
+#define BOOTLOADER_CAPABILITY_ENFORCE_UPGRADE_ENCRYPTION       (1 << 1)
+/// @brief Bootloader enforces signature verification of the application image
+///        before every boot
+#define BOOTLOADER_CAPABILITY_ENFORCE_SECURE_BOOT              (1 << 2)
+
+/// Bootloader has the capability of being upgraded
+#define BOOTLOADER_CAPABILITY_BOOTLOADER_UPGRADE               (1 << 4)
+
+/// Bootloader has the capability of parsing GBL files
+#define BOOTLOADER_CAPABILITY_GBL                              (1 << 5)
+/// Bootloader has the capability of parsing signed GBL files
+#define BOOTLOADER_CAPABILITY_GBL_SIGNATURE                    (1 << 6)
+/// Bootloader has the capability of parsing encrypted GBL files
+#define BOOTLOADER_CAPABILITY_GBL_ENCRYPTION                   (1 << 7)
+/// @brief Bootloader enforces signature verification of the application image
+///        before every boot using certificate
+#define BOOTLOADER_CAPABILITY_ENFORCE_CERTIFICATE_SECURE_BOOT  (1 << 8)
+/// Bootloader has the capability of application rollback protection
+#define BOOTLOADER_CAPABILITY_ROLLBACK_PROTECTION              (1 << 9)
+/// Bootloader has the capability to check the peripherals in use
+#define BOOTLOADER_CAPABILITY_PERIPHERAL_LIST                  (1 << 10)
+
+/// @brief Bootloader has the capability of storing data in an internal or
+/// external storage medium
+#define BOOTLOADER_CAPABILITY_STORAGE                     (1 << 16)
+/// @brief Bootloader has the capability of communicating with host processors
+/// using a communication interface
+#define BOOTLOADER_CAPABILITY_COMMUNICATION               (1 << 20)
+
+// --------------------------------
+// Magic constants for bootloader tables
+
+/// Magic word indicating first stage bootloader table
+#define BOOTLOADER_MAGIC_FIRST_STAGE                      (0xB00710ADUL)
+/// Magic word indicating main bootloader table
+#define BOOTLOADER_MAGIC_MAIN                             (0x5ECDB007UL)
+
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+#define BOOTLOADER_HEADER_VERSION_FIRST_STAGE             (0x00000001UL)
+#define BOOTLOADER_HEADER_VERSION_MAIN                    (0x00000002UL)
+/// @endcond
+
+// --------------------------------
+// Bootloader table access
+
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+
+#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) || defined(MAIN_BOOTLOADER_TEST)
+// No first stage on devices with SE
+#define BTL_FIRST_STAGE_SIZE              (0UL)
+#else
+// First stage takes a single flash page
+#define BTL_FIRST_STAGE_SIZE              (FLASH_PAGE_SIZE)
+#define BOOTLOADER_HAS_FIRST_STAGE
+#endif
+
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
+// No writeable bootloader area: Place the bootloader in main flash
+#define BTL_FIRST_STAGE_BASE              0x00000000UL
+#define BTL_APPLICATION_BASE              0x00004000UL
+#define BTL_MAIN_STAGE_MAX_SIZE           (BTL_APPLICATION_BASE \
+                                           - BTL_FIRST_STAGE_SIZE)
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
+// Dedicated bootloader area of 38k
+// Place the bootloader in the dedicated bootloader area of the
+// information block
+#define BTL_FIRST_STAGE_BASE              0x0FE10000UL
+#define BTL_APPLICATION_BASE              0x00000000UL
+#define BTL_MAIN_STAGE_MAX_SIZE           (0x00009800UL - BTL_FIRST_STAGE_SIZE)
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
+#define BTL_FIRST_STAGE_BASE              0x0FE10000UL
+#if defined(MAIN_BOOTLOADER_IN_MAIN_FLASH)
+#define BTL_APPLICATION_BASE              0x00004800UL
+#define BTL_MAIN_STAGE_MAX_SIZE           BTL_APPLICATION_BASE
+#else
+// Dedicated bootloader area of 16k
+// Place the bootloader in the dedicated bootloader area of the
+// information block
+#define BTL_APPLICATION_BASE              0x00000000UL
+#define BTL_MAIN_STAGE_MAX_SIZE           (0x00004000UL - BTL_FIRST_STAGE_SIZE)
+#endif
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
+#define BTL_FIRST_STAGE_BASE              0x0FE10000UL
+#if defined(MAIN_BOOTLOADER_IN_MAIN_FLASH)
+#define BTL_APPLICATION_BASE              0x00004800UL
+#define BTL_MAIN_STAGE_MAX_SIZE           BTL_APPLICATION_BASE
+#else
+// Dedicated bootloader area of 18k
+// Place the bootloader in the dedicated bootloader area of the
+// information block
+#define BTL_APPLICATION_BASE              0x00000000UL
+#define BTL_MAIN_STAGE_MAX_SIZE           (0x00004800UL - BTL_FIRST_STAGE_SIZE)
+#endif
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106)
+// Dedicated bootloader area of 32k
+// Place the bootloader in the dedicated bootloader area of the
+// information block
+#define BTL_FIRST_STAGE_BASE              0x0FE10000UL
+#define BTL_APPLICATION_BASE              0x00000000UL
+#define BTL_MAIN_STAGE_MAX_SIZE           (0x00008000UL - BTL_FIRST_STAGE_SIZE)
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
+// Dedicated bootloader area of 18k
+// Place the bootloader in the dedicated bootloader area of the
+// information block
+#define BTL_FIRST_STAGE_BASE              0x0FE10000UL
+#define BTL_APPLICATION_BASE              0x00000000UL
+#define BTL_MAIN_STAGE_MAX_SIZE           (0x00004800UL - BTL_FIRST_STAGE_SIZE)
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200)
+// No bootloader area: Place the bootloader in main flash
+#define BTL_FIRST_STAGE_BASE              FLASH_BASE
+#if defined(BOOTLOADER_APPLOADER)
+#if defined(BOOTLOADER_SECURE)
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00014000UL)
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00012000UL)
+#endif // BOOTLOADER_SECURE
+#elif defined(BOOTLOADER_SECURE) && defined(BOOTLOADER_SUPPORT_COMMUNICATION)
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00006000UL)
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00004000UL)
+#endif // BOOTLOADER_APPLOADER
+#define BTL_MAIN_STAGE_MAX_SIZE           (BTL_APPLICATION_BASE \
+                                           - BTL_FIRST_STAGE_SIZE)
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205)
+// No bootloader area: Place the bootloader in main flash
+#define BTL_FIRST_STAGE_BASE              FLASH_BASE
+#if defined(BOOTLOADER_APPLOADER)
+#if defined(BOOTLOADER_SECURE)
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00014000UL)
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00012000UL)
+#endif // BOOTLOADER_SECURE
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00006000UL)
+#endif // BOOTLOADER_APPLOADER
+#define BTL_MAIN_STAGE_MAX_SIZE           (BTL_APPLICATION_BASE \
+                                           - BTL_FIRST_STAGE_SIZE)
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_210)
+// No bootloader area: Place the bootloader in main flash
+#define BTL_FIRST_STAGE_BASE              FLASH_BASE
+#if defined(BOOTLOADER_APPLOADER)
+#if defined(BOOTLOADER_SECURE)
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00014000UL)
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00012000UL)
+#endif // BOOTLOADER_SECURE
+#elif defined(BOOTLOADER_CUSTOM_SIZE)
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00004000UL)
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00006000UL)
+#endif // BOOTLOADER_APPLOADER
+#define BTL_MAIN_STAGE_MAX_SIZE           (BTL_APPLICATION_BASE    \
+                                           - (BTL_FIRST_STAGE_BASE \
+                                              + BTL_FIRST_STAGE_SIZE))
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_215)
+// No bootloader area: Place the bootloader in main flash
+#define BTL_FIRST_STAGE_BASE              FLASH_BASE
+#if defined(BOOTLOADER_APPLOADER)
+#if defined(BOOTLOADER_SECURE)
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00014000UL)
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00012000UL)
+#endif // BOOTLOADER_SECURE
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00006000UL)
+#endif // BOOTLOADER_APPLOADER
+#define BTL_MAIN_STAGE_MAX_SIZE           (BTL_APPLICATION_BASE    \
+                                           - (BTL_FIRST_STAGE_BASE \
+                                              + BTL_FIRST_STAGE_SIZE))
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_220)
+// No bootloader area: Place the bootloader in main flash
+#define BTL_FIRST_STAGE_BASE              FLASH_BASE
+#if defined(BOOTLOADER_APPLOADER)
+#if defined(BOOTLOADER_SECURE)
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00014000UL)
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00012000UL)
+#endif // BOOTLOADER_SECURE
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00006000UL)
+#endif // BOOTLOADER_APPLOADER
+#define BTL_MAIN_STAGE_MAX_SIZE           (BTL_APPLICATION_BASE    \
+                                           - (BTL_FIRST_STAGE_BASE \
+                                              + BTL_FIRST_STAGE_SIZE))
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_225)
+// No bootloader area: Place the bootloader in main flash
+#define BTL_FIRST_STAGE_BASE              FLASH_BASE
+#if defined(BOOTLOADER_APPLOADER)
+#if defined(BOOTLOADER_SECURE)
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00014000UL)
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00012000UL)
+#endif // BOOTLOADER_SECURE
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00006000UL)
+#endif // BOOTLOADER_APPLOADER
+#define BTL_MAIN_STAGE_MAX_SIZE           (BTL_APPLICATION_BASE    \
+                                           - (BTL_FIRST_STAGE_BASE \
+                                              + BTL_FIRST_STAGE_SIZE))
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_230)
+// No bootloader area: Place the bootloader in main flash
+#define BTL_FIRST_STAGE_BASE              FLASH_BASE
+#if defined(BOOTLOADER_APPLOADER)
+#if defined(BOOTLOADER_SECURE)
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00014000UL)
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00012000UL)
+#endif // BOOTLOADER_SECURE
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00006000UL)
+#endif // BOOTLOADER_APPLOADER
+#define BTL_MAIN_STAGE_MAX_SIZE           (BTL_APPLICATION_BASE    \
+                                           - (BTL_FIRST_STAGE_BASE \
+                                              + BTL_FIRST_STAGE_SIZE))
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_235)
+// No bootloader area: Place the bootloader in main flash
+#define BTL_FIRST_STAGE_BASE              FLASH_BASE
+#if defined(BOOTLOADER_APPLOADER)
+#if defined(BOOTLOADER_SECURE)
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00014000UL)
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00012000UL)
+#endif // BOOTLOADER_SECURE
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00006000UL)
+#endif // BOOTLOADER_APPLOADER
+#define BTL_MAIN_STAGE_MAX_SIZE           (BTL_APPLICATION_BASE    \
+                                           - (BTL_FIRST_STAGE_BASE \
+                                              + BTL_FIRST_STAGE_SIZE))
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_240)
+// No bootloader area: Place the bootloader in main flash
+#define BTL_FIRST_STAGE_BASE              FLASH_BASE
+#if defined(BOOTLOADER_APPLOADER)
+#if defined(BOOTLOADER_SECURE)
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00014000UL)
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00012000UL)
+#endif // BOOTLOADER_SECURE
+#else
+#define BTL_APPLICATION_BASE              (FLASH_BASE + 0x00006000UL)
+#endif // BOOTLOADER_APPLOADER
+#define BTL_MAIN_STAGE_MAX_SIZE           (BTL_APPLICATION_BASE    \
+                                           - (BTL_FIRST_STAGE_BASE \
+                                              + BTL_FIRST_STAGE_SIZE))
+#else
+#error "This part is not supported in this bootloader version."
+#endif
+
+#if defined(MAIN_BOOTLOADER_TEST) || defined(MAIN_BOOTLOADER_IN_MAIN_FLASH)
+#define BTL_MAIN_STAGE_BASE               (FLASH_BASE)
+#else
+#define BTL_MAIN_STAGE_BASE               (BTL_FIRST_STAGE_BASE \
+                                           + BTL_FIRST_STAGE_SIZE)
+#endif
+
+#if defined(BOOTLOADER_HAS_FIRST_STAGE)
+#define BTL_FIRST_BOOTLOADER_TABLE_BASE   (BTL_FIRST_STAGE_BASE \
+                                           + offsetof(BareBootTable_t, table))
+#endif
+#define BTL_MAIN_BOOTLOADER_TABLE_BASE    (BTL_MAIN_STAGE_BASE \
+                                           + offsetof(BareBootTable_t, table))
+
+/// @endcond // DO_NOT_INCLUDE_WITH_DOXYGEN
+
+#if defined(MAIN_BOOTLOADER_TEST)
+#if defined(BOOTLOADER_HAS_FIRST_STAGE)
+extern FirstBootloaderTable_t * firstBootloaderTable;
+#endif
+extern MainBootloaderTable_t *mainBootloaderTable;
+#else
+#if defined(BOOTLOADER_HAS_FIRST_STAGE)
+/// Pointer to first stage bootloader table
+#define firstBootloaderTable              (*(FirstBootloaderTable_t **) \
+                                           (BTL_FIRST_BOOTLOADER_TABLE_BASE))
+#endif // BOOTLOADER_HAS_FIRST_STAGE
+/// Pointer to main bootloader table
+#define mainBootloaderTable               (*(MainBootloaderTable_t **) \
+                                           (BTL_MAIN_BOOTLOADER_TABLE_BASE))
+#endif // MAIN_BOOTLOADER_TEST
+// --------------------------------
+// Functions
+
+/***************************************************************************//**
+ * Get information about the bootloader on this device.
+ *
+ * The returned information is fetched from the main bootloader
+ * information table.
+ *
+ * @param[out] info Pointer to the bootloader information struct.
+ ******************************************************************************/
+void bootloader_getInfo(BootloaderInformation_t *info);
+
+/***************************************************************************//**
+ * Initialize components of the bootloader
+ * so the app can use the interface. This typically includes initializing
+ * serial peripherals for communication with external SPI flashes, and so on.
+ *
+ * @return Error code. @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_INIT_BASE range.
+ ******************************************************************************/
+int32_t bootloader_init(void);
+
+/***************************************************************************//**
+ * De-initialize components of the bootloader that were previously initialized.
+ * This typically includes powering down external SPI flashes and
+ * de-initializing the serial peripheral used for communication with the
+ * external flash.
+ *
+ * @return Error code. @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_INIT_BASE range.
+ ******************************************************************************/
+int32_t bootloader_deinit(void);
+
+/***************************************************************************//**
+ * Reboot into the bootloader to perform an install.
+ *
+ * If there is a storage component and a slot is marked for bootload, install
+ * the image in that slot after verifying it.
+ *
+ * If a communication component is present, open the communication channel and
+ * receive an image to be installed.
+ ******************************************************************************/
+void bootloader_rebootAndInstall(void);
+
+/***************************************************************************//**
+ * Verify the application image stored in the Flash memory starting at
+ * the address startAddress.
+ *
+ * If the secure boot is enforced, the function will only return true if the
+ * cryptographic signature of the application is valid. Otherwise, the
+ * application is verified according to the signature type defined in the
+ * ApplicationProperties_t structure embedded in the application. Silicon Labs
+ * wireless stacks include a declaration of this structure. However,
+ * applications not using a full wireless stack may need to instantiate
+ * the structure.
+ *
+ * Examples of results when the secure boot is not enforced:
+ * - App has no signature: Valid if initial stack pointer and program counter
+ *                         have reasonable values.
+ * - App has CRC checksum: Valid if checksum is valid.
+ * - App has ECDSA signature: Valid if ECDSA signature is valid.
+ *
+ * When secure boot is enforced, only ECDSA signed applications with
+ * a valid signature are considered valid.
+ *
+ *
+ * @param[in] startAddress Starting address of the application.
+ *
+ * @return True if the application is valid, else false.
+ ******************************************************************************/
+bool bootloader_verifyApplication(uint32_t startAddress);
+
+/***************************************************************************//**
+ * Check whether signature verification on the application image in internal flash
+ * is enforced before every boot.
+ *
+ * @return True if signature verification is enforced, else false.
+ ******************************************************************************/
+bool bootloader_secureBootEnforced(void);
+
+/***************************************************************************//**
+ * Get base address of the bootloader upgrade image.
+ *
+ * @param[out] location the base address of bootloader upgrade image.
+ *
+ * @return Returns true if the location was found.
+ ******************************************************************************/
+bool bootloader_getUpgradeLocation(uint32_t *location);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+/***************************************************************************//**
+ * Get the list of the peripheral that is used by the bootloader.
+ *
+ * @param[out] ppusatd0      Word containing all the peripherals used by the
+ *                           bootloader. Each bit represents a peripheral,
+ *                           which is ordered after the PPUSATD0 register bit
+ *                           fields.
+ *
+ * @param[out] ppusatd1      Word containing all the peripherals used by the
+ *                           bootloader. Each bit represents a peripheral,
+ *                           which is ordered after the PPUSATD1 register bit
+ *                           fields.
+ ******************************************************************************/
+#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+void bootloader_getPeripheralList(uint32_t *ppusatd0, uint32_t *ppusatd1, uint32_t *ppusatd2);
+#else
+void bootloader_getPeripheralList(uint32_t *ppusatd0, uint32_t *ppusatd1);
+#endif
+
+/***************************************************************************//**
+ * Save PPUSATDn state in RAM.
+ * Configure the peripheral attributes before calling into the bootloader.
+ *
+ * @note Enters ATOMIC section.
+ *
+ * @param[out] ctx      Context struct to save register state into
+ *
+ * @return True if a valid certificate version is found.
+ ******************************************************************************/
+void bootloader_ppusatdnSaveReconfigureState(Bootloader_PPUSATDnCLKENnState_t *ctx);
+
+/***************************************************************************//**
+ * Restore PPUSATDn state from RAM.
+ * Store the USART used by the bootloader if this is unknown.
+ *
+ * @note Exits ATOMIC section.
+ *
+ * @param[in] ctx      Context struct to restore register state from
+ *
+ * @return True if a valid certificate version is found.
+ ******************************************************************************/
+void bootloader_ppusatdnRestoreState(Bootloader_PPUSATDnCLKENnState_t *ctx);
+
+/***************************************************************************//**
+ * Called before the bootloader is initialized.
+ *
+ * This function implementation does not perform anything, but it is __weak
+ * so that it can be implemented by another application.
+ ******************************************************************************/
+void sli_bootloader_preHook(void);
+
+/***************************************************************************//**
+ * Called after the bootloader is de-initialized.
+ *
+ * This function implementation does not perform anything, but it is __weak
+ * so that it can be implemented by another application.
+ ******************************************************************************/
+void sli_bootloader_postHook(void);
+#endif
+
+#if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
+/***************************************************************************//**
+ * Count the total remaining number of application upgrades.
+ *
+ * @return remaining number of application upgrades.
+ ******************************************************************************/
+uint32_t bootloader_remainingApplicationUpgrades(void);
+#endif
+
+#if defined(_SILICON_LABS_32B_SERIES_2)
+/***************************************************************************//**
+ * Get bootloader certificate version.
+ *
+ * @param[out] version           Bootloader certificate version
+ *
+ * @return True if a valid certificate version is found.
+ ******************************************************************************/
+bool bootloader_getCertificateVersion(uint32_t *version);
+#endif // _SILICON_LABS_32B_SERIES_2
+
+/***************************************************************************//**
+ * Get reset cause of the bootloader.
+ *
+ * @return Reset cause of the bootloader.
+ ******************************************************************************/
+BootloaderResetCause_t bootloader_getResetReason(void);
+
+#if defined(BOOTLOADER_HAS_FIRST_STAGE)
+/***************************************************************************//**
+ * Check if a pointer is valid and if it points to the bootloader first stage.
+ *
+ * This function checks pointers to bootloader
+ * jump tables.
+ *
+ *
+ * @param[in] ptr The pointer to check
+ *
+ * @return True if the pointer points to the bootloader first stage,
+ *         false if not.
+ ******************************************************************************/
+__STATIC_INLINE bool bootloader_pointerToFirstStageValid(const void *ptr);
+__STATIC_INLINE bool bootloader_pointerToFirstStageValid(const void *ptr)
+{
+#if defined(MAIN_BOOTLOADER_TEST)
+  // In main bootloader tests, no first stage is present
+  (void) ptr;
+  return false;
+#elif BTL_FIRST_STAGE_BASE > 0U
+  if (((size_t)(ptr) >= BTL_FIRST_STAGE_BASE)
+      && ((size_t)(ptr) < (BTL_FIRST_STAGE_BASE + BTL_FIRST_STAGE_SIZE))) {
+    return true;
+  } else {
+    return false;
+  }
+#else
+  // First stage starts at address 0, don't need to check lower bound
+  if ((size_t)(ptr) < (BTL_FIRST_STAGE_BASE + BTL_FIRST_STAGE_SIZE)) {
+    return true;
+  } else {
+    return false;
+  }
+#endif
+}
+#endif // BOOTLOADER_HAS_FIRST_STAGE
+
+/***************************************************************************//**
+ * Check if a pointer is valid and if it points to the bootloader main stage.
+ *
+ * This function checks pointers to bootloader
+ * jump tables.
+ *
+ *
+ * @param[in] ptr The pointer to check
+ *
+ * @return True if the pointer points into the bootloader main stage,
+ *         false if not.
+ ******************************************************************************/
+__STATIC_INLINE bool bootloader_pointerValid(const void *ptr);
+__STATIC_INLINE bool bootloader_pointerValid(const void *ptr)
+{
+#if defined(MAIN_BOOTLOADER_TEST)
+  // In main bootloader tests, all of memory is considered part of the bootloader
+  (void) ptr;
+  return true;
+#elif BTL_MAIN_STAGE_BASE > 0U
+  if (((size_t)ptr >= BTL_MAIN_STAGE_BASE)
+      && ((size_t)ptr < (BTL_MAIN_STAGE_BASE + BTL_MAIN_STAGE_MAX_SIZE))) {
+    return true;
+  } else {
+    return false;
+  }
+#else
+  if ((size_t)ptr < (BTL_MAIN_STAGE_BASE + BTL_MAIN_STAGE_MAX_SIZE)) {
+    return true;
+  } else {
+    return false;
+  }
+#endif
+}
+
+/** @} (end addtogroup CommonInterface) */
+/** @} (end addtogroup Interface) */
+#if defined(__GNUC__)
+#pragma GCC diagnostic pop
+#endif
+
+#endif // BTL_INTERFACE_H

Libs/platform/bootloader/api/btl_interface_parser.h

@@ -0,0 +1,138 @@
+/***************************************************************************//**
+ * @file
+ * @brief Application interface to the bootloader parser.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * The licensor of this software is Silicon Laboratories Inc.  Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement.  This
+ * software is distributed to you in Source Code format and is governed by the
+ * sections of the MSLA applicable to Source Code.
+ *
+ ******************************************************************************/
+
+#ifndef BTL_INTERFACE_PARSER_H
+#define BTL_INTERFACE_PARSER_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/***************************************************************************//**
+ * @addtogroup Interface
+ * @{
+ * @addtogroup ParserInterface Application Parser Interface
+ * @brief Application interface for the bootloader image
+ *        parser.
+ * @details The Parser Interface can be used to parse upgrade images from the
+ *          context of the application.
+ * @{
+ ******************************************************************************/
+
+// -----------------------------------------------------------------------------
+// Typedefs
+
+/***************************************************************************//**
+ * Bootloader parser callback
+ *
+ * @param address Address of the data
+ * @param data    Raw data
+ * @param length  Size in bytes of raw data.
+ * @param context A context variable defined by the implementation that
+ *                is implementing this callback.
+ ******************************************************************************/
+typedef void (*BootloaderParserCallback_t)(uint32_t address,
+                                           uint8_t  *data,
+                                           size_t   length,
+                                           void     *context);
+
+/// Context for the bootloader image parser routine.
+typedef struct BootloaderParserContext BootloaderParserContext_t;
+
+/// Function pointers to parser callbacks
+typedef struct {
+  /// Opaque pointer passed to the callback functions
+  void                        *context;
+  /// Callback function pointer for application image data
+  BootloaderParserCallback_t  applicationCallback;
+  /// Callback function pointer for image metadata
+  BootloaderParserCallback_t  metadataCallback;
+  /// Callback function pointer for bootloader upgrade image data
+  BootloaderParserCallback_t  bootloaderCallback;
+} BootloaderParserCallbacks_t;
+
+/***************************************************************************//**
+ * Initialize the image parser.
+ *
+ * @param[in] context     Pointer to the parser context struct.
+ * @param[in] contextSize Size of the context struct.
+ *
+ * @return BOOTLOADER_OK if success, BOOTLOADER_ERROR_PARSE_CONTEXT if context
+ *         struct is too small.
+ ******************************************************************************/
+int32_t bootloader_initParser(BootloaderParserContext_t *context,
+                              size_t                    contextSize);
+
+#if !defined(SL_TRUSTZONE_NONSECURE)
+/***************************************************************************//**
+ * Parse a buffer.
+ * @param[in] context   Pointer to the parser context struct.
+ * @param[in] callbacks Callbacks to be called by the parser.
+ * @param[in] data      Data to be parsed.
+ * @param[in] numBytes  Size of the data buffer.
+ *
+ * @return BOOTLOADER_ERROR_PARSE_CONTINUE if the chunk was parsed correctly,
+ *         and a new chunk is expected. BOOTLOADER_ERROR_PARSE_ERROR if
+ *         something went wrong while parsing. BOOTLOADER_ERROR_PARSE_SUCCESS
+ *         if the entire file was successfully parsed.
+ ******************************************************************************/
+int32_t bootloader_parseBuffer(BootloaderParserContext_t   *context,
+                               BootloaderParserCallbacks_t *callbacks,
+                               uint8_t                     data[],
+                               size_t                      numBytes);
+#endif // SL_TRUSTZONE_NONSECURE
+
+/***************************************************************************//**
+ * Parse a buffer and get application and bootloader upgrade metadata
+ * from the buffer.
+ *
+ * @note \p appInfo and \p bootloaderVersion will default to zeros.
+ *
+ * @param[in]  context           Pointer to the parser context struct.
+ * @param[in]  data              Data to be parsed.
+ * @param[in]  numBytes          Size of the data buffer.
+ * @param[out] appInfo           Pointer to @ref ApplicationData_t struct.
+ * @param[out] bootloaderVersion Pointer to an integer representing bootloader
+ *                               version.
+ *
+ * @return @ref BOOTLOADER_OK if metadata was filled successfully.
+ ******************************************************************************/
+#if !defined(SL_TRUSTZONE_NONSECURE)
+int32_t bootloader_parseImageInfo(BootloaderParserContext_t *context,
+                                  uint8_t                   data[],
+                                  size_t                    numBytes,
+                                  ApplicationData_t         *appInfo,
+                                  uint32_t                  *bootloaderVersion);
+#else
+int32_t bootloader_parseImageInfo(uint8_t                   data[],
+                                  size_t                    numBytes,
+                                  ApplicationData_t         *appInfo,
+                                  uint32_t                  *bootloaderVersion);
+#endif // SL_TRUSTZONE_NONSECURE
+
+/***************************************************************************//**
+ * Find the size of the context struct BootloaderParserContext used by the bootloader
+ * image parser to store parser state.
+ *
+ * @return size of BootloaderParserContext, returns 0 if something went wrong.
+ ******************************************************************************/
+uint32_t bootloader_parserContextSize(void);
+
+/** @} (end addtogroup ParserInterface) */
+/** @} (end addtogroup Interface) */
+
+#endif // BTL_INTERFACE_PARSER_H

Libs/platform/bootloader/api/btl_interface_storage.c

@@ -0,0 +1,769 @@
+/***************************************************************************//**
+ * @file
+ * @brief Application interface to the storage component of the bootloader.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * The licensor of this software is Silicon Laboratories Inc.  Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement.  This
+ * software is distributed to you in Source Code format and is governed by the
+ * sections of the MSLA applicable to Source Code.
+ *
+ ******************************************************************************/
+
+#include "btl_interface.h"
+#include "btl_internal_flash.h"
+#include <string.h>
+
+// -----------------------------------------------------------------------------
+// Defines
+
+// Make assert no-op if not configured
+#ifndef BTL_ASSERT
+#define BTL_ASSERT(x)
+#endif
+#if defined(__GNUC__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
+#endif
+// -----------------------------------------------------------------------------
+// Static variables
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+static Bootloader_PPUSATDnCLKENnState_t blPPUSATDnCLKENnState = { 0 };
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+// -----------------------------------------------------------------------------
+// Functions
+
+static bool verifyAddressRange(uint32_t address,
+                               uint32_t length)
+{
+  // Flash starts at FLASH_BASE, and is FLASH_SIZE large
+  if ((length > FLASH_SIZE)
+#if (FLASH_BASE > 0x0UL)
+      || (address < FLASH_BASE)
+#endif
+      || (address > FLASH_BASE + FLASH_SIZE)) {
+    return false;
+  }
+
+  if ((address + length) <= FLASH_BASE + FLASH_SIZE) {
+    return true;
+  } else {
+    return false;
+  }
+}
+
+static bool verifyErased(uint32_t address,
+                         uint32_t length)
+{
+  for (uint32_t i = 0; i < length; i += 4) {
+    if (*(uint32_t *)(address + i) != 0xFFFFFFFF) {
+      return false;
+    }
+  }
+  return true;
+}
+
+void bootloader_getStorageInfo(BootloaderStorageInformation_t *info)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)
+      || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+    return;
+  }
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  mainBootloaderTable->storage->getInfo(info);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+}
+
+int32_t bootloader_getStorageSlotInfo(uint32_t                slotId,
+                                      BootloaderStorageSlot_t *slot)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)
+      || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+    return BOOTLOADER_ERROR_INIT_TABLE;
+  }
+  return mainBootloaderTable->storage->getSlotInfo(slotId, slot);
+}
+
+int32_t bootloader_readStorage(uint32_t slotId,
+                               uint32_t offset,
+                               uint8_t  *buffer,
+                               size_t   length)
+{
+  int32_t retVal;
+  BootloaderStorageInformation_t storageInfo;
+  BootloaderStorageSlot_t storageSlot;
+
+  //Check for the storageType of the device
+  bootloader_getStorageInfo(&storageInfo);
+
+  if (storageInfo.storageType == INTERNAL_FLASH) {
+    // Ensure slot is valid
+    if (slotId >= storageInfo.numStorageSlots) {
+      return BOOTLOADER_ERROR_STORAGE_INVALID_SLOT;
+    }
+
+    retVal = bootloader_getStorageSlotInfo(slotId, &storageSlot);
+    if (retVal != BOOTLOADER_OK) {
+      return retVal;
+    }
+
+    // Ensure address is within slot
+    if ((offset + length > storageSlot.length) \
+        || (offset > storageSlot.length)       \
+        || (length > storageSlot.length)) {
+      return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS;
+    }
+
+    // Address range is valid; read data
+    retVal = bootloader_readRawStorage(storageSlot.address + offset,
+                                       buffer,
+                                       length);
+  }
+  //END OF INTERNAL_FLASH
+  else {
+    if (!bootloader_pointerValid(mainBootloaderTable)
+        || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+      return BOOTLOADER_ERROR_INIT_TABLE;
+    }
+
+  #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+  #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+    retVal = mainBootloaderTable->storage->read(slotId, offset, buffer, length);
+
+  #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+  #endif
+  }
+
+  return retVal;
+}
+
+int32_t bootloader_writeStorage(uint32_t slotId,
+                                uint32_t offset,
+                                uint8_t  *buffer,
+                                size_t   length)
+{
+  int32_t retVal;
+  BootloaderStorageInformation_t storageInfo;
+  BootloaderStorageSlot_t storageSlot;
+
+  //Check for the storageType of the device
+  bootloader_getStorageInfo(&storageInfo);
+
+  if (storageInfo.storageType == INTERNAL_FLASH) {
+    // Ensure slot is valid
+    if (slotId >= storageInfo.numStorageSlots) {
+      return BOOTLOADER_ERROR_STORAGE_INVALID_SLOT;
+    }
+
+    retVal = bootloader_getStorageSlotInfo(slotId, &storageSlot);
+    if (retVal != BOOTLOADER_OK) {
+      return retVal;
+    }
+
+    // Ensure address is within slot
+    if ((offset + length > storageSlot.length) \
+        || (offset > storageSlot.length)       \
+        || (length > storageSlot.length)) {
+      return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS;
+    }
+
+    retVal = bootloader_writeRawStorage(storageSlot.address + offset,
+                                        buffer,
+                                        length);
+  } else {
+    if (!bootloader_pointerValid(mainBootloaderTable)
+        || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+      return BOOTLOADER_ERROR_INIT_TABLE;
+    }
+
+  #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+  #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+    retVal = mainBootloaderTable->storage->write(slotId, offset, buffer, length);
+
+  #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+  #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+  }
+
+  return retVal;
+}
+
+int32_t bootloader_eraseWriteStorage(uint32_t slotId,
+                                     uint32_t offset,
+                                     uint8_t  *buffer,
+                                     size_t   length)
+{
+  int32_t retVal;
+  uint16_t flashPageSize;
+  uint32_t storageStartAddr;
+  uint32_t eraseOffset;
+  uint32_t eraseLength;
+  BootloaderStorageSlot_t storageSlot;
+  BootloaderStorageInformation_t storageInfo;
+
+  if (!bootloader_pointerValid(mainBootloaderTable)
+      || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+    return BOOTLOADER_ERROR_INIT_TABLE;
+  }
+
+  bootloader_getStorageInfo(&storageInfo);
+  flashPageSize = storageInfo.info->pageSize;
+  if (flashPageSize == 0) {
+    return BOOTLOADER_ERROR_STORAGE_INVALID_SLOT;
+  }
+
+  retVal = bootloader_getStorageSlotInfo(slotId, &storageSlot);
+  if (retVal != BOOTLOADER_OK) {
+    return retVal;
+  }
+  storageStartAddr = storageSlot.address;
+
+  if (offset + length > storageSlot.length) {
+    return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS;
+  }
+
+  if (offset % flashPageSize) {
+    // Erase from next page:
+    eraseOffset = (offset & ~(flashPageSize - 1)) + flashPageSize;
+
+    if ((offset + length) % flashPageSize) {
+      // Example case for this if/else section:
+      // 0    1    2    3
+      // |----|----|----|
+      //   ^          ^
+      //   O          L
+      eraseLength = ((offset + length) & ~(flashPageSize - 1)) + flashPageSize - eraseOffset;
+    } else {
+      // Example case for this if/else section:
+      // 0    1    2    3
+      // |----|----|----|
+      //   ^            ^
+      //   O            L
+      eraseLength = length - (flashPageSize - (offset % flashPageSize));
+    }
+    eraseOffset = storageStartAddr + eraseOffset;
+  } else {
+    eraseOffset = storageStartAddr + offset;
+    if (length % flashPageSize) {
+      // Example case for this if/else section:
+      // 0    1    2    3
+      // |----|----|----|
+      //      ^       ^
+      //      O       L
+      eraseLength = (length & ~(flashPageSize - 1)) + flashPageSize;
+    } else {
+      // Example case for this if/else section:
+      // 0    1    2    3
+      // |----|----|----|
+      //      ^         ^
+      //      O         L
+      eraseLength = length;
+    }
+  }
+  if (eraseLength != 0) {
+    retVal = bootloader_eraseRawStorage(eraseOffset, eraseLength);
+    if (retVal != BOOTLOADER_OK) {
+      return retVal;
+    }
+  }
+
+  retVal = bootloader_writeRawStorage(storageStartAddr + offset, buffer, length);
+  if (retVal != BOOTLOADER_OK) {
+    return retVal;
+  }
+
+  return BOOTLOADER_OK;
+}
+
+int32_t bootloader_eraseStorageSlot(uint32_t slotId)
+{
+  int32_t retVal;
+  BootloaderStorageInformation_t storageInfo;
+  BootloaderStorageSlot_t storageSlot;
+
+  //Check for the storageType of the device
+  bootloader_getStorageInfo(&storageInfo);
+
+  if (storageInfo.storageType == INTERNAL_FLASH) {
+    // Ensure slot is valid
+    if (slotId >= storageInfo.numStorageSlots) {
+      return BOOTLOADER_ERROR_STORAGE_INVALID_SLOT;
+    }
+
+    retVal = bootloader_getStorageSlotInfo(slotId, &storageSlot);
+    if (retVal != BOOTLOADER_OK) {
+      return retVal;
+    }
+
+    retVal = bootloader_eraseRawStorage(storageSlot.address, storageSlot.length);
+  } else {
+    if (!bootloader_pointerValid(mainBootloaderTable)
+        || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+      return BOOTLOADER_ERROR_INIT_TABLE;
+    }
+
+  #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+  #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+    retVal = mainBootloaderTable->storage->erase(slotId);
+
+  #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+  #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+  }
+
+  return retVal;
+}
+
+int32_t bootloader_initChunkedEraseStorageSlot(uint32_t                slotId,
+                                               BootloaderEraseStatus_t *eraseStat)
+{
+  int32_t retVal;
+  BootloaderStorageInformation_t storageInfo;
+  bootloader_getStorageInfo(&storageInfo);
+
+  retVal = bootloader_getStorageSlotInfo(slotId, &eraseStat->storageSlotInfo);
+  if (retVal != BOOTLOADER_OK) {
+    return retVal;
+  }
+
+  eraseStat->currentPageAddr = eraseStat->storageSlotInfo.address;
+  eraseStat->pageSize = storageInfo.info->pageSize;
+
+  return BOOTLOADER_OK;
+}
+
+int32_t bootloader_chunkedEraseStorageSlot(BootloaderEraseStatus_t *eraseStat)
+{
+  int32_t retVal;
+  if (eraseStat->currentPageAddr
+      == (eraseStat->storageSlotInfo.address + eraseStat->storageSlotInfo.length)) {
+    return BOOTLOADER_OK;
+  }
+
+  retVal = bootloader_eraseRawStorage(eraseStat->currentPageAddr, eraseStat->pageSize);
+  if (retVal != BOOTLOADER_OK) {
+    return retVal;
+  }
+
+  eraseStat->currentPageAddr += eraseStat->pageSize;
+  if (eraseStat->currentPageAddr
+      == (eraseStat->storageSlotInfo.address + eraseStat->storageSlotInfo.length)) {
+    return BOOTLOADER_OK;
+  }
+
+  return BOOTLOADER_ERROR_STORAGE_CONTINUE;
+}
+
+int32_t bootloader_setImageToBootload(int32_t slotId)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)
+      || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+    return BOOTLOADER_ERROR_INIT_TABLE;
+  }
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  int32_t retVal = mainBootloaderTable->storage->setImagesToBootload(&slotId, 1);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  return retVal;
+}
+
+int32_t bootloader_setImagesToBootload(int32_t *slotIds, size_t length)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)
+      || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+    return BOOTLOADER_ERROR_INIT_TABLE;
+  }
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  int32_t retVal = mainBootloaderTable->storage->setImagesToBootload(slotIds, length);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  return retVal;
+}
+
+int32_t bootloader_getImagesToBootload(int32_t *slotIds, size_t length)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)
+      || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+    return BOOTLOADER_ERROR_INIT_TABLE;
+  }
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  int32_t retVal = mainBootloaderTable->storage->getImagesToBootload(slotIds, length);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  return retVal;
+}
+
+int32_t bootloader_appendImageToBootloadList(int32_t slotId)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)
+      || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+    return BOOTLOADER_ERROR_INIT_TABLE;
+  }
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  int32_t retVal = mainBootloaderTable->storage->appendImageToBootloadList(slotId);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  return retVal;
+}
+
+int32_t bootloader_initVerifyImage(uint32_t slotId,
+                                   void     *context,
+                                   size_t   contextSize)
+{
+  int32_t retVal;
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return BOOTLOADER_ERROR_PARSE_STORAGE;
+  }
+
+  // Check that the bootloader has image verification capability
+  if (mainBootloaderTable->storage == NULL) {
+    return BOOTLOADER_ERROR_PARSE_STORAGE;
+  }
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  retVal = mainBootloaderTable->storage->initParseImage(
+    slotId,
+    (BootloaderParserContext_t*)context,
+    contextSize);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  return retVal;
+}
+
+int32_t bootloader_continueVerifyImage(void                       *context,
+                                       BootloaderParserCallback_t metadataCallback)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)
+      || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+    return BOOTLOADER_ERROR_PARSE_STORAGE;
+  }
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  int32_t retVal = mainBootloaderTable->storage->verifyImage(
+    (BootloaderParserContext_t *)context,
+    metadataCallback);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  return retVal;
+}
+
+int32_t bootloader_verifyImage(uint32_t                   slotId,
+                               BootloaderParserCallback_t metadataCallback)
+{
+  int32_t retval;
+  uint8_t context[BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE];
+
+  if (!bootloader_pointerValid(mainBootloaderTable)) {
+    return BOOTLOADER_ERROR_PARSE_STORAGE;
+  }
+
+  retval = bootloader_initVerifyImage(slotId,
+                                      context,
+                                      BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE);
+
+  if (retval != BOOTLOADER_OK) {
+    return retval;
+  }
+
+  do {
+    retval = bootloader_continueVerifyImage(context, metadataCallback);
+  } while (retval == BOOTLOADER_ERROR_PARSE_CONTINUE);
+
+  if (retval == BOOTLOADER_ERROR_PARSE_SUCCESS) {
+    return BOOTLOADER_OK;
+  } else {
+    return retval;
+  }
+}
+
+int32_t bootloader_getImageInfo(uint32_t          slotId,
+                                ApplicationData_t *appInfo,
+                                uint32_t          *bootloaderVersion)
+{
+  int32_t retval;
+  uint8_t context[BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE];
+
+  if (!bootloader_pointerValid(mainBootloaderTable)
+      || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+    return BOOTLOADER_ERROR_PARSE_STORAGE;
+  }
+
+  // Check that the bootloader has image verification capability
+  BTL_ASSERT(mainBootloaderTable->storage != NULL);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  retval = mainBootloaderTable->storage->initParseImage(
+    slotId,
+    (BootloaderParserContext_t *)context,
+    BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE);
+  if (retval != BOOTLOADER_OK) {
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+    return retval;
+  }
+  retval = mainBootloaderTable->storage->getImageInfo(
+    (BootloaderParserContext_t *)context,
+    appInfo,
+    bootloaderVersion);
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  return retval;
+}
+
+bool bootloader_storageIsBusy(void)
+{
+  bool isBusy = false;
+
+  if (!bootloader_pointerValid(mainBootloaderTable)
+      || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+    return true;
+  }
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  isBusy = mainBootloaderTable->storage->isBusy();
+
+#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+  bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+  return isBusy;
+}
+
+int32_t bootloader_readRawStorage(uint32_t address,
+                                  uint8_t  *buffer,
+                                  size_t   length)
+{
+  int32_t retVal;
+  BootloaderStorageInformation_t storageInfo;
+
+  //Check for the storageType of the device
+  bootloader_getStorageInfo(&storageInfo);
+
+  if (storageInfo.storageType == INTERNAL_FLASH) {
+    // Ensure address is is within flash
+    if (!verifyAddressRange(address, length)) {
+      return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS;
+    }
+
+    memcpy(buffer, (void *)address, length);
+
+    retVal = BOOTLOADER_OK;
+  } else {
+    if (!bootloader_pointerValid(mainBootloaderTable)
+        || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+      return BOOTLOADER_ERROR_INIT_STORAGE;
+    }
+    #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+    #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+    retVal = mainBootloaderTable->storage->readRaw(address, buffer, length);
+
+    #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+    #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+  }
+
+  return retVal;
+}
+
+int32_t bootloader_writeRawStorage(uint32_t address,
+                                   uint8_t  *buffer,
+                                   size_t   length)
+{
+  int32_t retVal;
+  BootloaderStorageInformation_t storageInfo;
+
+  //Check for the storageType of the device
+  bootloader_getStorageInfo(&storageInfo);
+
+  if (storageInfo.storageType == INTERNAL_FLASH) {
+    // Ensure address is is within chip
+    if (!verifyAddressRange(address, length)) {
+      return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS;
+    }
+    // Ensure space is empty
+    if (!verifyErased(address, length)) {
+      return BOOTLOADER_ERROR_STORAGE_NEEDS_ERASE;
+    }
+
+    if (flash_writeBuffer(address, buffer, length)) {
+      retVal = BOOTLOADER_OK;
+    } else {
+      retVal = BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS;
+    }
+    //END OF INTERNAL FLASH
+  } else {
+    if (!bootloader_pointerValid(mainBootloaderTable)
+        || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+      return BOOTLOADER_ERROR_INIT_STORAGE;
+    }
+
+    #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+    #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+    retVal = mainBootloaderTable->storage->writeRaw(address, buffer, length);
+
+    #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+    #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+  }
+
+  return retVal;
+}
+
+int32_t bootloader_getAllocatedDMAChannel(void)
+{
+  if (!bootloader_pointerValid(mainBootloaderTable)
+      || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+    return BOOTLOADER_ERROR_INIT_STORAGE;
+  }
+
+  BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U };
+  bootloader_getInfo(&info);
+
+  if ((info.capabilities & BOOTLOADER_CAPABILITY_STORAGE) == 0u) {
+    return BOOTLOADER_ERROR_INIT_STORAGE;
+  }
+
+  uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK)
+                             >> BOOTLOADER_VERSION_MAJOR_SHIFT);
+  uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK)
+                             >> BOOTLOADER_VERSION_MINOR_SHIFT);
+
+  if ((blMajorVersion < 1UL) || (blMajorVersion == 1UL && blMinorVersion < 11UL)) {
+    return BOOTLOADER_ERROR_INIT_STORAGE;
+  }
+
+  return mainBootloaderTable->storage->getDMAchannel();
+}
+
+int32_t bootloader_eraseRawStorage(uint32_t address,
+                                   size_t   length)
+{
+  int32_t retVal;
+  BootloaderStorageInformation_t storageInfo;
+
+  //Check for the storageType of the device
+  bootloader_getStorageInfo(&storageInfo);
+
+  if (storageInfo.storageType == INTERNAL_FLASH) {
+    // Ensure erase covers an integer number of pages
+    if (length % FLASH_PAGE_SIZE) {
+      return BOOTLOADER_ERROR_STORAGE_NEEDS_ALIGN;
+    }
+    // Ensure erase is page aligned
+    if (address % FLASH_PAGE_SIZE) {
+      return BOOTLOADER_ERROR_STORAGE_NEEDS_ALIGN;
+    }
+    // Ensure address is is within flash
+    if (!verifyAddressRange(address, length)) {
+      return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS;
+    }
+
+    bool ret = false;
+
+    do {
+      ret = flash_erasePage(address);
+      address += FLASH_PAGE_SIZE;
+      length -= FLASH_PAGE_SIZE;
+    } while (length > 0 && ret);
+
+    if (ret) {
+      retVal = BOOTLOADER_OK;
+    } else {
+      retVal = BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS;
+    }
+  } else {
+    if (!bootloader_pointerValid(mainBootloaderTable)
+        || !bootloader_pointerValid(mainBootloaderTable->storage)) {
+      return BOOTLOADER_ERROR_INIT_STORAGE;
+    }
+
+  #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState);
+  #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+
+    retVal = mainBootloaderTable->storage->eraseRaw(address, length);
+
+  #if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE)
+    bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState);
+  #endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE
+  }
+
+  return retVal;
+}
+
+#if defined(__GNUC__)
+#pragma GCC diagnostic pop
+#endif

Libs/platform/bootloader/api/btl_interface_storage.h

@@ -0,0 +1,653 @@
+/***************************************************************************//**
+ * @file
+ * @brief Application interface to the storage component of the bootloader.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * The licensor of this software is Silicon Laboratories Inc.  Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement.  This
+ * software is distributed to you in Source Code format and is governed by the
+ * sections of the MSLA applicable to Source Code.
+ *
+ ******************************************************************************/
+
+#ifndef BTL_INTERFACE_STORAGE_H
+#define BTL_INTERFACE_STORAGE_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+// Get part series version.
+#include "em_device.h"
+
+/***************************************************************************//**
+ * @addtogroup Interface
+ * @{
+ * @addtogroup StorageInterface Application Storage Interface
+ * @brief Application interface for interfacing with the bootloader storage.
+ * @note These Bootloader APIs are not reentrant and should be wrapped in critical section
+ *       where needed.
+ * @details The Storage Interface is only available on bootloaders that declare
+ *          they support @ref BOOTLOADER_CAPABILITY_STORAGE.
+ *
+ * @li @ref bootloader_interface_example
+ *
+ * @n @section bootloader_interface_example Example
+ *
+ * @brief Snippet for the OTA use case:
+ * @verbatim
+ * OTA Example
+ * Assuming the user has an upgrade image downloaded which will be used to upgrade the application
+ *
+ * Initialize the bootloader interface
+ * bootloader_init();
+ *
+ * Erase the storage slot in internal/SPI flash memory
+ * bootloader_eraseStorageSlot(0);
+ *
+ * Write the upgrade image (GBL file data) to the slot. blinkGbl  uint8 array holding the GBL data in memory
+ * bootloader_writeStorage(0, 0, blinkGbl, sizeof(blinkGbl));
+ *
+ * Reboot into the bootloader to install the new image
+ * bootloader_rebootAndInstall();
+ *
+ * The general flow for bootloader interface APIs from the application is:
+ *
+ * General flow
+ *
+ * Initialize the bootloader interface
+ * bootloader_init();
+ *
+ * Interface API accesses
+ * ……………
+ * ……………
+ * ……………
+ *
+ * De-initialize the bootloader interface
+ * bootloader_deinit();
+ * @endverbatim
+ * @{
+ ******************************************************************************/
+
+// -----------------------------------------------------------------------------
+// Typedefs
+
+/// Possible storage types
+typedef enum {
+  /// Storage backend is a SPI flash
+  SPIFLASH,
+  /// Storage backend is internal flash
+  INTERNAL_FLASH,
+  /// Storage backend is custom
+  CUSTOM_STORAGE
+} BootloaderStorageType_t;
+
+/// Information about a storage slot
+typedef struct {
+  /// Address of the slot.
+  uint32_t address;
+  /// Size of the slot.
+  uint32_t length;
+} BootloaderStorageSlot_t;
+
+/// Information about the bootloader storage implementation
+/// <b>Note:</b> From Gecko Bootloader version >= 2.1,
+/// the pointer <b>partType</b> will only contain a zero value.
+/// The <b>partType</b> variable can be used to find information
+/// about the attached storage.
+typedef struct {
+  /// The version of this data structure
+  uint16_t version;
+  /// A bitmask describing the capabilities of this particular storage
+  uint16_t capabilitiesMask;
+  /// Maximum time it takes to erase a page. (in milliseconds)
+  uint32_t pageEraseMs;
+  /// Maximum time it takes to erase the entire part. (in milliseconds)
+  uint32_t partEraseMs;
+  /// The size of a single erasable page in bytes
+  uint32_t pageSize;
+  /// The total size of the storage in bytes
+  uint32_t partSize;
+  /// Pointer to a string describing the attached storage
+  char *partDescription;
+  /// The number of bytes in a word for the storage
+  uint8_t wordSizeBytes;
+  /// Value representing the attached storage
+  uint32_t partType;
+} BootloaderStorageImplementationInformation_t;
+
+/// Information about the bootloader storage \n
+/// <b>Note:</b> The <b>flashInfo</b> variable is only usable with
+/// Gecko Bootloader version >= 2.0. All previous versions of the
+/// Gecko Bootloader do not support the <b>flashInfo</b> data field.
+typedef struct {
+  /// The version of this data structure
+  uint32_t version;
+  /// The capabilities of the storage component
+  uint32_t capabilities;
+  /// Type of storage
+  BootloaderStorageType_t storageType;
+  /// Number of storage slots
+  uint32_t numStorageSlots;
+  /// A pointer to detailed information about the attached storage
+  BootloaderStorageImplementationInformation_t *info;
+  /// Detailed information about the attached storage(<b>available for use only with Gecko Bootloader version >= 2.0</b>)
+  BootloaderStorageImplementationInformation_t flashInfo;
+} BootloaderStorageInformation_t;
+
+/// Erase status struct
+typedef struct {
+  /// Address of the current page to be erased
+  uint32_t currentPageAddr;
+  /// The size of a single erasable page in bytes
+  uint32_t pageSize;
+  /// Information about a storage slot
+  BootloaderStorageSlot_t storageSlotInfo;
+} BootloaderEraseStatus_t;
+
+/// Storage API accessible from the application
+typedef struct BootloaderStorageFunctions {
+  /// Version of this struct
+  uint32_t version;
+  /// Get information about the storage -- capabilities, layout, configuration
+  void (*getInfo)(BootloaderStorageInformation_t *info);
+  /// Get information about storage slot -- size, location
+  int32_t (*getSlotInfo)(uint32_t slotId, BootloaderStorageSlot_t *slot);
+  /// Read bytes from slot into buffer
+  int32_t (*read)(uint32_t slotId,
+                  uint32_t offset,
+                  uint8_t  *buffer,
+                  size_t   length);
+  /// Write bytes from buffer into slot
+  int32_t (*write)(uint32_t slotId,
+                   uint32_t offset,
+                   uint8_t  *buffer,
+                   size_t   length);
+  /// Erase an entire slot
+  int32_t (*erase)(uint32_t slotId);
+  // ------------------------------
+  /// Mark a list of slots for bootload
+  int32_t (*setImagesToBootload)(int32_t *slotIds, size_t length);
+  /// Mark a list of slots for bootload
+  int32_t (*getImagesToBootload)(int32_t *slotIds, size_t length);
+  /// Append a slot to bootload list
+  int32_t (*appendImageToBootloadList)(int32_t slotId);
+  // ------------------------------
+  /// Start image parsing
+  int32_t (*initParseImage)(uint32_t                  slotId,
+                            BootloaderParserContext_t *context,
+                            size_t                    contextSize);
+  /// Continue image verification
+  int32_t (*verifyImage)(BootloaderParserContext_t  *context,
+                         BootloaderParserCallback_t metadataCallback);
+  /// Get app and bootloader upgrade information from storage slot
+  int32_t (*getImageInfo)(BootloaderParserContext_t *context,
+                          ApplicationData_t         *appInfo,
+                          uint32_t                  *bootloaderVersion);
+  /// Check whether the bootloader storage is busy
+  bool (*isBusy)(void);
+  /// Read raw bytes from storage
+  int32_t (*readRaw)(uint32_t address, uint8_t *buffer, size_t length);
+  /// Write bytes to raw storage
+  int32_t (*writeRaw)(uint32_t address, uint8_t *buffer, size_t length);
+  /// Erase storage
+  int32_t (*eraseRaw)(uint32_t address, size_t length);
+  /// Get configured DMA channel
+  int32_t (*getDMAchannel)(void);
+} BootloaderStorageFunctions_t;
+
+// -----------------------------------------------------------------------------
+// Defines
+
+/// Context size for bootloader verification context
+#if defined(_SILICON_LABS_32B_SERIES_2)
+#if defined(SEMAILBOX_PRESENT)
+/// Context size(701) includes counter(16) plus stream_block(16 (block size) * 8 (Maximum blocks))
+#define BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE            (705)
+#else
+#define BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE            (593)
+#endif
+#else
+#define BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE            (384)
+#endif
+
+/// Current version of the BootloaderStorageInformation_t struct
+#define BOOTLOADER_STORAGE_INFO_VERSION                         (0x30000U)
+/// Current version of the BootloaderStorageImplementationInformation_t struct
+#define BOOTLOADER_STORAGE_IMPL_INFO_VERSION                    (0x0210U)
+/// Major version of the BootloaderStorageImplementationInformation_t struct
+#define BOOTLOADER_STORAGE_IMPL_INFO_VERSION_MAJOR              (0x0200U)
+/// Major version mask for @ref BOOTLOADER_STORAGE_IMPL_INFO_VERSION
+#define BOOTLOADER_STORAGE_IMPL_INFO_VERSION_MAJOR_MASK         (0xFF00U)
+
+/// Spiflash capability indicating that it supports erase
+#define BOOTLOADER_STORAGE_IMPL_CAPABILITY_ERASE_SUPPORTED      (1 << 0)
+/// @brief Spiflash capability indicating it requires full page erases before
+/// new data can be written
+#define BOOTLOADER_STORAGE_IMPL_CAPABILITY_PAGE_ERASE_REQUIRED  (1 << 1)
+/// Spiflash capability indicating that the write function is blocking
+#define BOOTLOADER_STORAGE_IMPL_CAPABILITY_BLOCKING_WRITE       (1 << 2)
+/// Spiflash capability indicating that the erase function is blocking
+#define BOOTLOADER_STORAGE_IMPL_CAPABILITY_BLOCKING_ERASE       (1 << 3)
+
+/// ISSI IS25LQ040B SPI Flash
+#define BOOTLOADER_STORAGE_ISSI_IS25LQ040B       (1U << 0)
+/// ISSI IS25LQ020B SPI Flash
+#define BOOTLOADER_STORAGE_ISSI_IS25LQ020B       (1U << 1)
+/// ISSI IS25LQ010B SPI Flash
+#define BOOTLOADER_STORAGE_ISSI_IS25LQ010B       (1U << 2)
+/// ISSI IS25LQ512B SPI Flash
+#define BOOTLOADER_STORAGE_ISSI_IS25LQ512B       (1U << 3)
+/// ISSI IS25LQ025B SPI Flash
+#define BOOTLOADER_STORAGE_ISSI_IS25LQ025B       (1U << 4)
+/// Numonyx M25P16 SPI Flash
+#define BOOTLOADER_STORAGE_NUMONYX_M25P16        (1U << 5)
+/// Numonyx M25P80 SPI Flash
+#define BOOTLOADER_STORAGE_NUMONYX_M25P80        (1U << 6)
+/// Numonyx M25P40 SPI Flash
+#define BOOTLOADER_STORAGE_NUMONYX_M25P40        (1U << 7)
+/// Numonyx M25P20 SPI Flash
+#define BOOTLOADER_STORAGE_NUMONYX_M25P20        (1U << 8)
+/// Adesto AT25SF041 SPI Flash
+#define BOOTLOADER_STORAGE_ADESTO_AT25SF041      (1U << 9)
+/// Atmel AT25DF081A SPI Flash
+#define BOOTLOADER_STORAGE_ATMEL_AT25DF081A      (1U << 10)
+/// Atmel AT25DF041A SPI Flash
+#define BOOTLOADER_STORAGE_ATMEL_AT25DF041A      (1U << 11)
+/// Macronix MX25R6435F SPI Flash
+#define BOOTLOADER_STORAGE_MACRONIX_MX25R6435F   (1U << 12)
+/// Macronix MX25R6435F SPI Flash
+#define BOOTLOADER_STORAGE_MACRONIX_MX25R3235F   (1U << 13)
+/// Macronix MX25U1635E SPI Flash
+#define BOOTLOADER_STORAGE_MACRONIX_MX25U1635E   (1U << 14)
+/// Macronix MX25L1606E SPI Flash
+#define BOOTLOADER_STORAGE_MACRONIX_MX25L1606E   (1U << 15)
+/// Macronix MX25R8035F SPI Flash
+#define BOOTLOADER_STORAGE_MACRONIX_MX25R8035F   (1U << 16)
+/// Macronix MX25L8006E SPI Flash
+#define BOOTLOADER_STORAGE_MACRONIX_MX25L8006E   (1U << 17)
+/// Macronix MX25L4006E SPI Flash
+#define BOOTLOADER_STORAGE_MACRONIX_MX25L4006E   (1U << 18)
+/// Macronix MX25L2006E SPI Flash
+#define BOOTLOADER_STORAGE_MACRONIX_MX25L2006E   (1U << 19)
+/// Winbond W25Q80BV SPI Flash
+#define BOOTLOADER_STORAGE_WINBOND_W25Q80BV      (1U << 20)
+/// Winbond W25X20BV SPI Flash
+#define BOOTLOADER_STORAGE_WINBOND_W25X20BV      (1U << 21)
+/// Spansion S25L208K SPI Flash
+#define BOOTLOADER_STORAGE_SPANSION_S25FL208K    (1U << 22)
+/// Internal storage
+#define BOOTLOADER_STORAGE_INTERNAL_STORAGE      (1U << 30)
+/// JEDEC Supported SPI Flash
+#define BOOTLOADER_STORAGE_JEDEC                 (1U << 31)
+
+// -----------------------------------------------------------------------------
+// Functions
+
+/***************************************************************************//**
+ * Get information about the storage component.
+ *
+ * @param[out] info Information about the storage component.
+ ******************************************************************************/
+void bootloader_getStorageInfo(BootloaderStorageInformation_t *info);
+
+/***************************************************************************//**
+ * Get information about a storage slot.
+ *
+ * @param[in]  slotId ID of the slot to get information about
+ * @param[out] slot Information about the storage slot
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_STORAGE_BASE range
+ ******************************************************************************/
+int32_t bootloader_getStorageSlotInfo(uint32_t                slotId,
+                                      BootloaderStorageSlot_t *slot);
+
+/***************************************************************************//**
+ * Read data from a storage slot.
+ *
+ * @param[in]  slotId  ID of the slot
+ * @param[in]  offset Offset into the slot to start reading from
+ * @param[out] buffer Buffer to store the data
+ * @param[in]  length Amount of data to read
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_STORAGE_BASE range
+ ******************************************************************************/
+int32_t bootloader_readStorage(uint32_t slotId,
+                               uint32_t offset,
+                               uint8_t  *buffer,
+                               size_t   length);
+
+/***************************************************************************//**
+ * Write data to a storage slot.
+ *
+ * @note
+ *   If DMA-based MSC write is enabled on the bootloader, writing data from
+ *   flash to flash is not supported on Series-1 devices. DMA-based MSC write is
+ *   enabled, both offset and buffer should be word aligned. In case the buffer
+ *   is not aligned, the normal write procedure is used instead of DMA.
+ *
+ * @param[in] slotId ID of the slot
+ * @param[in] offset Offset into the slot to start writing to
+ * @param[in] buffer Buffer to read data to write from
+ * @param[in] length Amount of data to write. Must be a multiple of 4.
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_STORAGE_BASE range
+ ******************************************************************************/
+int32_t bootloader_writeStorage(uint32_t slotId,
+                                uint32_t offset,
+                                uint8_t  *buffer,
+                                size_t   length);
+
+/***************************************************************************//**
+ * Erase and write data to a storage slot.
+ *
+ * @note This function automatically erases the following Flash page whenever
+ *       the written data crosses a page boundary. In other words, the function
+ *       can't be used to perform multiple sequential writes to the same
+ *       address range unless the range starts at a page boundary.
+ *       For a sequential write, the first call to this function should have
+ *       a start address at a page boundary. Otherwise, the corresponding page
+ *       of the starting address needs to be erased explicitly. If DMA-based
+ *       MSC write is enabled on the bootloader, writing data from flash to
+ *       flash is not supported on Series-1 devices.
+ *
+ * @param[in] slotId ID of the slot
+ * @param[in] offset Offset into the slot to start writing to
+ * @param[in] buffer Buffer to read data to write from
+ * @param[in] length Amount of data to write. Must be a multiple of 4.
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_STORAGE_BASE range
+ ******************************************************************************/
+int32_t bootloader_eraseWriteStorage(uint32_t slotId,
+                                     uint32_t offset,
+                                     uint8_t  *buffer,
+                                     size_t   length);
+
+/***************************************************************************//**
+ * Erase all contents of a storage slot.
+ *
+ * @param[in] slotId ID of the slot
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_STORAGE_BASE range
+ ******************************************************************************/
+int32_t bootloader_eraseStorageSlot(uint32_t slotId);
+
+/***************************************************************************//**
+ * Initialize chunked erase of a storage slot.
+ *
+ * @note This function must be called before calling
+ *       @ref bootloader_chunkedEraseStorageSlot in a loop.
+ *
+ * @param[in] slotId    ID of the slot
+ * @param[in] eraseStat Erase status struct
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_STORAGE_BASE range
+ ******************************************************************************/
+int32_t bootloader_initChunkedEraseStorageSlot(uint32_t                slotId,
+                                               BootloaderEraseStatus_t *eraseStat);
+
+/***************************************************************************//**
+ * Erase one page from a storage slot according to
+ * the struct BootloaderEraseStatus_t.
+ *
+ * @note @ref bootloader_initChunkedEraseStorageSlot must be called
+ *       before calling this function, in order to prepare
+ *       BootloaderEraseStatus_t.
+ *
+ * @note This can be called sequentially to, for example, erase all contents
+ *       of a storage slot.
+ *
+ * @param[in] eraseStat Erase status struct
+ *
+ * @return @ref BOOTLOADER_ERROR_STORAGE_CONTINUE if erasing a page was
+ *         successful. Erase can be continued by calling this function again.
+ *         @ref BOOTLOADER_OK if the entire slot has been erased,
+ *         else error code in @ref BOOTLOADER_ERROR_STORAGE_BASE range
+ ******************************************************************************/
+int32_t bootloader_chunkedEraseStorageSlot(BootloaderEraseStatus_t *eraseStat);
+
+/***************************************************************************//**
+ * Set a prioritized list of images to attempt to bootload. The last call to
+ * this function determines which slot will be installed when
+ * @ref bootloader_rebootAndInstall is called.
+ *
+ * @param[in] slotIds Prioritized list of slot IDs to attempt to bootload. The
+ *                    first image to pass verification will be bootloaded.
+ * @param[in] length  Length of the slotIds array
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_BOOTLOAD_BASE range
+ ******************************************************************************/
+int32_t bootloader_setImagesToBootload(int32_t *slotIds, size_t length);
+
+/***************************************************************************//**
+ * Get the prioritized list of images the bootloader will attempt to bootload.
+ *
+ * @param[out] slotIds Prioritized list of slot IDs to attempt to bootload. The
+ *                     first image to pass verification will be bootloaded.
+ * @param[in] length   Length of the slotIds array
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_BOOTLOAD_BASE range
+ ******************************************************************************/
+int32_t bootloader_getImagesToBootload(int32_t *slotIds, size_t length);
+
+/***************************************************************************//**
+ * Append a single image to the list of images to attempt to bootload.
+ *
+ * @param[in] slotId ID of the slot to append
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_BOOTLOAD_BASE range
+ ******************************************************************************/
+int32_t bootloader_appendImageToBootloadList(int32_t slotId);
+
+/***************************************************************************//**
+ * Set a single image to attempt to bootload.
+ *
+ * @param[in] slotId ID of the slot
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_BOOTLOAD_BASE range
+ ******************************************************************************/
+int32_t bootloader_setImageToBootload(int32_t slotId);
+
+/***************************************************************************//**
+ * Initialize image verification.
+ *
+ * Initialize verification of an upgrade image stored in a bootloader storage
+ * slot.
+ *
+ * @note This function must be called before calling
+ *       @ref bootloader_continueVerifyImage in a loop.
+ *
+ * @note The context pointer must point to memory allocated by the caller.
+ *       The caller must ensure that the context pointer is 32 bit aligned.
+ *       The required size of this context may depend on the version
+ *       of the bootloader. The required size for the bootloader associated with
+ *       this version of the application interface is given by the define
+ *       @ref BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE.
+ *
+ * @note Instead of calling @ref bootloader_initVerifyImage followed by
+ *       @ref bootloader_continueVerifyImage, call
+ *       @ref bootloader_verifyImage if no
+ *       time-critical tasks are needed and sufficient stack space is
+ *       available for the automatically allocated context. The purpose of the
+ *       init-and-continue functions is to allow the caller to service system
+ *       needs during verification.
+ *
+ *
+ * @param[in] slotId      ID of the slot to check.
+ * @param     context     Pointer to memory used to hold the parser context.
+ * @param[in] contextSize Size of the context. An error is returned if the
+ *                        supplied context is too small.
+ *
+ * @return @ref BOOTLOADER_OK if the image parser was initialized, else error
+ *         code.
+ ******************************************************************************/
+#if !defined(SL_TRUSTZONE_NONSECURE)
+int32_t bootloader_initVerifyImage(uint32_t slotId,
+                                   void     *context,
+                                   size_t   contextSize);
+#else
+int32_t bootloader_initVerifyImage(uint32_t slotId);
+#endif // SL_TRUSTZONE_NONSECURE
+
+/***************************************************************************//**
+ * Continue image verification.
+ *
+ * Continue verification of an upgrade image stored in a bootloader storage
+ * slot.
+ *
+ * @note This function must be called in a loop until anything other than
+ *       @ref BOOTLOADER_ERROR_PARSE_CONTINUE is returned.
+ *
+ * @note @ref bootloader_initVerifyImage must be called before calling this
+ *       function to reset the parser.
+ *
+ * @note Instead of calling @ref bootloader_initVerifyImage followed by
+ *       @ref bootloader_continueVerifyImage, call
+ *       @ref bootloader_verifyImage if no
+ *       time-critical tasks are needed. The purpose of the
+ *       init-and-continue functions is to allow the caller to service system
+ *       needs during verification.
+ *
+ *
+ * @param     context          Pointer to a context structure that has
+ *                             been initialized by calling
+ *                             @ref bootloader_initVerifyImage()
+ * @param[in] metadataCallback Function pointer, which is called when
+ *                             the binary metadata in the image is currently
+ *                             verified. Set to NULL if not required.
+ *
+ * @return @ref BOOTLOADER_ERROR_PARSE_CONTINUE if parsing was successful, and
+ *         the parser expects more data. @ref BOOTLOADER_ERROR_PARSE_SUCCESS if
+ *         the parser has successfully parsed the image and it passes
+ *         verification. Else error code.
+ ******************************************************************************/
+#if !defined(SL_TRUSTZONE_NONSECURE)
+int32_t bootloader_continueVerifyImage(void                       *context,
+                                       BootloaderParserCallback_t metadataCallback);
+#else
+int32_t bootloader_continueVerifyImage(void);
+#endif // SL_TRUSTZONE_NONSECURE
+
+/***************************************************************************//**
+ * Verify that the image in the given storage slot is valid.
+ *
+ * @param[in] slotId ID of the slot to check
+ * @param[in] metadataCallback Function pointer, which is called when
+ *                             binary metadata is present in the storage slot.
+ *                             Set to NULL if not required.
+ *
+ * @note This function allocates a context structure of the size given by
+ *       @ref BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE on the caller's
+ *       stack. To manage memory and allocate the
+ *       context elsewhere (on the heap, as a global variable, and so on), use
+ *       @ref bootloader_initVerifyImage and @ref bootloader_continueVerifyImage
+ *       functions instead.
+ *
+ * @return @ref BOOTLOADER_OK if the image is valid, else error code.
+ ******************************************************************************/
+#if !defined(SL_TRUSTZONE_NONSECURE)
+int32_t bootloader_verifyImage(uint32_t                   slotId,
+                               BootloaderParserCallback_t metadataCallback);
+#else
+int32_t bootloader_verifyImage(uint32_t slotId);
+#endif // SL_TRUSTZONE_NONSECURE
+
+/***************************************************************************//**
+ * Get application and bootloader upgrade metadata from the storage slot.
+ *
+ * @param[in]  slotId            ID of the slot to check
+ * @param[out] appInfo           Pointer to @ref ApplicationData_t struct
+ * @param[out] bootloaderVersion Pointer to an integer representing bootloader
+ *                               version
+ *
+ * @return @ref BOOTLOADER_OK if metadata was filled successfully
+ ******************************************************************************/
+int32_t bootloader_getImageInfo(uint32_t          slotId,
+                                ApplicationData_t *appInfo,
+                                uint32_t          *bootloaderVersion);
+
+/***************************************************************************//**
+ * Check whether the bootloader storage is busy.
+ *
+ * @return True if the storage is busy
+ ******************************************************************************/
+bool bootloader_storageIsBusy(void);
+
+#if !defined(SL_TRUSTZONE_NONSECURE)
+/***************************************************************************//**
+ * Read raw data from storage.
+ *
+ * @param[in]  address Address to start reading from
+ * @param[out] buffer  Buffer to store the data
+ * @param[in]  length  Amount of data to read
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_STORAGE_BASE range
+ ******************************************************************************/
+int32_t bootloader_readRawStorage(uint32_t address,
+                                  uint8_t  *buffer,
+                                  size_t   length);
+
+/***************************************************************************//**
+ * Write data to storage.
+ *
+ * @note
+ *   If DMA-based MSC write is enabled on the bootloader, writing data from
+ *   flash to flash is not supported on Series-1 devices.
+ *
+ * @param[in] address Address to start writing to
+ * @param[in] buffer  Buffer to read data to write from
+ * @param[in] length  Amount of data to write. Must be a multiple of 4.
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_STORAGE_BASE range
+ ******************************************************************************/
+int32_t bootloader_writeRawStorage(uint32_t address,
+                                   uint8_t  *buffer,
+                                   size_t   length);
+
+/***************************************************************************//**
+ * Erase data from storage.
+ *
+ * @note Erasing storage must adhere to the limitations of the underlying
+ *       storage medium, such as requiring full page erases. Use
+ *       @ref bootloader_getStorageInfo to learn about the limitations of the
+ *       configured storage medium.
+ *
+ * @param[in] address Address to start erasing from
+ * @param[in] length  Length of data to erase
+ *
+ * @return @ref BOOTLOADER_OK on success, else error code in
+ *         @ref BOOTLOADER_ERROR_STORAGE_BASE range
+ ******************************************************************************/
+int32_t bootloader_eraseRawStorage(uint32_t address, size_t length);
+#endif // !SL_TRUSTZONE_NONSECURE
+
+/***************************************************************************//**
+ * Get allocated DMA channel for MSC write.
+ *
+ * @return A positive number channel. -1 if DMA-based MSC write
+ *         is not enabled. Otherwise, the error code
+ *         BOOTLOADER_ERROR_INIT_STORAGE.
+ ******************************************************************************/
+int32_t bootloader_getAllocatedDMAChannel(void);
+
+/** @} (end addtogroup StorageInterface) */
+/** @} (end addtogroup Interface) */
+
+#endif // BTL_INTERFACE_STORAGE_H

Libs/platform/bootloader/api/btl_reset_info.h

@@ -0,0 +1,104 @@
+/***************************************************************************//**
+ * @file
+ * @brief Reset information for the Silicon Labs Gecko bootloader
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * The licensor of this software is Silicon Laboratories Inc.  Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement.  This
+ * software is distributed to you in Source Code format and is governed by the
+ * sections of the MSLA applicable to Source Code.
+ *
+ ******************************************************************************/
+#ifndef BTL_RESET_INFO_H
+#define BTL_RESET_INFO_H
+
+#include <stdint.h>
+
+/***************************************************************************//**
+ * @addtogroup Interface
+ * @{
+ * @addtogroup CommonInterface
+ * @{
+ * @addtogroup ResetInterface Reset Information
+ * @brief Passing information when resetting into and out of the bootloader
+ * @details
+ *   To signal the bootloader to run, the
+ *   application needs to write the @ref BootloaderResetCause_t structure
+ *   to the first address of RAM, setting @ref BootloaderResetCause_t.reason
+ *   to @ref BOOTLOADER_RESET_REASON_BOOTLOAD.
+ *
+ *   The reset cause is only valid if @ref BootloaderResetCause_t.signature
+ *   is set to @ref BOOTLOADER_RESET_SIGNATURE_VALID.
+ * @code BootloaderResetCause_t resetCause = {
+ *    .reason = BOOTLOADER_RESET_REASON_BOOTLOAD,
+ *    .signature = BOOTLOADER_RESET_SIGNATURE_VALID
+ *  } @endcode
+ *
+ *   When the bootloader reboots back into the app, it sets the reset
+ *   reason to @ref BOOTLOADER_RESET_REASON_GO if the bootload succeeded,
+ *   or @ref BOOTLOADER_RESET_REASON_BADIMAGE if the bootload failed due
+ *   to errors when parsing the upgrade image.
+ *
+ * @note
+ *   The reset information is automatically filled out before reset if the
+ *   @ref bootloader_rebootAndInstall function is called.
+ * @{
+ ******************************************************************************/
+
+/// Reset cause of the bootloader
+typedef struct {
+  /// Reset reason as defined in the [reset information](@ref ResetInterface)
+  uint16_t reason;
+  /// Signature indicating whether the reset reason is valid
+  uint16_t signature;
+} BootloaderResetCause_t;
+
+/// Unknown bootloader cause (should never occur)
+#define BOOTLOADER_RESET_REASON_UNKNOWN       0x0200u
+/// Bootloader caused reset telling app to run
+#define BOOTLOADER_RESET_REASON_GO            0x0201u
+/// Application requested that bootloader runs
+#define BOOTLOADER_RESET_REASON_BOOTLOAD      0x0202u
+/// Bootloader detected bad external upgrade image
+#define BOOTLOADER_RESET_REASON_BADIMAGE      0x0203u
+/// Fatal Error or assert in bootloader
+#define BOOTLOADER_RESET_REASON_FATAL         0x0204u
+/// Forced bootloader activation
+#define BOOTLOADER_RESET_REASON_FORCE         0x0205u
+/// OTA Bootloader mode activation
+#define BOOTLOADER_RESET_REASON_OTAVALID      0x0206u
+/// Bootloader initiated deep sleep
+#define BOOTLOADER_RESET_REASON_DEEPSLEEP     0x0207u
+/// Application verification failed
+#define BOOTLOADER_RESET_REASON_BADAPP        0x0208u
+/// Bootloader requested that first stage upgrades main bootloader
+#define BOOTLOADER_RESET_REASON_UPGRADE       0x0209u
+/// Bootloader timed out waiting for upgrade image
+#define BOOTLOADER_RESET_REASON_TIMEOUT       0x020Au
+/// Soft-reset was forced to handle a fault
+#define BOOTLOADER_RESET_REASON_FAULT         0x020Bu
+/// Soft-reset was forced to handle a security fault
+#define BOOTLOADER_RESET_REASON_TZ_FAULT      0x020Cu
+
+/// Insufficient slot space to re-create a new firmware
+#define BOOTLOADER_RESET_REASON_NO_SLOT_SPACE 0x020Du
+/// CRC mismatch of the newly re-constructed firmware
+#define BOOTLOADER_RESET_REASON_BADCRC        0x020Eu
+/// Re-creation of the new application using the DDFU library failed
+#define BOOTLOADER_RESET_REASON_DDFU_FAIL     0x020Fu
+
+/// Reset signature is valid
+#define BOOTLOADER_RESET_SIGNATURE_VALID      0xF00Fu
+/// Reset signature is invalid
+#define BOOTLOADER_RESET_SIGNATURE_INVALID    0xC33Cu
+
+/** @} (end addtogroup ResetInterface) */
+/** @} (end addtogroup CommonInterface) */
+/** @} (end addtogroup Interface) */
+
+#endif // BTL_RESET_INFO_H

Libs/platform/bootloader/app_properties/app_properties.c

@@ -0,0 +1,49 @@
+/***************************************************************************//**
+ * @file
+ * @brief Application Properties Source File
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifdef APP_PROPERTIES_CONFIG_FILE
+#include APP_PROPERTIES_CONFIG_FILE
+#else
+#include "app_properties_config.h"
+#endif
+
+const ApplicationProperties_t sl_app_properties = {
+  .magic = APPLICATION_PROPERTIES_MAGIC,
+  .structVersion = APPLICATION_PROPERTIES_VERSION,
+  .signatureType = SL_APPLICATION_SIGNATURE,
+  .signatureLocation = SL_APPLICATION_SIGNATURE_LOCATION,
+  .app = {
+    .type = SL_APPLICATION_TYPE,
+    .version = SL_APPLICATION_VERSION,
+    .capabilities = SL_APPLICATION_CAPABILITIES,
+    .productId = SL_APPLICATION_PRODUCT_ID
+  },
+  .cert = 0,
+  .longTokenSectionAddress = 0
+};

Libs/platform/bootloader/core/btl_util.h

@@ -0,0 +1,210 @@
+#ifndef BTL_UTIL_H
+#define BTL_UTIL_H
+
+#define BTL_STR_HELPER(x) #x
+#define QUOTE(x) BTL_STR_HELPER(x)
+
+#if defined(__CSTAT__)
+#define MISRAC_DISABLE _Pragma( \
+    "cstat_disable=                                                                     \
+    \"MISRAC2012-Dir-4.3\",\"MISRAC2012-Dir-4.4\",\"MISRAC2012-Dir-4.5\",               \
+    \"MISRAC2012-Dir-4.6_a\",\"MISRAC2012-Dir-4.6_b\",\"MISRAC2012-Dir-4.7_a\",         \
+    \"MISRAC2012-Dir-4.7_b\",\"MISRAC2012-Dir-4.7_c\",\"MISRAC2012-Dir-4.8\",           \
+    \"MISRAC2012-Dir-4.9\",\"MISRAC2012-Dir-4.10\",\"MISRAC2012-Dir-4.11_a\",           \
+    \"MISRAC2012-Dir-4.11_b\",\"MISRAC2012-Dir-4.11_c\",\"MISRAC2012-Dir-4.11_d\",      \
+    \"MISRAC2012-Dir-4.11_e\",\"MISRAC2012-Dir-4.11_f\",\"MISRAC2012-Dir-4.11_g\",      \
+    \"MISRAC2012-Dir-4.11_h\",\"MISRAC2012-Dir-4.11_i\",\"MISRAC2012-Dir-4.12\",        \
+    \"MISRAC2012-Dir-4.13_b\",\"MISRAC2012-Dir-4.13_c\",\"MISRAC2012-Dir-4.13_d\",      \
+    \"MISRAC2012-Dir-4.13_e\",\"MISRAC2012-Dir-4.13_f\",\"MISRAC2012-Dir-4.13_g\",      \
+    \"MISRAC2012-Dir-4.13_h\",\"MISRAC2012-Rule-1.3_a\",\"MISRAC2012-Rule-1.3_b\",      \
+    \"MISRAC2012-Rule-1.3_c\",\"MISRAC2012-Rule-1.3_d\",\"MISRAC2012-Rule-1.3_e\",      \
+    \"MISRAC2012-Rule-1.3_f\",\"MISRAC2012-Rule-1.3_g\",\"MISRAC2012-Rule-1.3_h\",      \
+    \"MISRAC2012-Rule-1.3_i\",\"MISRAC2012-Rule-1.3_j\",\"MISRAC2012-Rule-1.3_k\",      \
+    \"MISRAC2012-Rule-1.3_m\",\"MISRAC2012-Rule-1.3_n\",\"MISRAC2012-Rule-1.3_o\",      \
+    \"MISRAC2012-Rule-1.3_p\",\"MISRAC2012-Rule-1.3_q\",\"MISRAC2012-Rule-1.3_r\",      \
+    \"MISRAC2012-Rule-1.3_s\",\"MISRAC2012-Rule-1.3_t\",\"MISRAC2012-Rule-1.3_u\",      \
+    \"MISRAC2012-Rule-1.3_v\",\"MISRAC2012-Rule-1.3_w\",\"MISRAC2012-Rule-2.1_a\",      \
+    \"MISRAC2012-Rule-2.1_b\",\"MISRAC2012-Rule-2.2_a\",\"MISRAC2012-Rule-2.2_b\",      \
+    \"MISRAC2012-Rule-2.2_c\",\"MISRAC2012-Rule-2.3\",\"MISRAC2012-Rule-2.4\",          \
+    \"MISRAC2012-Rule-2.5\",\"MISRAC2012-Rule-2.6\",\"MISRAC2012-Rule-2.7\",            \
+    \"MISRAC2012-Rule-3.1\",\"MISRAC2012-Rule-3.2\",\"MISRAC2012-Rule-5.1\",            \
+    \"MISRAC2012-Rule-5.2_c89\",\"MISRAC2012-Rule-5.2_c99\",                            \
+    \"MISRAC2012-Rule-5.3_c89\",\"MISRAC2012-Rule-5.3_c99\",                            \
+    \"MISRAC2012-Rule-5.4_c89\",\"MISRAC2012-Rule-5.4_c99\",                            \
+    \"MISRAC2012-Rule-5.5_c89\",\"MISRAC2012-Rule-5.5_c99\",                            \
+    \"MISRAC2012-Rule-5.6\",\"MISRAC2012-Rule-5.7\",\"MISRAC2012-Rule-5.8\",            \
+    \"MISRAC2012-Rule-5.9\",\"MISRAC2012-Rule-6.1\",\"MISRAC2012-Rule-6.2\",            \
+    \"MISRAC2012-Rule-7.1\",\"MISRAC2012-Rule-7.2\",\"MISRAC2012-Rule-7.3\",            \
+    \"MISRAC2012-Rule-7.4_a\",\"MISRAC2012-Rule-7.4_b\",\"MISRAC2012-Rule-8.1\",        \
+    \"MISRAC2012-Rule-8.2_a\",\"MISRAC2012-Rule-8.2_b\",\"MISRAC2012-Rule-8.3_b\",      \
+    \"MISRAC2012-Rule-8.4\",\"MISRAC2012-Rule-8.5_a\",\"MISRAC2012-Rule-8.5_b\",        \
+    \"MISRAC2012-Rule-8.6\",\"MISRAC2012-Rule-8.7\",\"MISRAC2012-Rule-8.9_a\",          \
+    \"MISRAC2012-Rule-8.9_b\",\"MISRAC2012-Rule-8.10\",\"MISRAC2012-Rule-8.11\",        \
+    \"MISRAC2012-Rule-8.12\",\"MISRAC2012-Rule-8.13\",\"MISRAC2012-Rule-8.14\",         \
+    \"MISRAC2012-Rule-9.1_a\",\"MISRAC2012-Rule-9.1_b\",\"MISRAC2012-Rule-9.1_c\",      \
+    \"MISRAC2012-Rule-9.1_d\",\"MISRAC2012-Rule-9.1_e\",\"MISRAC2012-Rule-9.1_f\",      \
+    \"MISRAC2012-Rule-9.2\",\"MISRAC2012-Rule-9.3\",\"MISRAC2012-Rule-9.4\",            \
+    \"MISRAC2012-Rule-9.5_a\",\"MISRAC2012-Rule-9.5_b\",\"MISRAC2012-Rule-10.1_R2\",    \
+    \"MISRAC2012-Rule-10.1_R3\",\"MISRAC2012-Rule-10.1_R4\",                            \
+    \"MISRAC2012-Rule-10.1_R5\",\"MISRAC2012-Rule-10.1_R6\",                            \
+    \"MISRAC2012-Rule-10.1_R7\",\"MISRAC2012-Rule-10.1_R8\",                            \
+    \"MISRAC2012-Rule-10.2\",\"MISRAC2012-Rule-10.3\",\"MISRAC2012-Rule-10.4_a\",       \
+    \"MISRAC2012-Rule-10.4_b\",\"MISRAC2012-Rule-10.5\",\"MISRAC2012-Rule-10.6\",       \
+    \"MISRAC2012-Rule-10.7\",\"MISRAC2012-Rule-10.8\",\"MISRAC2012-Rule-11.1\",         \
+    \"MISRAC2012-Rule-11.2\",\"MISRAC2012-Rule-11.3\",\"MISRAC2012-Rule-11.4\",         \
+    \"MISRAC2012-Rule-11.5\",\"MISRAC2012-Rule-11.6\",\"MISRAC2012-Rule-11.7\",         \
+    \"MISRAC2012-Rule-11.8\",\"MISRAC2012-Rule-11.9\",\"MISRAC2012-Rule-12.1\",         \
+    \"MISRAC2012-Rule-12.2\",\"MISRAC2012-Rule-12.3\",\"MISRAC2012-Rule-13.1\",         \
+    \"MISRAC2012-Rule-13.2_a\",\"MISRAC2012-Rule-13.2_b\",\"MISRAC2012-Rule-13.2_c\",   \
+    \"MISRAC2012-Rule-13.3\",\"MISRAC2012-Rule-13.4_a\",\"MISRAC2012-Rule-13.4_b\",     \
+    \"MISRAC2012-Rule-13.5\",\"MISRAC2012-Rule-13.6\",\"MISRAC2012-Rule-14.1_a\",       \
+    \"MISRAC2012-Rule-14.1_b\",\"MISRAC2012-Rule-14.2\",\"MISRAC2012-Rule-14.3_a\",     \
+    \"MISRAC2012-Rule-14.3_b\",\"MISRAC2012-Rule-14.4_a\",\"MISRAC2012-Rule-14.4_b\",   \
+    \"MISRAC2012-Rule-14.4_c\",\"MISRAC2012-Rule-14.4_d\",\"MISRAC2012-Rule-15.1\",     \
+    \"MISRAC2012-Rule-15.2\",\"MISRAC2012-Rule-15.3\",\"MISRAC2012-Rule-15.4\",         \
+    \"MISRAC2012-Rule-15.5\",\"MISRAC2012-Rule-15.6_a\",\"MISRAC2012-Rule-15.6_b\",     \
+    \"MISRAC2012-Rule-15.6_c\",\"MISRAC2012-Rule-15.6_d\",\"MISRAC2012-Rule-15.6_e\",   \
+    \"MISRAC2012-Rule-15.7\",\"MISRAC2012-Rule-16.1\",\"MISRAC2012-Rule-16.2\",         \
+    \"MISRAC2012-Rule-16.3\",\"MISRAC2012-Rule-16.4\",\"MISRAC2012-Rule-16.5\",         \
+    \"MISRAC2012-Rule-16.6\",\"MISRAC2012-Rule-16.7\",\"MISRAC2012-Rule-17.1\",         \
+    \"MISRAC2012-Rule-17.2_a\",\"MISRAC2012-Rule-17.2_b\",\"MISRAC2012-Rule-17.3\",     \
+    \"MISRAC2012-Rule-17.4\",\"MISRAC2012-Rule-17.5\",\"MISRAC2012-Rule-17.6\",         \
+    \"MISRAC2012-Rule-17.7\",\"MISRAC2012-Rule-17.8\",\"MISRAC2012-Rule-18.1_a\",       \
+    \"MISRAC2012-Rule-18.1_b\",\"MISRAC2012-Rule-18.1_c\",\"MISRAC2012-Rule-18.1_d\",   \
+    \"MISRAC2012-Rule-18.2\",\"MISRAC2012-Rule-18.3\",\"MISRAC2012-Rule-18.4\",         \
+    \"MISRAC2012-Rule-18.5\",\"MISRAC2012-Rule-18.6_a\",\"MISRAC2012-Rule-18.6_b\",     \
+    \"MISRAC2012-Rule-18.6_c\",\"MISRAC2012-Rule-18.6_d\",\"MISRAC2012-Rule-18.7\",     \
+    \"MISRAC2012-Rule-18.8\",\"MISRAC2012-Rule-19.1\",\"MISRAC2012-Rule-19.2\",         \
+    \"MISRAC2012-Rule-20.1\",\"MISRAC2012-Rule-20.2\",\"MISRAC2012-Rule-20.4_c89\",     \
+    \"MISRAC2012-Rule-20.4_c99\",\"MISRAC2012-Rule-20.5\",\"MISRAC2012-Rule-20.7\",     \
+    \"MISRAC2012-Rule-20.10\",\"MISRAC2012-Rule-21.1\",\"MISRAC2012-Rule-21.2\",        \
+    \"MISRAC2012-Rule-21.3\",\"MISRAC2012-Rule-21.4\",\"MISRAC2012-Rule-21.5\",         \
+    \"MISRAC2012-Rule-21.6\",\"MISRAC2012-Rule-21.7\",\"MISRAC2012-Rule-21.8\",         \
+    \"MISRAC2012-Rule-21.9\",\"MISRAC2012-Rule-21.10\",\"MISRAC2012-Rule-21.11\",       \
+    \"MISRAC2012-Rule-21.12_a\",\"MISRAC2012-Rule-21.12_b\",\"MISRAC2012-Rule-22.1_a\", \
+    \"MISRAC2012-Rule-22.1_b\",\"MISRAC2012-Rule-22.2_a\",\"MISRAC2012-Rule-22.2_b\",   \
+    \"MISRAC2012-Rule-22.2_c\",\"MISRAC2012-Rule-22.3\",\"MISRAC2012-Rule-22.4\",       \
+    \"MISRAC2012-Rule-22.5_a\",\"MISRAC2012-Rule-22.5_b\",\"MISRAC2012-Rule-22.6\"")
+
+#define MISRAC_ENABLE  _Pragma( \
+    "cstat_restore=                                                                     \
+    \"MISRAC2012-Dir-4.3\",\"MISRAC2012-Dir-4.4\",\"MISRAC2012-Dir-4.5\",               \
+    \"MISRAC2012-Dir-4.6_a\",\"MISRAC2012-Dir-4.6_b\",\"MISRAC2012-Dir-4.7_a\",         \
+    \"MISRAC2012-Dir-4.7_b\",\"MISRAC2012-Dir-4.7_c\",\"MISRAC2012-Dir-4.8\",           \
+    \"MISRAC2012-Dir-4.9\",\"MISRAC2012-Dir-4.10\",\"MISRAC2012-Dir-4.11_a\",           \
+    \"MISRAC2012-Dir-4.11_b\",\"MISRAC2012-Dir-4.11_c\",\"MISRAC2012-Dir-4.11_d\",      \
+    \"MISRAC2012-Dir-4.11_e\",\"MISRAC2012-Dir-4.11_f\",\"MISRAC2012-Dir-4.11_g\",      \
+    \"MISRAC2012-Dir-4.11_h\",\"MISRAC2012-Dir-4.11_i\",\"MISRAC2012-Dir-4.12\",        \
+    \"MISRAC2012-Dir-4.13_b\",\"MISRAC2012-Dir-4.13_c\",\"MISRAC2012-Dir-4.13_d\",      \
+    \"MISRAC2012-Dir-4.13_e\",\"MISRAC2012-Dir-4.13_f\",\"MISRAC2012-Dir-4.13_g\",      \
+    \"MISRAC2012-Dir-4.13_h\",\"MISRAC2012-Rule-1.3_a\",\"MISRAC2012-Rule-1.3_b\",      \
+    \"MISRAC2012-Rule-1.3_c\",\"MISRAC2012-Rule-1.3_d\",\"MISRAC2012-Rule-1.3_e\",      \
+    \"MISRAC2012-Rule-1.3_f\",\"MISRAC2012-Rule-1.3_g\",\"MISRAC2012-Rule-1.3_h\",      \
+    \"MISRAC2012-Rule-1.3_i\",\"MISRAC2012-Rule-1.3_j\",\"MISRAC2012-Rule-1.3_k\",      \
+    \"MISRAC2012-Rule-1.3_m\",\"MISRAC2012-Rule-1.3_n\",\"MISRAC2012-Rule-1.3_o\",      \
+    \"MISRAC2012-Rule-1.3_p\",\"MISRAC2012-Rule-1.3_q\",\"MISRAC2012-Rule-1.3_r\",      \
+    \"MISRAC2012-Rule-1.3_s\",\"MISRAC2012-Rule-1.3_t\",\"MISRAC2012-Rule-1.3_u\",      \
+    \"MISRAC2012-Rule-1.3_v\",\"MISRAC2012-Rule-1.3_w\",\"MISRAC2012-Rule-2.1_a\",      \
+    \"MISRAC2012-Rule-2.1_b\",\"MISRAC2012-Rule-2.2_a\",\"MISRAC2012-Rule-2.2_b\",      \
+    \"MISRAC2012-Rule-2.2_c\",\"MISRAC2012-Rule-2.3\",\"MISRAC2012-Rule-2.4\",          \
+    \"MISRAC2012-Rule-2.5\",\"MISRAC2012-Rule-2.6\",\"MISRAC2012-Rule-2.7\",            \
+    \"MISRAC2012-Rule-3.1\",\"MISRAC2012-Rule-3.2\",\"MISRAC2012-Rule-5.1\",            \
+    \"MISRAC2012-Rule-5.2_c89\",\"MISRAC2012-Rule-5.2_c99\",                            \
+    \"MISRAC2012-Rule-5.3_c89\",\"MISRAC2012-Rule-5.3_c99\",                            \
+    \"MISRAC2012-Rule-5.4_c89\",\"MISRAC2012-Rule-5.4_c99\",                            \
+    \"MISRAC2012-Rule-5.5_c89\",\"MISRAC2012-Rule-5.5_c99\",                            \
+    \"MISRAC2012-Rule-5.6\",\"MISRAC2012-Rule-5.7\",\"MISRAC2012-Rule-5.8\",            \
+    \"MISRAC2012-Rule-5.9\",\"MISRAC2012-Rule-6.1\",\"MISRAC2012-Rule-6.2\",            \
+    \"MISRAC2012-Rule-7.1\",\"MISRAC2012-Rule-7.2\",\"MISRAC2012-Rule-7.3\",            \
+    \"MISRAC2012-Rule-7.4_a\",\"MISRAC2012-Rule-7.4_b\",\"MISRAC2012-Rule-8.1\",        \
+    \"MISRAC2012-Rule-8.2_a\",\"MISRAC2012-Rule-8.2_b\",\"MISRAC2012-Rule-8.3_b\",      \
+    \"MISRAC2012-Rule-8.4\",\"MISRAC2012-Rule-8.5_a\",\"MISRAC2012-Rule-8.5_b\",        \
+    \"MISRAC2012-Rule-8.6\",\"MISRAC2012-Rule-8.7\",\"MISRAC2012-Rule-8.9_a\",          \
+    \"MISRAC2012-Rule-8.9_b\",\"MISRAC2012-Rule-8.10\",\"MISRAC2012-Rule-8.11\",        \
+    \"MISRAC2012-Rule-8.12\",\"MISRAC2012-Rule-8.13\",\"MISRAC2012-Rule-8.14\",         \
+    \"MISRAC2012-Rule-9.1_a\",\"MISRAC2012-Rule-9.1_b\",\"MISRAC2012-Rule-9.1_c\",      \
+    \"MISRAC2012-Rule-9.1_d\",\"MISRAC2012-Rule-9.1_e\",\"MISRAC2012-Rule-9.1_f\",      \
+    \"MISRAC2012-Rule-9.2\",\"MISRAC2012-Rule-9.3\",\"MISRAC2012-Rule-9.4\",            \
+    \"MISRAC2012-Rule-9.5_a\",\"MISRAC2012-Rule-9.5_b\",\"MISRAC2012-Rule-10.1_R2\",    \
+    \"MISRAC2012-Rule-10.1_R3\",\"MISRAC2012-Rule-10.1_R4\",                            \
+    \"MISRAC2012-Rule-10.1_R5\",\"MISRAC2012-Rule-10.1_R6\",                            \
+    \"MISRAC2012-Rule-10.1_R7\",\"MISRAC2012-Rule-10.1_R8\",                            \
+    \"MISRAC2012-Rule-10.2\",\"MISRAC2012-Rule-10.3\",\"MISRAC2012-Rule-10.4_a\",       \
+    \"MISRAC2012-Rule-10.4_b\",\"MISRAC2012-Rule-10.5\",\"MISRAC2012-Rule-10.6\",       \
+    \"MISRAC2012-Rule-10.7\",\"MISRAC2012-Rule-10.8\",\"MISRAC2012-Rule-11.1\",         \
+    \"MISRAC2012-Rule-11.2\",\"MISRAC2012-Rule-11.3\",\"MISRAC2012-Rule-11.4\",         \
+    \"MISRAC2012-Rule-11.5\",\"MISRAC2012-Rule-11.6\",\"MISRAC2012-Rule-11.7\",         \
+    \"MISRAC2012-Rule-11.8\",\"MISRAC2012-Rule-11.9\",\"MISRAC2012-Rule-12.1\",         \
+    \"MISRAC2012-Rule-12.2\",\"MISRAC2012-Rule-12.3\",\"MISRAC2012-Rule-13.1\",         \
+    \"MISRAC2012-Rule-13.2_a\",\"MISRAC2012-Rule-13.2_b\",\"MISRAC2012-Rule-13.2_c\",   \
+    \"MISRAC2012-Rule-13.3\",\"MISRAC2012-Rule-13.4_a\",\"MISRAC2012-Rule-13.4_b\",     \
+    \"MISRAC2012-Rule-13.5\",\"MISRAC2012-Rule-13.6\",\"MISRAC2012-Rule-14.1_a\",       \
+    \"MISRAC2012-Rule-14.1_b\",\"MISRAC2012-Rule-14.2\",\"MISRAC2012-Rule-14.3_a\",     \
+    \"MISRAC2012-Rule-14.3_b\",\"MISRAC2012-Rule-14.4_a\",\"MISRAC2012-Rule-14.4_b\",   \
+    \"MISRAC2012-Rule-14.4_c\",\"MISRAC2012-Rule-14.4_d\",\"MISRAC2012-Rule-15.1\",     \
+    \"MISRAC2012-Rule-15.2\",\"MISRAC2012-Rule-15.3\",\"MISRAC2012-Rule-15.4\",         \
+    \"MISRAC2012-Rule-15.5\",\"MISRAC2012-Rule-15.6_a\",\"MISRAC2012-Rule-15.6_b\",     \
+    \"MISRAC2012-Rule-15.6_c\",\"MISRAC2012-Rule-15.6_d\",\"MISRAC2012-Rule-15.6_e\",   \
+    \"MISRAC2012-Rule-15.7\",\"MISRAC2012-Rule-16.1\",\"MISRAC2012-Rule-16.2\",         \
+    \"MISRAC2012-Rule-16.3\",\"MISRAC2012-Rule-16.4\",\"MISRAC2012-Rule-16.5\",         \
+    \"MISRAC2012-Rule-16.6\",\"MISRAC2012-Rule-16.7\",\"MISRAC2012-Rule-17.1\",         \
+    \"MISRAC2012-Rule-17.2_a\",\"MISRAC2012-Rule-17.2_b\",\"MISRAC2012-Rule-17.3\",     \
+    \"MISRAC2012-Rule-17.4\",\"MISRAC2012-Rule-17.5\",\"MISRAC2012-Rule-17.6\",         \
+    \"MISRAC2012-Rule-17.7\",\"MISRAC2012-Rule-17.8\",\"MISRAC2012-Rule-18.1_a\",       \
+    \"MISRAC2012-Rule-18.1_b\",\"MISRAC2012-Rule-18.1_c\",\"MISRAC2012-Rule-18.1_d\",   \
+    \"MISRAC2012-Rule-18.2\",\"MISRAC2012-Rule-18.3\",\"MISRAC2012-Rule-18.4\",         \
+    \"MISRAC2012-Rule-18.5\",\"MISRAC2012-Rule-18.6_a\",\"MISRAC2012-Rule-18.6_b\",     \
+    \"MISRAC2012-Rule-18.6_c\",\"MISRAC2012-Rule-18.6_d\",\"MISRAC2012-Rule-18.7\",     \
+    \"MISRAC2012-Rule-18.8\",\"MISRAC2012-Rule-19.1\",\"MISRAC2012-Rule-19.2\",         \
+    \"MISRAC2012-Rule-20.1\",\"MISRAC2012-Rule-20.2\",\"MISRAC2012-Rule-20.4_c89\",     \
+    \"MISRAC2012-Rule-20.4_c99\",\"MISRAC2012-Rule-20.5\",\"MISRAC2012-Rule-20.7\",     \
+    \"MISRAC2012-Rule-20.10\",\"MISRAC2012-Rule-21.1\",\"MISRAC2012-Rule-21.2\",        \
+    \"MISRAC2012-Rule-21.3\",\"MISRAC2012-Rule-21.4\",\"MISRAC2012-Rule-21.5\",         \
+    \"MISRAC2012-Rule-21.6\",\"MISRAC2012-Rule-21.7\",\"MISRAC2012-Rule-21.8\",         \
+    \"MISRAC2012-Rule-21.9\",\"MISRAC2012-Rule-21.10\",\"MISRAC2012-Rule-21.11\",       \
+    \"MISRAC2012-Rule-21.12_a\",\"MISRAC2012-Rule-21.12_b\",\"MISRAC2012-Rule-22.1_a\", \
+    \"MISRAC2012-Rule-22.1_b\",\"MISRAC2012-Rule-22.2_a\",\"MISRAC2012-Rule-22.2_b\",   \
+    \"MISRAC2012-Rule-22.2_c\",\"MISRAC2012-Rule-22.3\",\"MISRAC2012-Rule-22.4\",       \
+    \"MISRAC2012-Rule-22.5_a\",\"MISRAC2012-Rule-22.5_b\",\"MISRAC2012-Rule-22.6\"")
+
+#elif defined(__ICCARM__)
+#define MISRAC_DISABLE _Pragma( \
+    "diag_suppress= \
+    Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
+    Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
+    Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
+    Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
+    Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
+    Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
+    Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
+    Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
+    Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
+    Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
+    Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
+    Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
+    Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
+    Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
+    Pm155")
+#define MISRAC_ENABLE  _Pragma( \
+    "diag_default= \
+    Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
+    Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
+    Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
+    Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
+    Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
+    Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
+    Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
+    Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
+    Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
+    Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
+    Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
+    Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
+    Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
+    Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
+    Pm155")
+#else
+#define MISRAC_DISABLE
+#define MISRAC_ENABLE
+#endif
+
+#endif

Libs/platform/bootloader/core/flash/btl_internal_flash.c

@@ -0,0 +1,233 @@
+/***************************************************************************//**
+ * @file
+ * @brief Abstraction of internal flash read and write routines.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * The licensor of this software is Silicon Laboratories Inc.  Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement.  This
+ * software is distributed to you in Source Code format and is governed by the
+ * sections of the MSLA applicable to Source Code.
+ *
+ ******************************************************************************/
+#include "core/flash/btl_internal_flash.h"
+
+#include "core/btl_util.h"
+
+MISRAC_DISABLE
+#include "em_cmu.h"
+#include "em_msc.h"
+MISRAC_ENABLE
+
+#if !defined(_SILICON_LABS_32B_SERIES_2)
+static MSC_Status_TypeDef writeHalfword(uint32_t address,
+                                        uint16_t data);
+
+static MSC_Status_TypeDef writeHalfwordDMA(uint32_t address,
+                                           uint16_t data,
+                                           int      ch);
+
+static MSC_Status_TypeDef writeHalfword(uint32_t address,
+                                        uint16_t data)
+{
+  uint32_t address32, data32;
+  MSC_Status_TypeDef retval;
+
+  address32 = address & ~3UL;
+  if (address & 2UL) {
+    data32 = 0x0000FFFFUL | ((uint32_t)data << 16UL);
+  } else {
+    data32 = 0xFFFF0000UL | (uint32_t)data;
+  }
+
+  retval = MSC_WriteWord((uint32_t *)address32, &data32, 4U);
+
+  return retval;
+}
+
+static MSC_Status_TypeDef writeHalfwordDMA(uint32_t address,
+                                           uint16_t data,
+                                           int      ch)
+{
+  uint32_t address32, data32;
+  MSC_Status_TypeDef retval;
+
+  address32 = address & ~3UL;
+  if (address & 2UL) {
+    data32 = 0x0000FFFFUL | ((uint32_t)data << 16UL);
+  } else {
+    data32 = 0xFFFF0000UL | (uint32_t)data;
+  }
+
+  // ch is verified by flash_writeBuffer_dma, which calls this function.
+  retval = MSC_WriteWordDma(ch, (uint32_t *)address32, &data32, 4U);
+
+  return retval;
+}
+#endif // !defined(_SILICON_LABS_32B_SERIES_2)
+
+bool flash_erasePage(uint32_t address)
+{
+#if defined(_CMU_CLKEN1_MASK)
+  CMU->CLKEN1_SET = CMU_CLKEN1_MSC;
+#endif
+  MSC_Status_TypeDef retval = MSC_ErasePage((uint32_t *)address);
+  if (retval == mscReturnOk) {
+    return true;
+  } else {
+    return false;
+  }
+}
+
+bool flash_writeBuffer_dma(uint32_t       address,
+                           const void           *data,
+                           size_t         length,
+                           int            ch)
+{
+  MSC_Status_TypeDef retval = mscReturnOk;
+
+  if ((ch < 0) || (ch >= (int)DMA_CHAN_COUNT)) {
+    return false;
+  }
+  MISRAC_DISABLE
+  CMU_ClockEnable(cmuClock_LDMA, true);
+#if defined(CMU_CLKEN0_LDMAXBAR)
+  CMU_ClockEnable(cmuClock_LDMAXBAR, true);
+#endif
+  MISRAC_ENABLE
+
+  if (length == 0UL) {
+    // Attempt to write zero-length array, return immediately
+    return true;
+  }
+
+#if defined(_SILICON_LABS_32B_SERIES_2)
+  if ((address & 3UL) || (length & 3UL)) {
+    // Unaligned write, return early
+    return false;
+  }
+
+#if defined(_CMU_CLKEN1_MASK)
+  CMU->CLKEN1_SET = CMU_CLKEN1_MSC;
+#endif
+
+  retval = MSC_WriteWordDma(ch, (uint32_t *)address, data, length);
+#else
+  uint16_t * data16 = (uint16_t *)data;
+
+  if ((address & 1UL) || (length & 1UL)) {
+    // Unaligned write, return early
+    return false;
+  }
+
+  // Flash unaligned data at start
+  if (address & 2UL) {
+    if ((writeHalfwordDMA(address, *data16, ch)) != mscReturnOk) {
+      return false;
+    }
+    address += 2UL;
+    length -= 2UL;
+    data16++;
+  }
+
+  // Flash word-aligned data
+  if (length >= 4UL) {
+    uint32_t length16 = (length & ~3UL);
+
+    retval = MSC_WriteWordDma(ch, (uint32_t *)address, data16, length16);
+
+    data16 += length16 / sizeof(uint16_t);
+    address += length16;
+    length -= length16;
+  }
+
+  if (retval != mscReturnOk) {
+    return false;
+  }
+
+  // Flash unaligned data at end
+  if (length > 0UL) {
+    retval = writeHalfwordDMA(address, *data16, ch);
+    address += 2UL;
+    length -= 2UL;
+  }
+#endif // #if defined(_SILICON_LABS_32B_SERIES_2)
+
+  if (retval == mscReturnOk) {
+    return true;
+  } else {
+    return false;
+  }
+}
+
+bool flash_writeBuffer(uint32_t       address,
+                       const void           *data,
+                       size_t         length)
+{
+  MSC_Status_TypeDef retval = mscReturnOk;
+
+  if (length == 0UL) {
+    // Attempt to write zero-length array, return immediately
+    return true;
+  }
+
+#if defined(_SILICON_LABS_32B_SERIES_2)
+  if ((address & 3UL) || (length & 3UL)) {
+    // Unaligned write, return early
+    return false;
+  }
+
+#if defined(_CMU_CLKEN1_MASK)
+  CMU->CLKEN1_SET = CMU_CLKEN1_MSC;
+#endif
+
+  retval = MSC_WriteWord((uint32_t *)address, data, length);
+#else
+  uint16_t * data16 = (uint16_t *)data;
+
+  if ((address & 1UL) || (length & 1UL)) {
+    // Unaligned write, return early
+    return false;
+  }
+
+  // Flash unaligned data at start
+  if (address & 2UL) {
+    if ((writeHalfword(address, *data16)) != mscReturnOk) {
+      return false;
+    }
+    address += 2UL;
+    length -= 2UL;
+    data16++;
+  }
+
+  // Flash word-aligned data
+  if (length >= 4UL) {
+    uint32_t length16 = (length & ~3UL);
+    retval = MSC_WriteWord((uint32_t *)address, data16, length16);
+    data16 += length16 / sizeof(uint16_t);
+    address += length16;
+    length -= length16;
+  }
+
+  if (retval != mscReturnOk) {
+    return false;
+  }
+
+  // Flash unaligned data at end
+  if (length > 0UL) {
+    retval = writeHalfword(address, *data16);
+    address += 2UL;
+    length -= 2UL;
+  }
+#endif // #if defined(_SILICON_LABS_32B_SERIES_2)
+
+  if (retval == mscReturnOk) {
+    return true;
+  } else {
+    return false;
+  }
+}

Libs/platform/bootloader/core/flash/btl_internal_flash.h

@@ -0,0 +1,84 @@
+/***************************************************************************//**
+ * @file
+ * @brief Abstraction of internal flash read and write routines.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * The licensor of this software is Silicon Laboratories Inc.  Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement.  This
+ * software is distributed to you in Source Code format and is governed by the
+ * sections of the MSLA applicable to Source Code.
+ *
+ ******************************************************************************/
+#ifndef BTL_INTERNAL_FLASH_H
+#define BTL_INTERNAL_FLASH_H
+
+#include "core/btl_util.h"
+MISRAC_DISABLE
+#include "em_device.h"
+MISRAC_ENABLE
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/***************************************************************************//**
+ * @addtogroup Core Bootloader Core
+ * @{
+ * @addtogroup Flash
+ * @brief Interface to internal flash
+ * @details Used for writing application images to the main flash.
+ * @{
+ ******************************************************************************/
+
+// -----------------------------------------------------------------------------
+// Defines
+
+/// DMA Channel for MSC write
+#define SL_GBL_MSC_LDMA_CHANNEL     2
+
+// -----------------------------------------------------------------------------
+// Prototypes
+
+/**
+ * Erase a flash page.
+ *
+ * @param[in] address Start address of the flash page to erase.
+ * @return True if operation was successful
+ */
+bool flash_erasePage(uint32_t address);
+
+/**
+ * Write buffer to internal flash.
+ *
+ * @param address   Starting address to write data to. Must be half-word aligned.
+ * @param data      Data buffer to write to internal flash
+ * @param length    Amount of bytes in the data buffer to write
+ * @param ch        DMA channel to use
+ * @return True if operation was successful
+ */
+bool flash_writeBuffer_dma(uint32_t       address,
+                           const void           *data,
+                           size_t         length,
+                           int            ch);
+
+/**
+ * Write buffer to internal flash.
+ *
+ * @param address   Starting address to write data to. Must be half-word aligned.
+ * @param data      Data buffer to write to internal flash
+ * @param length    Amount of bytes in the data buffer to write
+ * @return True if operation was successful
+ */
+bool flash_writeBuffer(uint32_t       address,
+                       const void           *data,
+                       size_t         length);
+
+/** @} addtogroup internal_flash */
+/** @} addtogroup core */
+
+#endif // BTL_INTERNAL_FLASH_H

Libs/platform/emdrv/common/inc/ecode.h

@@ -0,0 +1,70 @@
+/***************************************************************************//**
+ * @file
+ * @brief Energy Aware drivers error code definitions.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifndef __SILICON_LABS_ECODE_H__
+#define __SILICON_LABS_ECODE_H__
+
+#include <stdint.h>
+
+/***************************************************************************//**
+ * @addtogroup ecode ECODE - Error Codes
+ * @details ECODE is set of error and status codes related to DMA, RTC, SPI,
+ *        NVM, USTIMER, UARTDRV, EZRADIO, TEMP, and NVM3 drivers. These error and
+ *        status codes are used by the above listed drivers to update the layer
+ *        (using the driver) about an error or status.
+ *
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief Typedef for API function error code return values.
+ *
+ * @details
+ *        Bit 24-31:  Component, for example emdrv @n
+ *        Bit 16-23:  Module, for example @ref uartdrv or @ref spidrv @n
+ *        Bit 0-15:   Error code
+ ******************************************************************************/
+typedef uint32_t Ecode_t;
+
+#define ECODE_EMDRV_BASE  (0xF0000000U)   ///< Base value for all EMDRV errorcodes.
+
+#define ECODE_OK          (0U)            ///< Generic success return value.
+
+#define ECODE_EMDRV_SPIDRV_BASE      (ECODE_EMDRV_BASE | 0x00002000U)   ///< Base value for SPIDRV error codes.
+#define ECODE_EMDRV_NVM_BASE         (ECODE_EMDRV_BASE | 0x00003000U)   ///< Base value for NVM error codes.
+#define ECODE_EMDRV_USTIMER_BASE     (ECODE_EMDRV_BASE | 0x00004000U)   ///< Base value for USTIMER error codes.
+#define ECODE_EMDRV_UARTDRV_BASE     (ECODE_EMDRV_BASE | 0x00007000U)   ///< Base value for UARTDRV error codes.
+#define ECODE_EMDRV_DMADRV_BASE      (ECODE_EMDRV_BASE | 0x00008000U)   ///< Base value for DMADRV error codes.
+#define ECODE_EMDRV_EZRADIODRV_BASE  (ECODE_EMDRV_BASE | 0x00009000U)   ///< Base value for EZRADIODRV error codes.
+#define ECODE_EMDRV_TEMPDRV_BASE     (ECODE_EMDRV_BASE | 0x0000D000U)   ///< Base value for TEMPDRV error codes.
+#define ECODE_EMDRV_NVM3_BASE        (ECODE_EMDRV_BASE | 0x0000E000U)   ///< Base value for NVM3 error codes.
+
+/** @} (end addtogroup ecode) */
+
+#endif // __SILICON_LABS_ECODE_H__

Libs/platform/emdrv/dmadrv/inc/dmadrv.h

@@ -0,0 +1,185 @@
+/***************************************************************************//**
+ * @file
+ * @brief DMADRV API definition.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __SILICON_LABS_DMADRV_H__
+#define __SILICON_LABS_DMADRV_H__
+
+#include "em_device.h"
+
+#include "ecode.h"
+
+#include "dmadrv_signals.h"
+
+#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1)
+#if (_SILICON_LABS_32B_SERIES > 2)
+#define EMDRV_DMADRV_LDMA_S3
+#else
+#define EMDRV_DMADRV_DMA_PRESENT
+#define EMDRV_DMADRV_LDMA
+#endif
+#else
+#error "No valid DMA engine defined."
+#endif
+
+#include "dmadrv_config.h"
+#include "sl_code_classification.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup dmadrv
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup dmadrv_error_codes Error Codes
+ * @{
+ ******************************************************************************/
+
+#define ECODE_EMDRV_DMADRV_OK                  (ECODE_OK)                               ///< A successful return value.
+#define ECODE_EMDRV_DMADRV_PARAM_ERROR         (ECODE_EMDRV_DMADRV_BASE | 0x00000001)   ///< An illegal input parameter.
+#define ECODE_EMDRV_DMADRV_NOT_INITIALIZED     (ECODE_EMDRV_DMADRV_BASE | 0x00000002)   ///< DMA is not initialized.
+#define ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000003)   ///< DMA has already been initialized.
+#define ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED  (ECODE_EMDRV_DMADRV_BASE | 0x00000004)   ///< No DMA channels available.
+#define ECODE_EMDRV_DMADRV_IN_USE              (ECODE_EMDRV_DMADRV_BASE | 0x00000005)   ///< DMA is in use.
+#define ECODE_EMDRV_DMADRV_ALREADY_FREED       (ECODE_EMDRV_DMADRV_BASE | 0x00000006)   ///< A DMA channel was free.
+#define ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED    (ECODE_EMDRV_DMADRV_BASE | 0x00000007)   ///< A channel is not reserved.
+
+/** @} (end addtogroup error codes) */
+/***************************************************************************//**
+ * @brief
+ *  DMADRV transfer completion callback function.
+ *
+ * @details
+ *  The callback function is called when a transfer is complete.
+ *
+ * @param[in] channel
+ *  The DMA channel number.
+ *
+ * @param[in] sequenceNo
+ *  The number of times the callback was called. Useful on long chains of
+ *  linked transfers or on endless ping-pong type transfers.
+ *
+ * @param[in] userParam
+ *  Optional user parameter supplied on DMA invocation.
+ *
+ * @return
+ *   When doing ping-pong transfers, return true to continue or false to
+ *   stop transfers.
+ ******************************************************************************/
+typedef bool (*DMADRV_Callback_t)(unsigned int channel,
+                                  unsigned int sequenceNo,
+                                  void *userParam);
+
+Ecode_t DMADRV_AllocateChannel(unsigned int *channelId,
+                               void         *capabilities);
+Ecode_t DMADRV_DeInit(void);
+Ecode_t DMADRV_FreeChannel(unsigned int channelId);
+Ecode_t DMADRV_Init(void);
+
+Ecode_t DMADRV_MemoryPeripheral(unsigned int              channelId,
+                                DMADRV_PeripheralSignal_t peripheralSignal,
+                                void                      *dst,
+                                void                      *src,
+                                bool                      srcInc,
+                                int                       len,
+                                DMADRV_DataSize_t         size,
+                                DMADRV_Callback_t         callback,
+                                void                      *cbUserParam);
+Ecode_t DMADRV_PeripheralMemory(unsigned int              channelId,
+                                DMADRV_PeripheralSignal_t peripheralSignal,
+                                void                      *dst,
+                                void                      *src,
+                                bool                      dstInc,
+                                int                       len,
+                                DMADRV_DataSize_t         size,
+                                DMADRV_Callback_t         callback,
+                                void                      *cbUserParam);
+Ecode_t DMADRV_MemoryPeripheralPingPong(unsigned int              channelId,
+                                        DMADRV_PeripheralSignal_t peripheralSignal,
+                                        void                      *dst,
+                                        void                      *src0,
+                                        void                      *src1,
+                                        bool                      srcInc,
+                                        int                       len,
+                                        DMADRV_DataSize_t         size,
+                                        DMADRV_Callback_t         callback,
+                                        void                      *cbUserParam);
+Ecode_t DMADRV_PeripheralMemoryPingPong(unsigned int              channelId,
+                                        DMADRV_PeripheralSignal_t peripheralSignal,
+                                        void                      *dst0,
+                                        void                      *dst1,
+                                        void                      *src,
+                                        bool                      dstInc,
+                                        int                       len,
+                                        DMADRV_DataSize_t         size,
+                                        DMADRV_Callback_t         callback,
+                                        void                      *cbUserParam);
+
+#if defined(EMDRV_DMADRV_LDMA)
+Ecode_t DMADRV_LdmaStartTransfer(int                channelId,
+                                 LDMA_TransferCfg_t *transfer,
+                                 LDMA_Descriptor_t  *descriptor,
+                                 DMADRV_Callback_t  callback,
+                                 void               *cbUserParam);
+#elif defined(EMDRV_DMADRV_LDMA_S3)
+Ecode_t DMADRV_LdmaStartTransfer(int                            channelId,
+                                 sl_hal_ldma_transfer_config_t  *transfer,
+                                 sl_hal_ldma_descriptor_t       *descriptor,
+                                 DMADRV_Callback_t              callback,
+                                 void                           *cbUserParam);
+#endif
+
+Ecode_t DMADRV_PauseTransfer(unsigned int channelId);
+Ecode_t DMADRV_ResumeTransfer(unsigned int channelId);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DMADRV, SL_CODE_CLASS_TIME_CRITICAL)
+Ecode_t DMADRV_StopTransfer(unsigned int channelId);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DMADRV, SL_CODE_CLASS_TIME_CRITICAL)
+Ecode_t DMADRV_TransferActive(unsigned int channelId,
+                              bool         *active);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DMADRV, SL_CODE_CLASS_TIME_CRITICAL)
+Ecode_t DMADRV_TransferCompletePending(unsigned int channelId,
+                                       bool         *pending);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DMADRV, SL_CODE_CLASS_TIME_CRITICAL)
+Ecode_t DMADRV_TransferDone(unsigned int channelId,
+                            bool         *done);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DMADRV, SL_CODE_CLASS_TIME_CRITICAL)
+Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId,
+                                      int          *remaining);
+
+/** @} (end addtogroup dmadrv) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SILICON_LABS_DMADRV_H__ */

Libs/platform/emdrv/dmadrv/inc/s2_signals/dmadrv_signals.h

@@ -0,0 +1,223 @@
+#ifndef __SILICON_LABS_DMADRV_SIGNALS_S2_H__
+#define __SILICON_LABS_DMADRV_SIGNALS_S2_H__
+
+#include "em_device.h"
+#include "ecode.h"
+#include "sl_enum.h"
+#include "em_ldma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup dmadrv
+ * @{
+ ******************************************************************************/
+
+#if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0)
+
+/// Maximum length of one DMA transfer.
+#define DMADRV_MAX_XFER_COUNT ((int)((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1))
+
+/// Peripherals that can trigger LDMA transfers.
+SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) {
+  dmadrvPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE,                                                          ///< No peripheral selected for DMA triggering.
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0
+  dmadrvPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1
+  dmadrvPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2
+  dmadrvPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF
+  dmadrvPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0
+  dmadrvPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1
+  dmadrvPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2
+  dmadrvPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF
+  dmadrvPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV
+  dmadrvPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT
+  dmadrvPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL
+  dmadrvPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT
+  dmadrvPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY
+  dmadrvPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV
+  dmadrvPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT
+  dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL
+  dmadrvPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT
+  dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY
+  dmadrvPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV
+  dmadrvPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT
+  dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL
+  dmadrvPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT
+  dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY
+  dmadrvPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV
+  dmadrvPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL
+  dmadrvPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV
+  dmadrvPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL
+  dmadrvPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI
+  dmadrvPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF
+  dmadrvPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0
+  dmadrvPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1
+  dmadrvPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2
+  dmadrvPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3
+  dmadrvPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4
+  dmadrvPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF
+  dmadrvPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF
+  dmadrvPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG
+  dmadrvPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN
+  dmadrvPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE
+  dmadrvPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA
+  dmadrvPeripheralSignal_IMEM_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_IMEM,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0
+  dmadrvPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1
+  dmadrvPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2
+  dmadrvPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF
+  dmadrvPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0
+  dmadrvPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1
+  dmadrvPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2
+  dmadrvPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF
+  dmadrvPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3,
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL
+  dmadrvPeripheralSignal_EUART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0,             ///< Trig on EUART0_TXBL.
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL
+  dmadrvPeripheralSignal_EUART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0,          ///< Trig on EUART0_RXBL.
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL
+  dmadrvPeripheralSignal_EUSART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0,          ///< Trig on EUART0_TXBL.
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL
+  dmadrvPeripheralSignal_EUSART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0,       ///< Trig on EUART0_RXBL.
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL
+  dmadrvPeripheralSignal_EUSART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1,          ///< Trig on EUART1_TXBL.
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL
+  dmadrvPeripheralSignal_EUSART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1,       ///< Trig on EUART1_RXBL.
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL
+  dmadrvPeripheralSignal_EUSART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2,          ///< Trig on EUART2_TXBL.
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL
+  dmadrvPeripheralSignal_EUSART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2,       ///< Trig on EUART2_RXBL.
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL
+  dmadrvPeripheralSignal_EUSART3_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3,          ///< Trig on EUART2_TXBL.
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL
+  dmadrvPeripheralSignal_EUSART3_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3,       ///< Trig on EUART3_RXBL.
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL
+  dmadrvPeripheralSignal_EUSART4_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4,          ///< Trig on EUART4_TXBL.
+  #endif
+  #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL
+  dmadrvPeripheralSignal_EUSART4_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4,       ///< Trig on EUART4_RXBL.
+  #endif
+};
+
+/// Data size of one LDMA transfer item.
+SL_ENUM(DMADRV_DataSize_t) {
+  dmadrvDataSize1 = ldmaCtrlSizeByte, ///< Byte
+  dmadrvDataSize2 = ldmaCtrlSizeHalf, ///< Halfword
+  dmadrvDataSize4 = ldmaCtrlSizeWord  ///< Word
+};
+
+#endif /* defined( LDMAXBAR_COUNT ) && ( LDMAXBAR_COUNT == 1 ) */
+
+/** @} (end addtogroup dmadrv) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SILICON_LABS_DMADRV_SIGNALS_S2_H__ */

Libs/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h

@@ -0,0 +1,132 @@
+/***************************************************************************//**
+ * @file
+ * @brief GPIOINT API definition
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef GPIOINTERRUPT_H
+#define GPIOINTERRUPT_H
+
+#include "em_device.h"
+#include "em_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup gpioint
+ * @{
+ ******************************************************************************/
+/*******************************************************************************
+ *****************************   DEFINITIONS   *********************************
+ ******************************************************************************/
+
+#define INTERRUPT_UNAVAILABLE                         (0xFF) ///< A MACRO for Interrupt Un-available.
+
+/*******************************************************************************
+ *******************************   TYPEDEFS   **********************************
+ ******************************************************************************/
+
+/**
+ * @brief
+ *  GPIO interrupt callback function pointer.
+ * @details
+ *   Parameters:
+ *   @li intNo - The pin interrupt number the callback function is invoked for.
+ */
+typedef void (*GPIOINT_IrqCallbackPtr_t)(uint8_t intNo);
+
+/**
+ * @brief
+ *  Extended GPIO interrupt callback function pointer.
+ * @details
+ *   Parameters:
+ *   @li intNo - The pin interrupt number the callback function is invoked for.
+ *   @li ctx   - Pointer to callback context.
+ */
+typedef void (*GPIOINT_IrqCallbackPtrExt_t)(uint8_t intNo, void *ctx);
+
+/*******************************************************************************
+ ******************************   PROTOTYPES   *********************************
+ ******************************************************************************/
+void GPIOINT_Init(void);
+void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPtr);
+unsigned int GPIOINT_CallbackRegisterExt(uint8_t pin, GPIOINT_IrqCallbackPtrExt_t callbackPtr, void *callbackCtx);
+__STATIC_INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo);
+
+#if defined(_SILICON_LABS_32B_SERIES_2)
+unsigned int GPIOINT_EM4WUCallbackRegisterExt(GPIO_Port_TypeDef port,
+                                              uint8_t pin,
+                                              GPIOINT_IrqCallbackPtrExt_t callbackPtr,
+                                              void *callbackCtx);
+__STATIC_INLINE void GPIOINT_EM4WUCallbackUnRegister(uint8_t intNo);
+#endif
+/***************************************************************************//**
+ * @brief
+ *   Unregister user callback for a given pin interrupt number.
+ *
+ * @details
+ *   Use this function to unregister a callback.
+ *
+ * @param[in] intNo
+ *   Pin interrupt number for the callback.
+ *
+ ******************************************************************************/
+__STATIC_INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo)
+{
+  GPIOINT_CallbackRegister(intNo, 0);
+}
+
+#if defined(_SILICON_LABS_32B_SERIES_2)
+/***************************************************************************//**
+ * @brief
+ *   Unregister user EM4WU callback for a given pin interrupt number.
+ *
+ * @details
+ *   Use this function to unregister a EM4WU callback.
+ *
+ * @param[in] intNo
+ *   Pin interrupt number for the EM4WU callback.
+ *
+ ******************************************************************************/
+__STATIC_INLINE void GPIOINT_EM4WUCallbackUnRegister(uint8_t intNo)
+{
+#if defined(_GPIO_IEN_EM4WUIEN_SHIFT)
+  GPIOINT_CallbackRegister(_GPIO_IEN_EM4WUIEN_SHIFT + intNo, 0);
+#else
+  GPIOINT_CallbackRegister(_GPIO_IEN_EM4WUIEN0_SHIFT + intNo, 0);
+#endif
+}
+#endif
+
+/** @} (end addtogroup gpioint) */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GPIOINTERRUPT_H */

Libs/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c

@@ -0,0 +1,359 @@
+/***************************************************************************//**
+ * @file
+ * @brief GPIOINT API implementation
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include <stddef.h>
+
+#include "gpiointerrupt.h"
+#include "sl_assert.h"
+#include "sl_common.h"
+#include "sl_gpio.h"
+
+/***************************************************************************//**
+ * @addtogroup gpioint
+ * @{
+ ******************************************************************************/
+
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+
+/*******************************************************************************
+ ********************************   DEFINES   **********************************
+ ******************************************************************************/
+
+/// Define for supporting gpiointerrupt porting
+#define SL_GPIO_PORT_INTERRUPT  (0xFF)
+
+/*******************************************************************************
+ *******************************   STRUCTS   ***********************************
+ ******************************************************************************/
+
+typedef struct {
+  /* Pin interrupt number in range of 0 to 31 */
+  uint32_t intNo;
+  /* Pointer to the callback function */
+  void *callback;
+  /* Pointer to the callback context */
+  void *context;
+  /* True if callback takes a context */
+  bool context_flag;
+} GPIOINT_CallbackDesc_t;
+
+/*******************************************************************************
+ **************************   LOCAL FUNCTIONS   *******************************
+ ******************************************************************************/
+
+static void gpioint_map_callback (uint8_t int_no, void *context);
+
+/** @endcond */
+
+/*******************************************************************************
+ ***************************   GLOBAL FUNCTIONS   ******************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   Initialization of GPIOINT module.
+ *
+ ******************************************************************************/
+void GPIOINT_Init(void)
+{
+  sl_gpio_init();
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Registers user callback for given pin interrupt number.
+ *
+ * @details
+ *   Use this function to register a callback which shall be called upon
+ *   interrupt generated for a given pin interrupt number.
+ *   Interrupt itself must be configured externally. Function overwrites previously
+ *   registered callback.
+ *
+ * @param[in] intNo
+ *   Pin interrupt number for the callback.
+ * @param[in] callbackPtr
+ *   A pointer to callback function.
+ ******************************************************************************/
+void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPtr)
+{
+  sl_gpio_t gpio;
+  gpio.port = SL_GPIO_PORT_INTERRUPT;
+  gpio.pin = -1;
+  int32_t int_no = intNo;
+  if (int_no <= GPIO_PIN_MAX) {
+    sl_gpio_configure_external_interrupt(&gpio, &int_no, false, gpioint_map_callback, (void *)callbackPtr);
+  } else {
+#if defined(_GPIO_IEN_EM4WUIEN_SHIFT)
+    int_no = int_no - _GPIO_IEN_EM4WUIEN_SHIFT;
+#else
+    int_no = int_no - _GPIO_IEN_EM4WUIEN0_SHIFT;
+#endif
+    sl_gpio_configure_wakeup_em4_interrupt(&gpio, &int_no, false, gpioint_map_callback, (void *)callbackPtr);
+  }
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Registers user em4 wakeup callback for given port and pin interrupt number.
+ *
+ * @details
+ *   Use this function to register an EM4 wakeup callback with context which shall
+ *   be called upon interrupt generated for a given pin number.
+ *   The function will return an interrupt number if one is available and pin is
+ *   EM4WU compatible.
+ *   Interrupt itself must be configured externally.
+ *
+ * @param[in] port
+ *   GPIO Port for the callback.
+ * @param[in] pin
+ *   Pin number for the callback.
+ * @param[in] callbackPtr
+ *   A pointer to callback function.
+ * @param[in] callbackCtx
+ *   A pointer to the callback context.
+ *
+ * @return
+ *   Interrupt number, or INTERRUPT_UNAVAILABLE if all are in use or pin doesn't
+ *   support em4 wakeup.
+ ******************************************************************************/
+unsigned int GPIOINT_EM4WUCallbackRegisterExt(GPIO_Port_TypeDef port,
+                                              uint8_t pin,
+                                              GPIOINT_IrqCallbackPtrExt_t callbackPtr,
+                                              void *callbackCtx)
+{
+  int32_t intNo = INTERRUPT_UNAVAILABLE;
+  sl_gpio_t gpio;
+  gpio.port = SL_GPIO_PORT_INTERRUPT;
+  gpio.pin = -1;
+
+  if (false) {
+    /* Check all the EM4WU Pins and check if given pin matches any of them. */
+#if defined(GPIO_EM4WU0_PORT)
+  } else if (GPIO_EM4WU0_PORT == port && GPIO_EM4WU0_PIN == pin) {
+    intNo = 0;
+#endif
+#if defined(GPIO_EM4WU1_PORT)
+  } else if (GPIO_EM4WU1_PORT == port && GPIO_EM4WU1_PIN == pin) {
+    intNo = 1;
+#endif
+#if defined(GPIO_EM4WU3_PORT)
+  } else if (GPIO_EM4WU3_PORT == port && GPIO_EM4WU3_PIN == pin) {
+    intNo = 3;
+#endif
+#if defined(GPIO_EM4WU4_PORT)
+  } else if (GPIO_EM4WU4_PORT == port && GPIO_EM4WU4_PIN == pin) {
+    intNo = 4;
+#endif
+#if defined(GPIO_EM4WU6_PORT)
+  } else if (GPIO_EM4WU6_PORT == port && GPIO_EM4WU6_PIN == pin) {
+    intNo = 6;
+#endif
+#if defined(GPIO_EM4WU7_PORT)
+  } else if (GPIO_EM4WU7_PORT == port && GPIO_EM4WU7_PIN == pin) {
+    intNo = 7;
+#endif
+#if defined(GPIO_EM4WU8_PORT)
+  } else if (GPIO_EM4WU8_PORT == port && GPIO_EM4WU8_PIN == pin) {
+    intNo = 8;
+#endif
+#if defined(GPIO_EM4WU9_PORT)
+  } else if (GPIO_EM4WU9_PORT == port && GPIO_EM4WU9_PIN == pin) {
+    intNo = 9;
+#endif
+#if defined(GPIO_EM4WU10_PORT)
+  } else if (GPIO_EM4WU10_PORT == port && GPIO_EM4WU10_PIN == pin) {
+    intNo = 10;
+#endif
+  }
+
+  sl_status_t status = sl_gpio_configure_wakeup_em4_interrupt(&gpio, &intNo, false, (sl_gpio_irq_callback_t)callbackPtr, callbackCtx);
+
+  if (status == SL_STATUS_OK) {
+    return intNo;
+  } else {
+    return INTERRUPT_UNAVAILABLE;
+  }
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Registers user callback for given pin interrupt number.
+ *
+ * @details
+ *   Use this function to register a callback with context which shall be called upon
+ *   interrupt generated for a given pin number.
+ *   The function will return an interrupt number if one is available.
+ *   Interrupt itself must be configured externally.
+ *
+ * @param[in] pin
+ *   Pin number for the callback.
+ * @param[in] callbackPtr
+ *   A pointer to callback function.
+ * @param[in] callbackCtx
+ *   A pointer to the callback context.
+ *
+ * @return
+ *   Interrupt number, or INTERRUPT_UNAVAILABLE if all are in use
+ ******************************************************************************/
+unsigned int GPIOINT_CallbackRegisterExt(uint8_t pin, GPIOINT_IrqCallbackPtrExt_t callbackPtr, void *callbackCtx)
+{
+  sl_gpio_t gpio;
+  gpio.port = SL_GPIO_PORT_INTERRUPT;
+  gpio.pin = pin;
+  int32_t intNo = SL_GPIO_INTERRUPT_UNAVAILABLE;
+  sl_status_t status = sl_gpio_configure_external_interrupt(&gpio, &intNo, false, (sl_gpio_irq_callback_t)callbackPtr, callbackCtx);
+  if (status == SL_STATUS_OK) {
+    return intNo;
+  } else {
+    return INTERRUPT_UNAVAILABLE;
+  }
+}
+
+/*******************************************************************************
+ **************************   LOCAL FUNCTIONS   *******************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   Wrapper function to support porting gpiointerrupt
+ *
+ * @param[in] int_no
+ *   Interrupt number for callback
+ * @param[in] context
+ *   A pointer to callback
+ ******************************************************************************/
+static void gpioint_map_callback(uint8_t int_no, void *context)
+{
+  GPIOINT_IrqCallbackPtr_t old_callback = (GPIOINT_IrqCallbackPtr_t)context;
+  if (old_callback != NULL) {
+    old_callback(int_no);
+  }
+}
+
+/** @endcond */
+
+/** @} (end addtogroup gpioint) */
+
+/* *INDENT-OFF* */
+// ******* THE REST OF THE FILE IS DOCUMENTATION ONLY !************************
+/// @addtogroup gpioint GPIOINT - GPIO Interrupt
+/// @brief GPIOINT General Purpose Input/Output Interrupt dispatcher
+/// @{
+///
+///   @details
+///   The source files for the GPIO interrupt dispatcher library resides in the
+///   emdrv/gpiointerrupt folder, and are named gpiointerrupt.c and gpiointerrupt.h.
+///
+///
+///   @n @section gpioint_intro Introduction
+///   EFM32/EZR32/EFR32 has two GPIO interrupts lines, Odd and Even. If more
+///   than two interrupts are used then interrupt routine must dispatch from a callback
+///   register. This module provides small dispatcher for both GPIO interrupts enabling
+///   handling of up to 32 GPIO pin interrupts.
+///
+///   It is up to the user to configure and enable interrupt on given pin. This can be done
+///   using the GPIO library (emlib). This module handles the dispatch register and clearing of
+///   interrupt flags.
+///
+///   In order to use this dispatcher, it has to be initialized first by
+///   calling GPIOINT_Init(). Then each pin interrupt number must be configured by first
+///   registering the callback function for given interrupt number and then configure and
+///   enabling the interrupt number in the GPIO module.
+///
+///   The extended function GPIOINT_CallbackRegisterExt() may also be used to register a callback
+///   with context for a given pin number. The first available interrupt number will be returned.
+///
+///   @n @section gpioint_api The API
+///   This section contain brief descriptions of the functions in the API. You will
+///   find detailed information on parameters by clicking on the hyperlinked function names.
+///
+///   Your application code must include one header file: @em gpiointerrupt.h.
+///
+///   @ref GPIOINT_Init() @n
+///    This functions initializes the dispatcher register. Typically
+///    GPIOINT_Init() is called once in your startup code.
+///
+///   @ref GPIOINT_CallbackRegister() @n
+///    Register a callback function on a pin interrupt number.
+///
+///   @ref GPIOINT_CallbackUnRegister() @n
+///    Un-register a callback function on a pin interrupt number.
+///
+///   @ref GPIOINT_CallbackRegisterExt() @n
+///    Register a callback function with context on a pin number.
+///
+///   @n @section gpioint_example Example
+///   @code{.c}
+///
+///#include "gpiointerrupt.h"
+///
+///#include "em_chip.h"
+///#include "em_cmu.h"
+///#include "em_gpio.h"
+///
+///// An array to track if given pin callback was called
+///volatile uint8_t pinInt[32];
+///
+///// Gpio callbacks called when pin interrupt was triggered.
+///void gpioCallback1(uint8_t intNo)
+///{
+///  pinInt[intNo]++;
+///}
+///
+///void gpioCallback3(uint8_t intNo)
+///{
+///  pinInt[intNo]++;
+///}
+///
+///void gpioCallback8(uint8_t intNo)
+///{
+///  pinInt[intNo]++;
+///}
+///
+///int main(void)
+///{
+///  CHIP_Init();
+///
+///  // Enable clock for GPIO module, initialize GPIOINT
+///  CMU_ClockEnable(cmuClock_GPIO, true);
+///  GPIOINT_Init();
+///
+///  // Register callback functions and enable interrupts
+///  GPIOINT_CallbackRegister(1, gpioCallback1);
+///  GPIOINT_CallbackRegister(3, gpioCallback3);
+///  unsigned int intPin8 = GPIOINT_CallbackRegisterExt(8, gpioCallback8, (void *)callback8context);
+///  GPIO_IntEnable(1<<1 | 1<<3 | 1<<intPin8);
+///
+///  while(true);
+///}
+///
+///   @endcode
+///
+/// @} end group gpioint *******************************************************

Libs/platform/emdrv/nvm3/config/nvm3_config.h

@@ -0,0 +1,61 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 configuration file.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifndef NVM3_CONFIG_H
+#define NVM3_CONFIG_H
+
+/***************************************************************************//**
+ * @addtogroup nvm3
+ * @{
+ ******************************************************************************/
+
+/*** Driver instrumentation options */
+#define NVM3_TRACE_PORT_NONE               0               // Nothing is printed
+#define NVM3_TRACE_PORT_PRINTF             1               // Print is available
+#define NVM3_TRACE_PORT_UNITYPRINTF        2               // Unity print is available
+
+#define NVM3_TRACE_PORT                    NVM3_TRACE_PORT_NONE
+
+/*** Event level
+     0 Critical: Trace only critical events
+     1 Warning : Trace warning events and above
+     2 Info    : Trace info events and above
+ */
+#define NVM3_TRACE_LEVEL_ERROR             0
+#define NVM3_TRACE_LEVEL_WARNING           1
+#define NVM3_TRACE_LEVEL_INFO              2
+#define NVM3_TRACE_LEVEL_LOW               3
+
+#define NVM3_TRACE_LEVEL                   NVM3_TRACE_LEVEL_WARNING
+
+#define NVM3_ASSERT_ON_ERROR               false
+
+/** @} (end addtogroup nvm3) */
+
+#endif /* NVM3_CONFIG_H */

Libs/platform/emdrv/nvm3/inc/nvm3.h

@@ -0,0 +1,104 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 API definition (Device Specific).
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef NVM3_H
+#define NVM3_H
+
+#ifndef NVM3_HOST_BUILD
+#include "em_device.h"
+#endif
+
+#include "nvm3_generic.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup nvm3
+ * @{
+ ******************************************************************************/
+
+#define NVM3_MIN_FRAGMENT_COUNT         (2U)                            ///< The minimum number of fragments
+#if defined(FLASH_PAGE_SIZE)
+#define NVM3_MAX_OBJECT_SIZE_X          (NVM3_MAX_OBJECT_SIZE + 8)      // Adjust for an object header
+#define FLASH_PAGE_SIZE_X               (FLASH_PAGE_SIZE - 20)          // Adjust for a page header
+#define NVM3_FRAGMENT_COUNT             (((NVM3_MAX_OBJECT_SIZE_X - 1) / FLASH_PAGE_SIZE_X) + NVM3_MIN_FRAGMENT_COUNT)
+#endif
+
+typedef struct nvm3_ObjFrag {
+  uint8_t              idx;                 // Fragment index
+  bool                 isFirstFragFound;    // The object first fragment found
+  bool                 isLastFragFound;     // The object last fragment found
+#if defined(FLASH_PAGE_SIZE)
+  nvm3_ObjFragDetail_t detail[NVM3_FRAGMENT_COUNT];
+#else
+  nvm3_ObjFragDetail_t detail[NVM3_MIN_FRAGMENT_COUNT];
+#endif
+} nvm3_ObjFrag_t;
+
+typedef struct nvm3_Obj {
+  nvm3_ObjectKey_t  key;          // The object key
+  struct nvm3_Obj   *objAdr;      // The object pointer
+  struct nvm3_Obj   *nextObjAdr;  // The next object pointer
+  const void        *srcPtr;      // May be used to carry the source address of the data
+  size_t            totalLen;     // The object total length
+  uint8_t           objType;      // The object type
+  bool              isHdrValid;   // The object header is valid
+  bool              isValid;      // The object is valid
+  bool              isFragmented; // The object is fragmented
+  nvm3_ObjFrag_t    frag;         // The object fragment information
+} nvm3_Obj_t;
+
+// Definition of NVM3 variables
+/// @brief A variable used by the NVM3 functions.
+extern nvm3_Obj_t nvm3_internalObjectHandleA;
+/// @brief A variable used by the NVM3 functions.
+extern nvm3_Obj_t nvm3_internalObjectHandleB;
+/// @brief A variable used by the NVM3 functions.
+extern nvm3_Obj_t nvm3_internalObjectHandleC;
+/// @brief A variable used by the NVM3 functions.
+extern nvm3_Obj_t nvm3_internalObjectHandleD;
+#if defined(NVM3_SECURITY)
+/// @brief A variable used by the NVM3 functions.
+extern nvm3_Obj_t nvm3_internalObjectHandleE;
+#endif
+/// @brief A variable that must contain the maximum number of object fragments.
+extern const uint8_t  nvm3_maxFragmentCount;
+/// @brief A variable containing the object handle size in bytes.
+extern const size_t   nvm3_objHandleSize;
+
+#ifdef __cplusplus
+}
+#endif
+
+/// @} end group nvm3 ****************************************************/
+
+#endif /* NVM3_H */

Libs/platform/emdrv/nvm3/inc/nvm3_cache.h

@@ -0,0 +1,71 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 object cache
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef NVM3_CACHE_H
+#define NVM3_CACHE_H
+
+#include "nvm3_config.h"
+#include "nvm3.h"
+#include "nvm3_object.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ *******************************   TYPES   *************************************
+ ******************************************************************************/
+
+typedef bool (*nvm3_CacheScanCallback_t)(nvm3_Cache_t *h, nvm3_ObjectKey_t key, nvm3_ObjGroup_t group, nvm3_ObjPtr_t obj, void *user);
+
+/*******************************************************************************
+ ***************************   PROTOTYPES   ************************************
+ ******************************************************************************/
+
+void nvm3_cacheOpen(nvm3_Cache_t *h, nvm3_CacheEntry_t *ptr, size_t count);
+void nvm3_cacheClear(nvm3_Cache_t *h);
+void nvm3_cacheDelete(nvm3_Cache_t *h, nvm3_ObjectKey_t key);
+nvm3_ObjPtr_t nvm3_cacheGet(nvm3_Cache_t *h, nvm3_ObjectKey_t key, nvm3_ObjGroup_t *group);
+void nvm3_cacheSet(nvm3_Cache_t *h, nvm3_ObjectKey_t key, nvm3_ObjPtr_t obj, nvm3_ObjGroup_t group);
+
+void nvm3_cacheScan(nvm3_Cache_t *h, nvm3_CacheScanCallback_t cacheScanCallback, void *user);
+#if defined(NVM3_OPTIMIZATION) && (NVM3_OPTIMIZATION == 1)
+sl_status_t nvm3_cacheSort(nvm3_Cache_t *h);
+bool nvm3_cacheUpdateEntry(nvm3_Cache_t *h, nvm3_ObjectKey_t key, nvm3_ObjPtr_t obj, nvm3_ObjGroup_t group);
+sl_status_t nvm3_cacheAddEntry(nvm3_Cache_t *h, nvm3_ObjectKey_t key, nvm3_ObjPtr_t obj, nvm3_ObjGroup_t group);
+sl_status_t nvm3_cacheGetIdx(nvm3_Cache_t *h, nvm3_ObjectKey_t key, size_t low, size_t high, size_t *idx);
+void nvm3_cacheOrganize(nvm3_Cache_t *h, size_t idx);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NVM3_CACHE_H */

Libs/platform/emdrv/nvm3/inc/nvm3_default.h

@@ -0,0 +1,71 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 definition of the default data structures.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef NVM3_DEFAULT_H
+#define NVM3_DEFAULT_H
+#include "nvm3_generic.h"
+
+/***************************************************************************//**
+ * @addtogroup nvm3
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup nvm3default NVM3 Default Instance
+ * @brief NVM3 default instance functions and handles
+ * @{
+ ******************************************************************************/
+
+extern nvm3_Handle_t *nvm3_defaultHandle;       ///< The default handle.
+extern nvm3_Init_t   *nvm3_defaultInit;         ///< Default initialization data.
+
+/***************************************************************************//**
+ * @brief
+ *  Initialize the default NVM3 instance.
+ *  Once initialized the instance can be accessed through the NVM3 API using
+ *  nvm3_defaultHandle as the nvm3_Handle_t handle.
+ *
+ * @return
+ *   @ref SL_STATUS_OK on success and a NVM3 @ref sl_status_t on failure.
+ ******************************************************************************/
+sl_status_t nvm3_initDefault(void);
+
+/***************************************************************************//**
+ * @brief
+ *  Deinit the default NVM3 instance.
+ *
+ * @return
+ *   @ref SL_STATUS_OK on success and a NVM3 @ref sl_status_t on failure.
+ ******************************************************************************/
+sl_status_t nvm3_deinitDefault(void);
+
+/** @} (end addtogroup nvm3default) */
+/** @} (end addtogroup nvm3) */
+
+#endif /* NVM3_DEFAULT_H */

Libs/platform/emdrv/nvm3/inc/nvm3_hal.h

@@ -0,0 +1,249 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 driver HAL
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef NVM3_HAL_H
+#define NVM3_HAL_H
+
+#include "sl_status.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+#ifdef NVM3_HOST_BUILD
+#include "nvm3_hal_host.h"
+#else
+#include "sl_assert.h"
+#include "sl_common.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup nvm3
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup nvm3hal NVM3 HAL
+ * @brief NVM3 Hardware Abstraction Layer
+ * @{
+ * @details
+ * This module provides the interface to the NVM. By having all NVM access
+ * functions in a separate file, it is possible to support different hardware
+ * by substituting the functions in this module.
+ *
+ * @note These functions are used by the NVM3 and should not be used by
+ * any applications.
+ ******************************************************************************/
+
+/******************************************************************************
+ ******************************    MACROS    **********************************
+ *****************************************************************************/
+
+#define NVM3_HAL_WRITE_SIZE_32    0     ///< Only single writes are allowed
+#define NVM3_HAL_WRITE_SIZE_16    1     ///< Two writes are allowed
+
+#define NVM3_HAL_NVM_ACCESS_NONE  0     ///< No access
+#define NVM3_HAL_NVM_ACCESS_RD    1     ///< Read access
+#define NVM3_HAL_NVM_ACCESS_RDWR  2     ///< Read and write access
+#define NVM3_HAL_NVM_ACCESS_NOP   3     ///< Ignore
+
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+
+#define nvm3_halOpen(hal, a, b)           ((hal)->open((a), (b)))
+#define nvm3_halClose(hal)                ((hal)->close())
+#define nvm3_halGetInfo(hal, a)           ((hal)->getInfo(a))
+#define nvm3_halNvmAccess(hal, a)         ((hal)->access(a))
+#define nvm3_halReadWords(hal, a, b, c)   ((hal)->readWords((a), (b), (c)))
+#define nvm3_halWriteWords(hal, a, b, c)  ((hal)->writeWords((a), (b), (c)))
+#define nvm3_halPageErase(hal, a)         ((hal)->pageErase(a))
+
+/// @endcond
+
+/******************************************************************************
+ ******************************   TYPEDEFS   **********************************
+ *****************************************************************************/
+
+/// @brief Pointer to NVM
+typedef void   *nvm3_HalPtr_t;
+
+/// @brief Device NVM capabilities
+
+typedef struct nvm3_HalInfo {
+  uint16_t deviceFamilyPartNumber;  ///< Device family or part number.
+  uint8_t writeSize;                ///< Write-size: 0=32-bit, 1=16-bit.
+  uint8_t memoryMapped;             ///< Memory-mapped: 0=not memory mapped, 1=memory mapped.
+  size_t pageSize;                  ///< The data storage page size.
+  uint64_t systemUnique;            ///< Obsolete. Was used to support external flash.
+} nvm3_HalInfo_t;
+
+typedef uint8_t nvm3_HalNvmAccessCode_t; ///< Definition of the access data type.
+
+/*******************************************************************************
+ *****************************   PROTOTYPES   **********************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *  Open the NVM3 HAL for usage.
+ *
+ * @details
+ *   This function must be run at initialization, before any other functions
+ *   are called. It is used to call necessary startup routines before the
+ *   hardware can be accessed.
+ *
+ * @param[in] nvmAdr
+ *   A pointer to the destination in NVM.
+ *
+ * @param[in] nvmSize
+ *   The total size of the NVM.
+ *
+ * @return
+ *   The result of the open call.
+ *   @ref SL_STATUS_OK on success or a NVM3 @ref sl_status_t on failure.
+ ******************************************************************************/
+typedef sl_status_t (*nvm3_HalOpen_t)(nvm3_HalPtr_t nvmAdr, size_t nvmSize);
+
+/***************************************************************************//**
+ * @brief
+ *  Close the NVM3 HAL for usage.
+ *
+ * @details
+ *   This function should be called at program termination.
+ *   Should be done before any graceful halts.
+ ******************************************************************************/
+typedef void(*nvm3_HalClose_t)(void);
+
+/***************************************************************************//**
+ * @brief
+ *   Retrieve device information.
+ *
+ * @details
+ *   This function is used to retrieve information about the device properties,
+ *   such as the device family, write size, whether the NVM is memory mapped or
+ *   not, and finally the NVM page size.
+ *
+ * @param[in] info
+ *   A pointer to a structure that will receive the device information.
+ ******************************************************************************/
+typedef sl_status_t (*nvm3_HalGetInfo_t)(nvm3_HalInfo_t *info);
+
+/***************************************************************************//**
+ * @brief
+ *   Control read and write access to the NVM.
+ *
+ * @details
+ *   This function is used to control the access to the NVM. It can be either
+ *   read, write, or none.
+ *
+ * @param[in] access
+ *   The requested access.
+ ******************************************************************************/
+typedef void (*nvm3_HalNvmAccess_t)(nvm3_HalNvmAccessCode_t access);
+
+/***************************************************************************//**
+ * @brief
+ *   Erase a page in the NVM.
+ *
+ * @details
+ *   This function is used to erase an NVM page.
+ *
+ * @param[in] nvmAdr
+ *   A memory address pointing to the start of the page to erase.
+ *
+ * @return
+ *   The result of the erase operation.
+ ******************************************************************************/
+typedef sl_status_t (*nvm3_HalPageErase_t)(nvm3_HalPtr_t nvmAdr);
+
+/***************************************************************************//**
+ * @brief
+ *   Read data from NVM.
+ *
+ * @details
+ *   This function is used to read data from the NVM. It will be a
+ *   blocking call, since the thread asking for data to be read cannot continue
+ *   without the data.
+ *
+ * @param[in] nvmAdr
+ *   A memory address in NVM where data will be read.
+ *
+ * @param[in] *dst
+ *   A pointer to the destination buffer.
+ *
+ * @param[in] wordCnt
+ *   The number of words to read.
+ ******************************************************************************/
+typedef sl_status_t (*nvm3_HalReadWords_t)(nvm3_HalPtr_t nvmAdr, void *dst, size_t wordCnt);
+
+/***************************************************************************//**
+ * @brief
+ *   Write data to the NVM.
+ *
+ * @details
+ *   This function is used to write data to the NVM. This is a blocking
+ *   function.
+ *
+ * @param[in] nvmAdr
+ *   A memory address in NVM where data will be written.
+ *
+ * @param[in] *pSrc
+ *   A pointer to the source data.
+ *
+ * @param[in] cnt
+ *   The number of words to write.
+ *
+ * @return
+ *   The result of the write operation.
+ *   @ref SL_STATUS_OK on success or a NVM3 @ref sl_status_t on failure.
+ ******************************************************************************/
+typedef sl_status_t (*nvm3_HalWriteWords_t)(nvm3_HalPtr_t nvmAdr, void const *pSrc, size_t cnt);
+
+/// @brief The HAL handle definition.
+typedef struct {
+  nvm3_HalOpen_t          open;         ///< Pointer to the open function
+  nvm3_HalClose_t         close;        ///< Pointer to the close function
+  nvm3_HalGetInfo_t       getInfo;      ///< Pointer to the get-info function
+  nvm3_HalNvmAccess_t     access;       ///< Pointer to the access function
+  nvm3_HalPageErase_t     pageErase;    ///< Pointer to the page-erase function
+  nvm3_HalReadWords_t     readWords;    ///< Pointer to the read-words function
+  nvm3_HalWriteWords_t    writeWords;   ///< Pointer to the write-words function
+} nvm3_HalHandle_t;
+
+/** @} (end addtogroup nvm3hal) */
+/** @} (end addtogroup nvm3) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NVM3_HAL_H */

Libs/platform/emdrv/nvm3/inc/nvm3_hal_flash.h

@@ -0,0 +1,68 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 driver HAL for memory mapped FLASH
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef NVM3_HAL_FLASH_H
+#define NVM3_HAL_FLASH_H
+
+#include "nvm3_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup nvm3
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup nvm3hal
+ * @{
+ * @details
+ * This module provides the NVM3 interface to the EFM and EFR Flash NVM.
+ *
+ * @note The features available through the handle are used by the NVM3 and
+ * should not be used directly by any applications.
+ ******************************************************************************/
+
+/*******************************************************************************
+ ***************************   GLOBAL VARIABLES   ******************************
+ ******************************************************************************/
+
+extern const nvm3_HalHandle_t nvm3_halFlashHandle;      ///< The HAL flash handle.
+
+/** @} (end addtogroup nvm3hal) */
+/** @} (end addtogroup nvm3) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NVM3_HAL_FLASH_H */

Libs/platform/emdrv/nvm3/inc/nvm3_lock.h

@@ -0,0 +1,93 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 data access lock API definition
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef NVM3_LOCK_H
+#define NVM3_LOCK_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup nvm3
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup nvm3lock NVM3 Lock
+ * @brief NVM3 lock functions
+ * @{
+ * @details
+ * This module provides data protection tools for NVM3.
+ *
+ * The functions in this module are the default protection tools for NVM3.
+ * The application can substitute the nvm3_lockBegin and nvm3_lockEnd
+ * functions as long as the NVM3 functions are protected from
+ * being called re-entrant.
+ *
+ * @note These functions are used by the NVM3 and should not be used by
+ * any applications.
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *  Create a mutex to lock and unlock section.
+ ******************************************************************************/
+void nvm3_lockCreateMutex(void);
+
+/***************************************************************************//**
+ * @brief
+ *  Begin a lock section.
+ ******************************************************************************/
+void nvm3_lockBegin(void);
+
+/***************************************************************************//**
+ * @brief
+ *  End a lock section.
+ ******************************************************************************/
+void nvm3_lockEnd(void);
+
+/***************************************************************************//**
+ * @brief
+ *  Disable execution from data area.
+ ******************************************************************************/
+void nvm3_lockDisableExecute(void* address, size_t size);
+
+/** @} (end addtogroup nvm3lock) */
+/** @} (end addtogroup nvm3) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //NVM3_LOCK_H

Libs/platform/emdrv/nvm3/inc/nvm3_object.h

@@ -0,0 +1,111 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 object definition
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef NVM3_OBJECT_H
+#define NVM3_OBJECT_H
+
+#include "nvm3_hal.h"
+#include "nvm3_config.h"
+#include "nvm3.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+#define NVM3_OBJ_SMALL_MAX_SIZE          120U                              // Small object is limited to 120 bytes
+#define NVM3_OBJ_PTR_INVALID             ((nvm3_ObjPtr_t)(-1L))
+#define NVM3_OBJ_HDR_PTR_INVALID         ((nvm3_ObjHdrPtr_t)(-1L))
+#define NVM3_OBJ_HEADER_SIZE_LARGE       (sizeof(nvm3_ObjHdrLarge_t))
+#define NVM3_OBJ_HEADER_SIZE_WLARGE      (sizeof(nvm3_ObjHdrLarge_t) / sizeof(uint32_t))
+#define NVM3_OBJ_HEADER_SIZE_SMALL       (sizeof(nvm3_ObjHdrSmall_t))
+#define NVM3_OBJ_HEADER_SIZE_WSMALL      (sizeof(nvm3_ObjHdrSmall_t) / sizeof(uint32_t))
+#define NVM3_OBJ_HEADER_SIZE_COUNTER     (NVM3_OBJ_HEADER_SIZE_LARGE)
+
+typedef struct nvm3_ObjHeaderSmall {
+  uint32_t oh1;
+} nvm3_ObjHdrSmall_t;
+
+typedef struct nvm3_ObjHeaderLarge {
+  uint32_t oh1;
+  uint32_t oh2;
+} nvm3_ObjHdrLarge_t;
+
+typedef nvm3_ObjHdrSmall_t *nvm3_ObjHdrSmallPtr_t;
+typedef nvm3_ObjHdrLarge_t *nvm3_ObjHdrLargePtr_t;
+
+typedef enum {
+  objTypeDataLarge = 0,
+  objTypeCounterLarge = 1,
+  objTypeCounterSmall = 2,
+  objTypeDeleted = 3,
+  objTypeRes_1 = 4,
+  objTypeRes_2 = 5,
+  objTypeRes_3 = 6,
+  objTypeDataSmall = 7,
+} nvm3_ObjType_t;
+
+typedef enum {
+  objGroupUnknown,
+  objGroupData,
+  objGroupCounter,
+  objGroupDeleted,
+} nvm3_ObjGroup_t;
+
+typedef enum {
+  fragTypeNone = 0,
+  fragTypeFirst = 1,
+  fragTypeNext = 2,
+  fragTypeLast = 3,
+} nvm3_ObjFragType_t;
+
+typedef nvm3_Obj_t *nvm3_ObjPtr_t;
+
+void nvm3_objInit(nvm3_ObjPtr_t obj, nvm3_ObjPtr_t objAdr);
+size_t nvm3_objHdrInit(nvm3_ObjHdrLargePtr_t oh, nvm3_ObjectKey_t key, nvm3_ObjType_t objType, size_t len, bool isLarge, nvm3_ObjFragType_t fragTyp);
+size_t nvm3_objHdrLen(bool isLarge);
+bool nvm3_objHdrValidateSmall(nvm3_ObjHdrSmallPtr_t objHdrSmall);
+bool nvm3_objHdrValidateLarge(nvm3_ObjHdrLargePtr_t objHdrLarge);
+bool nvm3_objHdrGetErased(nvm3_ObjHdrSmallPtr_t objHdrSmall);
+nvm3_ObjFragType_t nvm3_objHdrGetFragTyp(nvm3_ObjHdrSmallPtr_t objHdrSmall);
+nvm3_ObjectKey_t nvm3_objHdrGetKey(nvm3_ObjHdrSmallPtr_t objHdrSmall);
+bool nvm3_objHdrGetHdrIsLarge(nvm3_ObjHdrSmallPtr_t objHdrSmall);
+size_t nvm3_objHdrGetHdrLen(nvm3_ObjHdrSmallPtr_t objHdrSmall);
+size_t nvm3_objHdrGetDatLen(nvm3_ObjHdrLargePtr_t objHdrLarge);
+nvm3_ObjType_t nvm3_objHdrGetType(nvm3_ObjHdrSmallPtr_t objHdrSmall);
+nvm3_ObjType_t nvm3_objGroupToType(nvm3_ObjGroup_t objGroup, bool hdrIsLarge);
+nvm3_ObjGroup_t nvm3_objTypeToGroup(nvm3_ObjType_t objType);
+/// @endcond
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NVM3_OBJECT_H */

Libs/platform/emdrv/nvm3/inc/nvm3_page.h

@@ -0,0 +1,97 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 page handling functions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef NVM3_PAGE_H
+#define NVM3_PAGE_H
+
+#include "nvm3_hal.h"
+#include "nvm3_object.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+
+#define NVM3_PAGE_COUNTER_SIZE          27U         // 27 bits
+#define NVM3_PAGE_COUNTER_MASK          ((1U << NVM3_PAGE_COUNTER_SIZE) - 1U)
+#define NVM3_PAGE_BCCB_SIZE             5U          //  5 bits
+#define NVM3_PAGE_BCCB_MASK             ((1U << NVM3_PAGE_BCCB_SIZE) - 1U)
+
+#define NVM3_PAGE_HEADER_WORDS          5           // The number of words in the page header
+#define NVM3_PAGE_HEADER_SIZE           (sizeof(nvm3_PageHdr_t))
+#define NVM3_PAGE_HEADER_WSIZE          (sizeof(nvm3_PageHdr_t) / sizeof(uint32_t))
+#define NVM3_PAGE_H1_OFFSET             (0 * sizeof(uint32_t))
+#define NVM3_PAGE_H2_OFFSET             (1 * sizeof(uint32_t))
+#define NVM3_PAGE_H3_OFFSET             (2 * sizeof(uint32_t))
+#define NVM3_PAGE_H4_OFFSET             (3 * sizeof(uint32_t))
+#define NVM3_PAGE_H5_OFFSET             (4 * sizeof(uint32_t))
+
+#define NVM3_ERASE_COUNT_INVALID        0xFFFFFFFFU
+#define NVM3_PAGE_INDEX_INVALID         0xFFFFU
+
+typedef struct nvm3_PageHdr {
+  uint32_t    data[NVM3_PAGE_HEADER_WORDS];
+} nvm3_PageHdr_t;
+
+/// @endcond
+
+typedef enum {
+  nvm3_PageStateGood,
+  nvm3_PageStateGoodEip,
+  nvm3_PageStateBad,
+  nvm3_PageStateInvalidErased,
+  nvm3_PageStateInvalidUnknown,
+} nvm3_PageState_t;
+
+#if defined(NVM3_SECURITY)
+sl_status_t nvm3_pageHeaderWrite(const nvm3_HalHandle_t *hal, nvm3_HalPtr_t pageAdr, uint32_t eraseCnt, nvm3_HalInfo_t *halInfo, nvm3_SecurityType_t secType);
+#else
+sl_status_t nvm3_pageHeaderWrite(const nvm3_HalHandle_t *hal, nvm3_HalPtr_t pageAdr, uint32_t eraseCnt, nvm3_HalInfo_t *halInfo);
+#endif
+void nvm3_pageSetBad(const nvm3_HalHandle_t *hal, nvm3_HalPtr_t pageAdr);
+sl_status_t nvm3_pageSetEip(const nvm3_HalHandle_t *hal, nvm3_HalPtr_t pageAdr);
+uint32_t nvm3_pageGetEraseCnt(nvm3_PageHdr_t *pageHdr);
+nvm3_PageState_t nvm3_pageGetState(nvm3_PageHdr_t *pageHdr);
+bool nvm3_pageStateIsGood(nvm3_PageState_t pageState);
+bool nvm3_pageStateIsInvalid(nvm3_PageState_t pageState);
+nvm3_ObjPtr_t nvm3_pageGetFirstObj(nvm3_HalPtr_t pageAdr);
+#if defined(NVM3_SECURITY)
+nvm3_SecurityType_t nvm3_pageGetSecType(nvm3_PageHdr_t *pageHdr);
+sl_status_t nvm3_pageErase(const nvm3_HalHandle_t *hal, nvm3_HalPtr_t pageAdr, uint32_t eraseCnt, nvm3_HalInfo_t *halInfo, nvm3_SecurityType_t secType);
+#else
+sl_status_t nvm3_pageErase(const nvm3_HalHandle_t *hal, nvm3_HalPtr_t pageAdr, uint32_t eraseCnt, nvm3_HalInfo_t *halInfo);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NVM3_PAGE_H */

Libs/platform/emdrv/nvm3/inc/nvm3_trace.h

@@ -0,0 +1,74 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 trace macros
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifndef NVM3_TRACE_H
+#define NVM3_TRACE_H
+
+#include "nvm3_config.h"
+#include <stdint.h>
+#if (NVM3_TRACE_PORT == NVM3_TRACE_PORT_PRINTF)
+#include <stdio.h>
+#endif
+#if NVM3_TRACE_PORT == NVM3_TRACE_PORT_UNITYPRINTF
+#include "unity.h"
+#endif
+
+/***************************************************************************//**
+ * @addtogroup nvm3trace NVM3 Trace
+ * @brief NVM3 Trace functions
+ * @{
+ ******************************************************************************/
+
+/*** */
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+
+// Temporary solution, shoud use NVM3_TRACE_LEVEL as well
+#define NVM3_TRACE_ENABLED (NVM3_TRACE_PORT != NVM3_TRACE_PORT_NONE)
+
+#ifdef NVM3_HOST_BUILD
+#define UnityPrintf(...)      nvm3_tracePrint(NVM3_TRACE_LEVEL, __VA_ARGS__)
+#define UNITY_PRINT_EOL()     nvm3_tracePrint(NVM3_TRACE_LEVEL, "\n")
+#define TEST_PRINTF           UnityPrintf
+#define TEST_MESSAGE          UnityPrintf
+#define UNITY_OUTPUT_CHAR     UnityPrintf
+#endif
+
+#if (NVM3_TRACE_PORT == NVM3_TRACE_PORT_PRINTF)
+#define nvm3_tracePrint(lev, ...) do { if (lev <= NVM3_TRACE_LEVEL) { printf(__VA_ARGS__); } } while (0)
+#elif (NVM3_TRACE_PORT == NVM3_TRACE_PORT_UNITYPRINTF)
+#define nvm3_tracePrint(lev, ...) do { if (lev <= NVM3_TRACE_LEVEL) { UnityPrintf(__VA_ARGS__); } } while (0)
+#else
+#define nvm3_tracePrint(lev, ...)
+#endif
+
+/// @endcond
+
+/** @} (end addtogroup nvm3trace) */
+
+#endif /* NVM3_TRACE_H */

Libs/platform/emdrv/nvm3/inc/nvm3_utils.h

@@ -0,0 +1,68 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 utility functions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef NVM3_UTILS_H
+#define NVM3_UTILS_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+
+/***************************************************************************//**
+ * @brief
+ *  This function calculates the Berger Code of the supplied input variable.
+ *  The Berger Code is calculated by looking at the binary value of the variable
+ *  and counting the number of binary zeros.
+ *
+ * @param[in, out] pResult
+ *   A pointer to a variable that will accumulate the berger code for
+ *   the input variable specified in the next two variables.
+ *
+ * @param[in] pInput
+ *   A pointer to the variable that contains data that is used.
+ *
+ * @param[in] numberOfBits
+ *   The number of bits in the input variable used in the calculation.
+ *   The calculation is starting from the least significant bit in the input
+ *   variable.
+ ******************************************************************************/
+void nvm3_utilsComputeBergerCode(uint8_t *pResult, void *pInput, uint8_t numberOfBits);
+
+/// @endcond
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NVM3_UTILS_H */

Libs/platform/emdrv/nvm3/src/nvm3_cache.c

@@ -0,0 +1,672 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 object cache
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include "nvm3_cache.h"
+#include "nvm3_trace.h"
+
+#if defined(__ICCARM__)
+#define SPEED_OPT _Pragma("optimize=speed")
+#elif defined(__GNUC__) && defined(__CORTEX_M)
+#define SPEED_OPT _Pragma("GCC optimize(\"O3\")")
+#else
+#define SPEED_OPT
+#endif
+
+#define TRACE_LEVEL                 NVM3_TRACE_LEVEL_LOW
+
+#if defined(NVM3_OPTIMIZATION) && (NVM3_OPTIMIZATION == 1)
+#include "sl_memory_manager.h"
+#endif
+
+//****************************************************************************
+
+// isValid is implemented as a macro as this significantly improves
+// speed when using compiler settings that do not inline these functions.
+#define isValid(h, idx) (h->entryPtr[idx].key != NVM3_KEY_INVALID)
+
+#if defined(NVM3_OPTIMIZATION) && (NVM3_OPTIMIZATION == 1)
+uint32_t *L;
+uint32_t *H;
+uint32_t *P1;
+uint32_t *P2;
+uint32_t *K1;
+uint32_t *K2;
+#endif
+
+static inline nvm3_ObjectKey_t entryGetKey(nvm3_Cache_t *h, size_t idx)
+{
+  uint32_t tmp = (uint32_t)h->entryPtr[idx].key;
+  return (nvm3_ObjectKey_t)(tmp & NVM3_KEY_MASK);
+}
+
+static inline nvm3_ObjGroup_t entryGetGroup(nvm3_Cache_t *h, size_t idx)
+{
+  uint32_t tmp = (uint32_t)h->entryPtr[idx].key;
+  return (nvm3_ObjGroup_t)(tmp >> NVM3_KEY_SIZE);
+}
+
+static inline nvm3_ObjPtr_t entryGetPtr(nvm3_Cache_t *h, size_t idx)
+{
+  return h->entryPtr[idx].ptr;
+}
+
+static inline void entrySetKey(nvm3_Cache_t *h, size_t idx, nvm3_ObjectKey_t key)
+{
+  uint32_t tmp = (uint32_t)h->entryPtr[idx].key;
+  tmp &= ~NVM3_KEY_MASK;
+  tmp |= key;
+  h->entryPtr[idx].key = (nvm3_ObjectKey_t)tmp;
+}
+
+static inline void entrySetGroup(nvm3_Cache_t *h, size_t idx, nvm3_ObjGroup_t group)
+{
+  uint32_t tmp = (uint32_t)h->entryPtr[idx].key;
+  tmp &= NVM3_KEY_MASK;
+  tmp |= (group << NVM3_KEY_SIZE);
+  h->entryPtr[idx].key = (nvm3_ObjectKey_t)tmp;
+}
+
+static inline void entrySetPtr(nvm3_Cache_t *h, size_t idx, nvm3_ObjPtr_t obj)
+{
+  h->entryPtr[idx].ptr = obj;
+}
+
+static inline void setInvalid(nvm3_Cache_t *h, size_t idx)
+{
+  h->entryPtr[idx].key = NVM3_KEY_INVALID;
+  h->entryPtr[idx].ptr = NVM3_OBJ_PTR_INVALID;
+}
+
+//****************************************************************************
+
+void nvm3_cacheOpen(nvm3_Cache_t *h, nvm3_CacheEntry_t *ptr, size_t count)
+{
+  h->entryPtr = ptr;
+  h->entryCount = count;
+  nvm3_cacheClear(h);
+}
+
+void nvm3_cacheClear(nvm3_Cache_t *h)
+{
+  nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheClear.\n");
+
+  for (size_t idx = 0; idx < h->entryCount; idx++) {
+    setInvalid(h, idx);
+  }
+  h->overflow = false;
+#if defined(NVM3_OPTIMIZATION) && (NVM3_OPTIMIZATION == 1)
+  h->usedCount = 0U;
+#endif
+}
+
+#if defined(NVM3_OPTIMIZATION) && (NVM3_OPTIMIZATION == 1)
+/******************************************************************************************************//**
+ * Find index of the key in cache using binary search.
+ *
+ * @param[in]  h      A pointer to NVM3 cache data.
+ *
+ * @param[in]  key    A 20-bit object identifier.
+ *
+ * @param[out] idx    A pointer to the location where key idx will be placed.
+ *
+ * @return            Returns SL_STATUS_OK on success or SL_STATUS_NOT_FOUND on failure.
+ *********************************************************************************************************/
+static sl_status_t cacheSearch(nvm3_Cache_t *h, nvm3_ObjectKey_t key, size_t *idx)
+{
+  if (h->usedCount <= 0U) {
+    return SL_STATUS_NOT_FOUND;
+  }
+
+  size_t low = 0U;
+  size_t high = h->usedCount - 1;
+  size_t mid = 0U;
+  while (low <= high) {
+    mid = (low + high) / 2;
+    if (entryGetKey(h, mid) == key) {
+      *idx = mid;
+      return SL_STATUS_OK;
+    }
+    if (entryGetKey(h, mid) < key) {
+      low = mid + 1;
+    } else {
+      if (mid != 0U) {
+        high = mid - 1;
+      } else {
+        return SL_STATUS_NOT_FOUND;
+      }
+    }
+  }
+  return SL_STATUS_NOT_FOUND;
+}
+
+/******************************************************************************************************//**
+ * Merge two cache subarrays. Merges the two haves arr[low..mid] and arr[mid+1..high] of cache subarrays.
+ *
+ * @param[in]  h       A pointer to NVM3 cache data.
+ *
+ * @param[in]  low     Left index of cache subarray.
+ *
+ * @param[in]  mid     Mid index of cache subarray.
+ *
+ * @param[in]  high    Right index of cache subarray.
+ *
+ * @return             Returns SL_STATUS_OK on success or SL_STATUS_ALLOCATION_FAILED on failure.
+ *********************************************************************************************************/
+static sl_status_t cacheMerge(nvm3_Cache_t *h, uint32_t low, uint32_t mid, uint32_t high)
+{
+  sl_status_t status = SL_STATUS_OK;
+
+  if ((low > mid) || (mid >= high)) {
+    return SL_STATUS_INVALID_PARAMETER;
+  }
+
+  uint32_t i, j, k;
+  uint32_t a1 = mid - low + 1;
+  uint32_t a2 = high - mid;
+
+  if ((L != NULL) && (H != NULL) && (P1 != NULL) && (P2 != NULL) && (K1 != NULL) && (K2 != NULL)) {
+    // Copy cache key and pointer data into subarrays
+    for (i = 0; i < a1; i++) {
+      L[i] = entryGetKey(h, low + i);
+      P1[i] = (uint32_t)h->entryPtr[low + i].ptr;
+      K1[i] = h->entryPtr[low + i].key;
+    }
+    for (j = 0; j < a2; j++) {
+      H[j] = entryGetKey(h, mid + 1 + j);
+      P2[j] = (uint32_t)h->entryPtr[mid + 1 + j].ptr;
+      K2[j] = h->entryPtr[mid + 1 + j].key;
+    }
+
+    // Index of first, second and merged subarrays
+    i = 0;
+    j = 0;
+    k = low;
+
+    // Merge cache subarrays
+    while (i < a1 && j < a2) {
+      if (L[i] <= H[j]) {
+        h->entryPtr[k].key = K1[i];
+        h->entryPtr[k].ptr = (uint32_t*)P1[i];
+        i++;
+      } else {
+        h->entryPtr[k].key = K2[j];
+        h->entryPtr[k].ptr = (uint32_t*)P2[j];
+        j++;
+      }
+      k++;
+    }
+
+    // Copy remaining cache elements of L subarray
+    while (i < a1) {
+      h->entryPtr[k].key = K1[i];
+      h->entryPtr[k].ptr = (uint32_t*)P1[i];
+      i++;
+      k++;
+    }
+
+    // Copy remaining cache elements of H subarray
+    while (j < a2) {
+      h->entryPtr[k].key = K2[j];
+      h->entryPtr[k].ptr = (uint32_t*)P2[j];
+      j++;
+      k++;
+    }
+  } else {
+    status = SL_STATUS_ALLOCATION_FAILED;
+  }
+
+  return status;
+}
+
+/******************************************************************************************************//**
+ * Sort cache entries using merge sort.
+ *
+ * @param[in]  h   A pointer to NVM3 cache data.
+ *
+ * @return         Returns SL_STATUS_OK on success or SL_STATUS_ALLOCATION_FAILED on failure.
+ *********************************************************************************************************/
+sl_status_t nvm3_cacheSort(nvm3_Cache_t *h)
+{
+  sl_status_t status = SL_STATUS_OK;
+  uint32_t cacheSize = h->usedCount;  // size of cache array
+  uint32_t currSize;                  // current size of subarray
+  uint32_t leftStart;                 // starting index of left subarray
+
+  // Allocate memory for cache subarrays
+  L = sl_malloc(cacheSize * sizeof(uint32_t));
+  H = sl_malloc(cacheSize * sizeof(uint32_t));
+  P1 = sl_malloc(cacheSize * sizeof(uint32_t));
+  P2 = sl_malloc(cacheSize * sizeof(uint32_t));
+  K1 = sl_malloc(cacheSize * sizeof(uint32_t));
+  K2 = sl_malloc(cacheSize * sizeof(uint32_t));
+
+  // Merge cache subarrays using bottom up approach.
+  for (currSize = 1; currSize <= cacheSize - 1; currSize = (currSize * 2U)) {
+    // Pick starting point of different subarrays of current size
+    for (leftStart = 0; leftStart < cacheSize - 1; leftStart += (currSize * 2U)) {
+      // Find ending point of left subarray. mid+1 is starting point of right
+      uint32_t mid = SL_MIN(leftStart + currSize - 1, cacheSize - 1);
+      uint32_t rightEnd = SL_MIN(leftStart + (2U * currSize - 1), cacheSize - 1);
+      // Merge cache subarrays arr[leftStart...mid] & arr[mid+1...rightEnd]
+      status = cacheMerge(h, leftStart, mid, rightEnd);
+    }
+  }
+
+  sl_free(L);
+  sl_free(H);
+  sl_free(K1);
+  sl_free(P1);
+  sl_free(K2);
+  sl_free(P2);
+
+  return status;
+}
+
+/******************************************************************************************************//**
+ * Update existing cache entry.
+ *
+ * @param[in]  h       A pointer to NVM3 cache data.
+ *
+ * @param[in]  key     A 20-bit object identifier.
+ *
+ * @param[in]  obj     A pointer to object struct.
+ *
+ * @param[in]  group   Object group.
+ *
+ * @return             Returns true on success or false on failure.
+ *********************************************************************************************************/
+bool nvm3_cacheUpdateEntry(nvm3_Cache_t *h, nvm3_ObjectKey_t key, nvm3_ObjPtr_t obj, nvm3_ObjGroup_t group)
+{
+  size_t idx = 0;
+  bool res = false;
+
+  if ((h->usedCount > 0U) && (h->usedCount <= h->entryCount)) {
+    if (cacheSearch(h, key, &idx) == SL_STATUS_OK) {
+      if (isValid(h, idx)) {
+        entrySetGroup(h, idx, group);
+        entrySetPtr(h, idx, obj);
+        res = true;
+      }
+    }
+  }
+  nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheUpdateEntry, key=%5u, grp=%u, obj=%p, idx=%u.\n", key, group, obj, idx);
+  return res;
+}
+
+/******************************************************************************************************//**
+ * Add new cache entry
+ *
+ * @param[in]  h       A pointer to NVM3 cache data.
+ *
+ * @param[in]  key     A 20-bit object identifier.
+ *
+ * @param[in]  obj     A pointer to object struct.
+ *
+ * @param[in]  group   Object type.
+ *
+ * @return             Returns SL_STATUS_OK on success or SL_STATUS_ALLOCATION_FAILED on failure.
+ *********************************************************************************************************/
+sl_status_t nvm3_cacheAddEntry(nvm3_Cache_t *h, nvm3_ObjectKey_t key, nvm3_ObjPtr_t obj, nvm3_ObjGroup_t group)
+{
+  sl_status_t status = SL_STATUS_OK;
+  bool cacheSet = false;
+
+  if (h->usedCount < h->entryCount) {
+    size_t idx = 0;
+    if (h->usedCount > 0U) {
+      if (nvm3_cacheGetIdx(h, key, 0U, h->usedCount - 1, &idx) == SL_STATUS_OK) {
+        nvm3_cacheOrganize(h, idx);
+      }
+    }
+    setInvalid(h, idx);
+    entrySetKey(h, idx, key);
+    entrySetGroup(h, idx, group);
+    entrySetPtr(h, idx, obj);
+    cacheSet = true;
+    h->usedCount++;
+    nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheAddEntry(1), key=%5u, grp=%u, obj=%p, idx=%u.\n", key, group, obj, idx);
+  }
+
+  // Prioritize data over deleted objects, force an overwrite if possible
+  if ((!cacheSet) && (group != objGroupDeleted)) {
+    for (size_t idx1 = 0; idx1 < h->entryCount; idx1++) {
+      nvm3_ObjGroup_t cacheGroup = entryGetGroup(h, idx1);
+      if (cacheGroup == objGroupDeleted) {
+        entrySetKey(h, idx1, key);
+        entrySetGroup(h, idx1, group);
+        entrySetPtr(h, idx1, obj);
+        cacheSet = true;
+        if (h->usedCount > 1U) {
+          status = nvm3_cacheSort(h);
+        }
+        nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheAddEntry(2), cache overflow for key=%u, grp=%u, obj=%p, inserted at idx=%u.\n", key, group, obj, idx1);
+        break;
+      }
+    }
+  }
+
+  if (!cacheSet) {
+    h->overflow = true;
+    nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheAddEntry(3), cache overflow for key=%u, grp=%u, obj=%p.\n", key, group, obj);
+  }
+
+  return status;
+}
+
+/******************************************************************************************************//**
+ * Get cache idx to add new entry
+ *
+ * @param[in]  h       A pointer to NVM3 cache data.
+ *
+ * @param[in]  key     A 20-bit object identifier.
+ *
+ * @param[in]  low     Left index of cache subarray.
+ *
+ * @param[in]  high    Right index of cache subarray.
+ *
+ * @param[out] idx     A pointer to the location where key idx will be placed.
+ *
+ * @return             Returns SL_STATUS_OK on success or SL_STATUS_NOT_FOUND on failure.
+ *********************************************************************************************************/
+sl_status_t nvm3_cacheGetIdx(nvm3_Cache_t *h, nvm3_ObjectKey_t key, size_t low, size_t high, size_t *idx)
+{
+  if (high <= low) {
+    *idx = (key > entryGetKey(h, low)) ? (low + 1) : low;
+    return SL_STATUS_OK;
+  }
+  if (key > entryGetKey(h, high)) {
+    *idx = high + 1;
+    return SL_STATUS_OK;
+  }
+  if (key < entryGetKey(h, low)) {
+    *idx = low;
+    return SL_STATUS_OK;
+  }
+  size_t mid = (low + high) / 2;
+  if (key == entryGetKey(h, mid)) {
+    *idx = mid + 1;
+    return SL_STATUS_OK;
+  }
+  if (key > entryGetKey(h, mid)) {
+    return nvm3_cacheGetIdx(h, key, mid + 1, high, idx);
+  }
+  if (mid != 0U) {
+    return nvm3_cacheGetIdx(h, key, low, mid - 1, idx);
+  } else {
+    return SL_STATUS_NOT_FOUND;
+  }
+}
+
+/******************************************************************************************************//**
+ * Arrange cache entries
+ *
+ * @param[in]  h       A pointer to NVM3 cache data.
+ *
+ * @param[in]  idx     Index of the key to arrange the cache entries.
+ *
+ *********************************************************************************************************/
+void nvm3_cacheOrganize(nvm3_Cache_t *h, size_t idx)
+{
+  size_t lastIdx = h->usedCount - 1;
+  // Move all cache entries from idx to end
+  for (; (lastIdx >= idx) && (lastIdx != 0); lastIdx--) {
+    h->entryPtr[lastIdx + 1].key = h->entryPtr[lastIdx].key;
+    h->entryPtr[lastIdx + 1].ptr = h->entryPtr[lastIdx].ptr;
+  }
+  if ((lastIdx == 0) && (idx == 0)) {
+    h->entryPtr[lastIdx + 1].key = h->entryPtr[lastIdx].key;
+    h->entryPtr[lastIdx + 1].ptr = h->entryPtr[lastIdx].ptr;
+  }
+}
+#endif
+
+#if defined(NVM3_OPTIMIZATION) && (NVM3_OPTIMIZATION == 1)
+void nvm3_cacheDelete(nvm3_Cache_t *h, nvm3_ObjectKey_t key)
+{
+  bool found = false;
+  size_t idx = 0;
+
+  if ((h->usedCount > 0U) && (h->usedCount <= h->entryCount)) {
+    if (cacheSearch(h, key, &idx) == SL_STATUS_OK) {
+      if (isValid(h, idx)) {
+        if (entryGetKey(h, idx) == key) {
+          setInvalid(h, idx);
+          found = true;
+          size_t lastIdx = h->usedCount - 1;
+          // Arrange cache entries after cache obj deletion
+          for (; idx < lastIdx; idx++) {
+            h->entryPtr[idx].key = h->entryPtr[idx + 1].key;
+            h->entryPtr[idx].ptr = h->entryPtr[idx + 1].ptr;
+          }
+          if (h->usedCount > 0) {
+            h->usedCount--;
+          }
+        }
+      }
+    }
+  }
+
+  nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheDelete, key=%u, found=%d.\n", key, found ? 1 : 0);
+  (void)found;
+}
+#else
+void nvm3_cacheDelete(nvm3_Cache_t *h, nvm3_ObjectKey_t key)
+{
+  bool found = false;
+
+  for (size_t idx = 0; idx < h->entryCount; idx++) {
+    if (isValid(h, idx)) {
+      if (entryGetKey(h, idx) == key) {
+        setInvalid(h, idx);
+        found = true;
+        break;
+      }
+    }
+  }
+
+  nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheDelete, key=%u, found=%d.\n", key, found ? 1 : 0);
+  (void)found;
+}
+#endif
+
+#if defined(NVM3_OPTIMIZATION) && (NVM3_OPTIMIZATION == 1)
+nvm3_ObjPtr_t nvm3_cacheGet(nvm3_Cache_t *h, nvm3_ObjectKey_t key, nvm3_ObjGroup_t *group)
+{
+  nvm3_ObjPtr_t obj = NVM3_OBJ_PTR_INVALID;
+#if NVM3_TRACE_PORT
+  int tmp = -1;
+#endif
+
+  size_t idx = 0;
+  if ((h->usedCount > 0U) && (h->usedCount <= h->entryCount)) {
+    if (cacheSearch(h, key, &idx) == SL_STATUS_OK) {
+      if (isValid(h, idx)) {
+        *group = entryGetGroup(h, idx);
+        obj = entryGetPtr(h, idx);
+#if NVM3_TRACE_PORT
+        tmp = (int)idx;
+#endif
+      }
+    }
+  }
+
+  nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheGet,    key=%5u, grp=%d, obj=%p, idx=%d.\n", key, (obj != NVM3_OBJ_PTR_INVALID) ? *group : -1, obj, tmp);
+
+  return obj;
+}
+#else
+nvm3_ObjPtr_t nvm3_cacheGet(nvm3_Cache_t *h, nvm3_ObjectKey_t key, nvm3_ObjGroup_t *group)
+{
+  nvm3_ObjPtr_t obj = NVM3_OBJ_PTR_INVALID;
+#if NVM3_TRACE_PORT
+  int tmp = -1;
+#endif
+
+  for (size_t idx = 0; idx < h->entryCount; idx++) {
+    if (isValid(h, idx)) {
+      if (entryGetKey(h, idx) == key) {
+        *group = entryGetGroup(h, idx);
+        obj = entryGetPtr(h, idx);
+#if NVM3_TRACE_PORT
+        tmp = (int)idx;
+#endif
+        break;
+      }
+    }
+  }
+
+  nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheGet,    key=%5u, grp=%d, obj=%p, idx=%d.\n", key, (obj != NVM3_OBJ_PTR_INVALID) ? *group : -1, obj, tmp);
+
+  return obj;
+}
+#endif
+
+#if defined(NVM3_OPTIMIZATION) && (NVM3_OPTIMIZATION == 1)
+SPEED_OPT
+void nvm3_cacheSet(nvm3_Cache_t *h, nvm3_ObjectKey_t key, nvm3_ObjPtr_t obj, nvm3_ObjGroup_t group)
+{
+  bool bSet = false;
+
+  // Update existing entry
+  size_t idx = 0;
+  if ((h->usedCount > 0U) && (h->usedCount <= h->entryCount)) {
+    for (idx = 0; idx < h->usedCount; idx++) {
+      if (isValid(h, idx)) {
+        if (entryGetKey(h, idx) == key) {
+          entrySetGroup(h, idx, group);
+          entrySetPtr(h, idx, obj);
+          nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheSet(1), key=%5u, grp=%u, obj=%p, idx=%u.\n", key, group, obj, idx);
+          return;
+        }
+      }
+    }
+  }
+
+  // Add new Entry
+  if (h->usedCount < h->entryCount) {
+    idx = h->usedCount;
+    if (!isValid(h, idx)) {
+      entrySetKey(h, idx, key);
+      entrySetGroup(h, idx, group);
+      entrySetPtr(h, idx, obj);
+      bSet = true;
+      h->usedCount++;
+      nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheSet(2), key=%5u, grp=%u, obj=%p, idx=%u.\n", key, group, obj, idx);
+    }
+  }
+
+  // Full, prioritize data over deleted objects, force an overwrite if possible
+  if ((!bSet) && (group != objGroupDeleted)) {
+    for (size_t idx1 = 0; idx1 < h->entryCount; idx1++) {
+      nvm3_ObjGroup_t cacheGroup = entryGetGroup(h, idx1);
+      if (cacheGroup == objGroupDeleted) {
+        entrySetKey(h, idx1, key);
+        entrySetGroup(h, idx1, group);
+        entrySetPtr(h, idx1, obj);
+        bSet = true;
+        nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheSet(3), cache overflow for key=%u, grp=%u, obj=%p, inserted at idx=%u.\n", key, group, obj, idx1);
+        break;
+      }
+    }
+  }
+
+  if (!bSet) {
+    h->overflow = true;
+    nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheSet(4), cache overflow for key=%u, grp=%u, obj=%p.\n", key, group, obj);
+  }
+}
+#else
+SPEED_OPT
+void nvm3_cacheSet(nvm3_Cache_t *h, nvm3_ObjectKey_t key, nvm3_ObjPtr_t obj, nvm3_ObjGroup_t group)
+{
+  bool bSet = false;
+
+  // Update existing entry
+  for (size_t idx = 0; idx < h->entryCount; idx++) {
+    if (isValid(h, idx)) {
+      if (entryGetKey(h, idx) == key) {
+        entrySetGroup(h, idx, group);
+        entrySetPtr(h, idx, obj);
+        nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheSet(1), key=%5u, grp=%u, obj=%p, idx=%u.\n", key, group, obj, idx);
+        return;
+      }
+    }
+  }
+
+  // Add new Entry
+  for (size_t idx = 0; idx < h->entryCount; idx++) {
+    if (!isValid(h, idx)) {
+      entrySetKey(h, idx, key);
+      entrySetGroup(h, idx, group);
+      entrySetPtr(h, idx, obj);
+      bSet = true;
+      nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheSet(2), key=%5u, grp=%u, obj=%p, idx=%u.\n", key, group, obj, idx);
+      break;
+    }
+  }
+
+  // Full, prioritize data over deleted objects, force an overwrite if possible
+  if ((!bSet) && (group != objGroupDeleted)) {
+    for (size_t idx = 0; idx < h->entryCount; idx++) {
+      nvm3_ObjGroup_t cacheGroup = entryGetGroup(h, idx);
+      if (cacheGroup == objGroupDeleted) {
+        entrySetKey(h, idx, key);
+        entrySetGroup(h, idx, group);
+        entrySetPtr(h, idx, obj);
+        bSet = true;
+        nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheSet(3), cache overflow for key=%u, grp=%u, obj=%p, inserted at idx=%u.\n", key, group, obj, idx);
+        break;
+      }
+    }
+  }
+
+  if (!bSet) {
+    h->overflow = true;
+    nvm3_tracePrint(TRACE_LEVEL, "      nvm3_cacheSet(4), cache overflow for key=%u, grp=%u, obj=%p.\n", key, group, obj);
+  }
+}
+#endif
+
+void nvm3_cacheScan(nvm3_Cache_t *h, nvm3_CacheScanCallback_t cacheScanCallback, void *user)
+{
+  bool keepGoing;
+  for (size_t idx = 0; idx < h->entryCount; idx++) {
+    if (isValid(h, idx)) {
+      // Found an object.
+      nvm3_ObjectKey_t key = entryGetKey(h, idx);
+      nvm3_ObjGroup_t group = entryGetGroup(h, idx);
+      nvm3_ObjPtr_t obj = entryGetPtr(h, idx);
+      keepGoing = cacheScanCallback(h, key, group, obj, user);
+      if (!keepGoing) {
+        return;
+      }
+    }
+  }
+}

Libs/platform/emdrv/nvm3/src/nvm3_default_common_linker.c

@@ -0,0 +1,100 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 definition of the default data structures.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include "nvm3.h"
+#include "nvm3_hal_flash.h"
+#include "nvm3_default_config.h"
+#if defined(NVM3_SECURITY)
+#include "nvm3_hal_crypto_handle.h"
+#endif
+
+#if defined(NVM3_BASE)
+/* Manually control the NVM3 address and size */
+
+#elif defined (__ICCARM__)
+
+__root __no_init uint8_t nvm3_default_storage[NVM3_DEFAULT_NVM_SIZE] @ "SIMEE";
+#define NVM3_BASE (nvm3_default_storage)
+
+#elif defined (__GNUC__)
+
+extern char linker_nvm_begin;
+
+__attribute__((used)) uint8_t nvm3_default_storage[NVM3_DEFAULT_NVM_SIZE] __attribute__ ((section(".simee")));
+#define NVM3_BASE (&linker_nvm_begin)
+
+#else
+#error "Unsupported toolchain"
+#endif
+
+nvm3_Handle_t  nvm3_defaultHandleData;
+nvm3_Handle_t *nvm3_defaultHandle = &nvm3_defaultHandleData;
+
+#if (NVM3_DEFAULT_CACHE_SIZE != 0)
+static nvm3_CacheEntry_t defaultCache[NVM3_DEFAULT_CACHE_SIZE];
+#endif
+
+// Compile time checks for NVM3 max object size macros
+#if NVM3_DEFAULT_MAX_OBJECT_SIZE > NVM3_MAX_OBJECT_SIZE_HIGH_LIMIT
+#error "NVM3_DEFAULT_MAX_OBJECT_SIZE is greater than max value supported"
+#elif NVM3_DEFAULT_MAX_OBJECT_SIZE < NVM3_MAX_OBJECT_SIZE_LOW_LIMIT
+#error "NVM3_DEFAULT_MAX_OBJECT_SIZE is less than min value supported"
+#endif
+
+nvm3_Init_t nvm3_defaultInitData =
+{
+  (nvm3_HalPtr_t)NVM3_BASE,
+  NVM3_DEFAULT_NVM_SIZE,
+#if (NVM3_DEFAULT_CACHE_SIZE != 0)
+  defaultCache,
+#else
+  NULL,
+#endif
+  NVM3_DEFAULT_CACHE_SIZE,
+  NVM3_DEFAULT_MAX_OBJECT_SIZE,
+  NVM3_DEFAULT_REPACK_HEADROOM,
+  &nvm3_halFlashHandle,
+#if defined(NVM3_SECURITY)
+  &nvm3_halCryptoHandle,
+  NVM3_DEFAULT_SECURITY_TYPE,
+#endif
+};
+
+nvm3_Init_t *nvm3_defaultInit = &nvm3_defaultInitData;
+
+sl_status_t nvm3_initDefault(void)
+{
+  return nvm3_open(nvm3_defaultHandle, nvm3_defaultInit);
+}
+
+sl_status_t nvm3_deinitDefault(void)
+{
+  return nvm3_close(nvm3_defaultHandle);
+}

Libs/platform/emdrv/nvm3/src/nvm3_hal_flash.c

@@ -0,0 +1,231 @@
+/***************************************************************************//**
+ * @file
+ * @brief Non-Volatile Memory Wear-Leveling driver HAL implementation
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include <stdbool.h>
+#include <string.h>
+#include "nvm3.h"
+#include "nvm3_hal_flash.h"
+#include "em_system.h"
+#include "em_msc.h"
+
+/***************************************************************************//**
+ * @addtogroup nvm3
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup nvm3hal
+ * @{
+ ******************************************************************************/
+
+/******************************************************************************
+ ******************************    MACROS    **********************************
+ *****************************************************************************/
+
+#define CHECK_DATA  1           ///< Macro defining if data should be checked
+
+/******************************************************************************
+ ***************************   LOCAL VARIABLES   ******************************
+ *****************************************************************************/
+
+/******************************************************************************
+ ***************************   LOCAL FUNCTIONS   ******************************
+ *****************************************************************************/
+
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+
+/***************************************************************************//**
+ * @brief
+ *   Convert return type.
+ *
+ * @details
+ *   This function converts between the return type of the emlib and the
+ *   NVM3 API.
+ *
+ * @param[in] result
+ *   Operation result.
+ *
+ * @return
+ *   Returns remapped status code.
+ ******************************************************************************/
+static sl_status_t convertMscStatusToNvm3Status(MSC_Status_TypeDef result)
+{
+  sl_status_t ret;
+
+  switch (result) {
+    case mscReturnOk:
+      ret = SL_STATUS_OK;
+      break;
+    case mscReturnInvalidAddr:
+      ret = SL_STATUS_NVM3_INVALID_ADDR;
+      break;
+    default:
+      ret = SL_STATUS_NVM3_EMULATOR;
+      break;
+  }
+
+  return ret;
+}
+
+// Check if the page is erased.
+static bool isErased(void *adr, size_t len)
+{
+  size_t i;
+  size_t cnt;
+  uint32_t *dat = adr;
+
+  cnt = len / sizeof(uint32_t);
+  for (i = 0U; i < cnt; i++) {
+    if (*dat != 0xFFFFFFFFUL) {
+      return false;
+    }
+    dat++;
+  }
+
+  return true;
+}
+
+/** @endcond */
+
+static sl_status_t nvm3_halFlashOpen(nvm3_HalPtr_t nvmAdr, size_t flashSize)
+{
+  (void)nvmAdr;
+  (void)flashSize;
+  MSC_Init();
+
+  return SL_STATUS_OK;
+}
+
+static void nvm3_halFlashClose(void)
+{
+  MSC_Deinit();
+}
+
+static sl_status_t nvm3_halFlashGetInfo(nvm3_HalInfo_t *halInfo)
+{
+  SYSTEM_ChipRevision_TypeDef chipRev;
+
+  SYSTEM_ChipRevisionGet(&chipRev);
+#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK)
+  halInfo->deviceFamilyPartNumber = chipRev.partNumber;
+#else
+  halInfo->deviceFamilyPartNumber = chipRev.family;
+#endif
+  halInfo->memoryMapped = 1;
+#if defined(_SILICON_LABS_32B_SERIES_2)
+  halInfo->writeSize = NVM3_HAL_WRITE_SIZE_32;
+#else
+  halInfo->writeSize = NVM3_HAL_WRITE_SIZE_16;
+#endif
+  halInfo->pageSize = SYSTEM_GetFlashPageSize();
+
+  return SL_STATUS_OK;
+}
+
+static void nvm3_halFlashAccess(nvm3_HalNvmAccessCode_t access)
+{
+  (void)access;
+}
+
+static sl_status_t nvm3_halFlashReadWords(nvm3_HalPtr_t nvmAdr, void *dst, size_t wordCnt)
+{
+  uint32_t *pSrc = (uint32_t *)nvmAdr;
+  uint32_t *pDst = dst;
+
+  if ((((size_t)pSrc % 4) == 0) && (((size_t)pDst % 4) == 0)) {
+    while (wordCnt > 0U) {
+      *pDst++ = *pSrc++;
+      wordCnt--;
+    }
+  } else {
+    (void)memcpy(dst, nvmAdr, wordCnt * sizeof(uint32_t));
+  }
+
+  return SL_STATUS_OK;
+}
+
+static sl_status_t nvm3_halFlashWriteWords(nvm3_HalPtr_t nvmAdr, void const *src, size_t wordCnt)
+{
+  const uint32_t *pSrc = src;
+  uint32_t *pDst = (uint32_t *)nvmAdr;
+  MSC_Status_TypeDef mscSta;
+  sl_status_t halSta;
+  size_t byteCnt;
+
+  byteCnt = wordCnt * sizeof(uint32_t);
+  mscSta = MSC_WriteWord(pDst, pSrc, byteCnt);
+  halSta = convertMscStatusToNvm3Status(mscSta);
+
+#if CHECK_DATA
+  if (halSta == SL_STATUS_OK) {
+    if (memcmp(pDst, pSrc, byteCnt) != 0) {
+      halSta = SL_STATUS_FLASH_PROGRAM_FAILED;
+    }
+  }
+#endif
+
+  return halSta;
+}
+
+static sl_status_t nvm3_halFlashPageErase(nvm3_HalPtr_t nvmAdr)
+{
+  MSC_Status_TypeDef mscSta;
+  sl_status_t halSta;
+
+  mscSta = MSC_ErasePage((uint32_t *)nvmAdr);
+  halSta = convertMscStatusToNvm3Status(mscSta);
+
+#if CHECK_DATA
+  if (halSta == SL_STATUS_OK) {
+    if (!isErased(nvmAdr, SYSTEM_GetFlashPageSize())) {
+      halSta = SL_STATUS_FLASH_ERASE_FAILED;
+    }
+  }
+#endif
+
+  return halSta;
+}
+
+/*******************************************************************************
+ ***************************   GLOBAL VARIABLES   ******************************
+ ******************************************************************************/
+
+const nvm3_HalHandle_t nvm3_halFlashHandle = {
+  .open = nvm3_halFlashOpen,                    ///< Set the open function
+  .close = nvm3_halFlashClose,                  ///< Set the close function
+  .getInfo = nvm3_halFlashGetInfo,              ///< Set the get-info function
+  .access = nvm3_halFlashAccess,                ///< Set the access function
+  .pageErase = nvm3_halFlashPageErase,          ///< Set the page-erase function
+  .readWords = nvm3_halFlashReadWords,          ///< Set the read-words function
+  .writeWords = nvm3_halFlashWriteWords,        ///< Set the write-words function
+};
+
+/** @} (end addtogroup nvm3hal) */
+/** @} (end addtogroup nvm3) */

Libs/platform/emdrv/nvm3/src/nvm3_lock.c

@@ -0,0 +1,207 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 data access lock API implementation
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include "nvm3_lock.h"
+#include "nvm3.h"
+
+#ifdef NVM3_HOST_BUILD
+#include "nvm3_config.h"
+#include "nvm3_trace.h"
+#include "nvm3_hal.h"
+#else
+#include "sl_core.h"
+#endif
+
+#if defined(SL_COMPONENT_CATALOG_PRESENT)
+#include "sl_component_catalog.h"
+#endif
+
+#if defined(SL_CATALOG_MPU_PRESENT)
+#include "sl_mpu.h"
+#endif
+
+#if defined(SL_CATALOG_KERNEL_PRESENT)
+#include "cmsis_os2.h"
+#endif
+
+//****************************************************************************
+
+#ifdef NVM3_HOST_BUILD
+#define SL_WEAK
+#endif
+
+#ifdef NVM3_HOST_BUILD
+static int lockCount = 0;
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+#elif defined(SL_CATALOG_KERNEL_PRESENT) && !defined(_SILICON_LABS_32B_SERIES_2)
+static osMutexId_t nvm3_mutex;   ///< NVM3 Lock Mutex
+#define NVM3_ERROR_ASSERT()   do { EFM_ASSERT(false); } while (0)
+#else
+CORE_DECLARE_IRQ_STATE;
+/// @endcond
+#endif
+
+/***************************************************************************//**
+ * @addtogroup nvm3
+ * @{
+ ******************************************************************************/
+
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+nvm3_Obj_t nvm3_internalObjectHandleA;
+nvm3_Obj_t nvm3_internalObjectHandleB;
+nvm3_Obj_t nvm3_internalObjectHandleC;
+nvm3_Obj_t nvm3_internalObjectHandleD;
+#if defined(NVM3_SECURITY)
+nvm3_Obj_t nvm3_internalObjectHandleE;
+#endif
+const uint8_t nvm3_maxFragmentCount = NVM3_FRAGMENT_COUNT;
+const size_t  nvm3_objHandleSize = sizeof(nvm3_Obj_t);
+
+/// @endcond
+
+/***************************************************************************//**
+ * @addtogroup nvm3lock
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @details
+ * The Mutex creation for lock enable and disable.
+ *
+ * It provides options for using "mutexes" for RTOS users
+ * and "core_critical" APIs for bare-metal users.
+ *
+ * @note RTOS users should avoid invoking the nvm3_lock APIs from within
+ *       critical sections, as this may result in unexpected behavior.
+ *       Please, ensure that kernel has been initialized before this API call.
+ ******************************************************************************/
+SL_WEAK void nvm3_lockCreateMutex(void)
+{
+#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(_SILICON_LABS_32B_SERIES_2)
+  if (nvm3_mutex == NULL) {
+    const osMutexAttr_t mutex_attr = {
+      " NVM3 Mutex",
+      osMutexRecursive | osMutexPrioInherit,
+      NULL,
+      0
+    };
+    nvm3_mutex = osMutexNew(&mutex_attr);
+    if (nvm3_mutex == NULL) {
+      NVM3_ERROR_ASSERT();
+    }
+  }
+#endif
+}
+
+/***************************************************************************//**
+ * @details
+ * The default lock-begin implementation.
+ * @note RTOS users should avoid invoking the nvm3_lock APIs from within
+ *       critical sections, as this may result in unexpected behavior.
+ *       Please, ensure that kernel has been initialized before this API call.
+ ******************************************************************************/
+SL_WEAK void nvm3_lockBegin(void)
+{
+#ifdef NVM3_HOST_BUILD
+  lockCount++;
+// In apps running on micrium OS on Ser2, the app is acquiring the mutex within
+// a critical section while invoking bootloader APIs
+#elif defined(SL_CATALOG_KERNEL_PRESENT) && !defined(_SILICON_LABS_32B_SERIES_2)
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+  osStatus_t os_status = osError;
+  // Bypass the lock if kernel is not running
+  if (osKernelGetState() == osKernelRunning) {
+    if (nvm3_mutex == NULL) {
+      nvm3_lockCreateMutex();
+    }
+    os_status = osMutexAcquire(nvm3_mutex, osWaitForever);
+    if (os_status != osErrorISR && os_status != osOK) {
+      NVM3_ERROR_ASSERT();
+    }
+  }
+#else
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+  CORE_ENTER_CRITICAL();
+/// @endcond
+#endif
+}
+
+/***************************************************************************//**
+ * @details
+ * The default lock-end implementation.
+ * @note RTOS users should avoid invoking the nvm3_lock APIs from within
+ *       critical sections, as this may result in unexpected behavior.
+ *       Please, ensure that kernel has been initialized before this API call.
+ ******************************************************************************/
+SL_WEAK void nvm3_lockEnd(void)
+{
+#ifdef NVM3_HOST_BUILD
+  if (lockCount == 0) {
+    nvm3_tracePrint(NVM3_TRACE_LEVEL_ERROR, "NVM3 ERROR - lockEnd: invalid lock count.\n");
+  }
+  lockCount--;
+#elif defined(SL_CATALOG_KERNEL_PRESENT) && !defined(_SILICON_LABS_32B_SERIES_2)
+  osStatus_t os_status = osError;
+  // Bypass the lock if kernel is not running
+  if (osKernelGetState() == osKernelRunning) {
+    os_status = osMutexRelease(nvm3_mutex);
+    if (os_status != osErrorISR && os_status != osOK) {
+      NVM3_ERROR_ASSERT();
+    }
+  }
+#else
+  CORE_EXIT_CRITICAL();
+#endif
+}
+
+/***************************************************************************//**
+ * @details
+ *  Disable execution from data area.
+ *
+ * @param[in]  address Start of memory range
+ *
+ * @param[in]  size Size of memory range.
+ ******************************************************************************/
+void nvm3_lockDisableExecute(void *address, size_t size)
+{
+#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) \
+  && defined(SL_CATALOG_MPU_PRESENT)                \
+  && !defined(SL_TRUSTZONE_SECURE)
+  // The memory range used by nvm3 may not be compatible with the mpu.
+  // Just ignore errors.
+  sl_mpu_disable_execute((uint32_t)address, (uint32_t)address + size - 1, size);
+#else
+  (void)address;
+  (void)size;
+#endif
+}
+
+/** @} (end addtogroup nvm3lock) */
+/** @} (end addtogroup nvm3) */

Libs/platform/emdrv/nvm3/src/nvm3_object.c

@@ -0,0 +1,267 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 object handling functions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include "nvm3_object.h"
+#include "nvm3_utils.h"
+#include <string.h>
+
+#define NVM3_OBJ_LEN_SIZE                7U          //  7 bits
+#define NVM3_OBJ_LEN_MASK                ((1U << NVM3_OBJ_LEN_SIZE) - 1U)
+#define NVM3_OBJ_LLEN_SIZE               26U         // 26 bits: large obj length
+#define NVM3_OBJ_LLEN_MASK               ((1U << NVM3_OBJ_LLEN_SIZE) - 1U)
+#define NVM3_OBJ_BCCB_SIZE               5U          //  5 bits: small obj berger code
+#define NVM3_OBJ_BCCB_MASK               ((1U << NVM3_OBJ_BCCB_SIZE) - 1U)
+#define NVM3_OBJ_LBCCB_SIZE              6U          //  6 bits: large obj berger code
+#define NVM3_OBJ_LBCCB_MASK              ((1U << NVM3_OBJ_LBCCB_SIZE) - 1U)
+#define NVM3_OBJ_F_SIZE                  2U          //  2 bits: fragment field
+#define NVM3_OBJ_F_MASK                  ((1U << NVM3_OBJ_F_SIZE) - 1U)
+#define NVM3_OBJ_U_SIZE                  3U          //  3 bits: unused field
+#define NVM3_OBJ_U_MASK                  ((1U << NVM3_OBJ_U_SIZE) - 1U)
+#define NVM3_OBJ_KEY_OFFSET              (NVM3_OBJ_LEN_SIZE)
+#define NVM3_OBJ_F_OFFSET                (NVM3_OBJ_LEN_SIZE + NVM3_KEY_SIZE)
+#define NVM3_OBJ_U_OFFSET                (NVM3_OBJ_LEN_SIZE + NVM3_KEY_SIZE + NVM3_OBJ_F_SIZE)
+#define NVM3_OBJ_BCCB_OFFSET             (NVM3_OBJ_LEN_SIZE + NVM3_KEY_SIZE)
+#define NVM3_OBJ_LBCCB_OFFSET            (NVM3_OBJ_LLEN_SIZE)
+
+//****************************************************************************
+
+__STATIC_INLINE uint32_t hdrSmallGetBergerCode(nvm3_ObjHdrSmall_t *oh)
+{
+  return (((oh)->oh1 >> NVM3_OBJ_BCCB_OFFSET) & NVM3_OBJ_BCCB_MASK);
+}
+
+__STATIC_INLINE uint32_t hdrLargeGetBergerCode(nvm3_ObjHdrLarge_t *oh)
+{
+  return (((oh)->oh2 >> NVM3_OBJ_LBCCB_OFFSET) & NVM3_OBJ_LBCCB_MASK);
+}
+
+__STATIC_INLINE nvm3_ObjType_t toObjType(uint32_t value)
+{
+  int type = (int)value;
+  return (nvm3_ObjType_t)type;
+}
+
+__STATIC_INLINE nvm3_ObjFragType_t toObjFragType(uint32_t value)
+{
+  int type = (int)value;
+  return (nvm3_ObjFragType_t)type;
+}
+
+__STATIC_INLINE nvm3_ObjType_t hdrGetType(nvm3_ObjHdrSmall_t *oh)
+{
+  return toObjType(oh->oh1 & NVM3_OBJ_LEN_MASK);
+}
+
+__STATIC_INLINE bool hdrIsLarge(nvm3_ObjHdrSmall_t *oh)
+{
+  nvm3_ObjType_t objTyp = hdrGetType(oh);
+  return ((objTyp == objTypeCounterLarge) || (objTyp == objTypeDataLarge));
+}
+
+//****************************************************************************
+
+/*** Initialize object header */
+size_t nvm3_objHdrInit(nvm3_ObjHdrLargePtr_t oh, nvm3_ObjectKey_t key, nvm3_ObjType_t objType,
+                       size_t len, bool isLarge, nvm3_ObjFragType_t fragTyp)
+{
+  uint8_t BCCB = 0;
+
+  oh->oh1 = (key & NVM3_KEY_MASK) << NVM3_OBJ_KEY_OFFSET;
+  oh->oh2 = (len & NVM3_OBJ_LLEN_MASK);
+  switch (objType) {
+    case objTypeCounterLarge:
+    /* Intented fall-through */
+    case objTypeDataLarge:
+      oh->oh1 |= (uint32_t)objType;
+      oh->oh1 |= ((uint32_t)NVM3_OBJ_U_MASK << NVM3_OBJ_U_OFFSET);
+      oh->oh1 |= ((uint32_t)fragTyp & NVM3_OBJ_F_MASK) << NVM3_OBJ_F_OFFSET;
+      break;
+    case objTypeCounterSmall:
+    /* Intented fall-through*/
+    case objTypeDeleted:
+      oh->oh1 |= (uint32_t)objType;
+      break;
+    default:
+      oh->oh1 |= ((len + (uint32_t)objTypeDataSmall) & NVM3_OBJ_LEN_MASK);
+      break;
+  }
+  if (isLarge) {
+    nvm3_utilsComputeBergerCode(&BCCB, &oh->oh1, 32);
+    nvm3_utilsComputeBergerCode(&BCCB, &oh->oh2, NVM3_OBJ_LLEN_SIZE);
+    oh->oh2 |= ((uint32_t)BCCB & NVM3_OBJ_LBCCB_MASK) << NVM3_OBJ_LBCCB_OFFSET;
+  } else {
+    nvm3_utilsComputeBergerCode(&BCCB, &oh->oh1, (uint8_t)(NVM3_OBJ_LEN_SIZE + NVM3_KEY_SIZE));
+    oh->oh1 |= ((uint32_t)BCCB & NVM3_OBJ_BCCB_MASK) << NVM3_OBJ_BCCB_OFFSET;
+  }
+
+  return nvm3_objHdrLen(isLarge);
+}
+
+size_t nvm3_objHdrLen(bool isLarge)
+{
+  return isLarge ? NVM3_OBJ_HEADER_SIZE_LARGE : NVM3_OBJ_HEADER_SIZE_SMALL;
+}
+
+bool nvm3_objHdrValidateSmall(nvm3_ObjHdrSmallPtr_t objHdrSmall)
+{
+  uint8_t codReq = 0;
+  uint8_t codAct;
+  bool res = false;
+
+  nvm3_utilsComputeBergerCode(&codReq, &objHdrSmall->oh1, (uint8_t)(NVM3_OBJ_LEN_SIZE + NVM3_KEY_SIZE));
+  codAct = (uint8_t)hdrSmallGetBergerCode(objHdrSmall);
+  if (codReq == codAct) {
+    res = true;
+  }
+
+  return res;
+}
+
+bool nvm3_objHdrValidateLarge(nvm3_ObjHdrLargePtr_t objHdrLarge)
+{
+  uint8_t codReq = 0;
+  uint8_t codAct;
+  bool res = false;
+
+  nvm3_utilsComputeBergerCode(&codReq, &objHdrLarge->oh1, 32);
+  nvm3_utilsComputeBergerCode(&codReq, &objHdrLarge->oh2, NVM3_OBJ_LLEN_SIZE);
+  codAct = (uint8_t)hdrLargeGetBergerCode(objHdrLarge);
+  if (codReq == codAct) {
+    res = true;
+  }
+
+  return res;
+}
+
+bool nvm3_objHdrGetErased(nvm3_ObjHdrSmallPtr_t objHdrSmall)
+{
+  return objHdrSmall->oh1 == 0xFFFFFFFFU;
+}
+
+nvm3_ObjFragType_t nvm3_objHdrGetFragTyp(nvm3_ObjHdrSmallPtr_t objHdrSmall)
+{
+  nvm3_ObjFragType_t fragTyp = toObjFragType((objHdrSmall->oh1 >> NVM3_OBJ_F_OFFSET) & NVM3_OBJ_F_MASK);
+
+  return hdrIsLarge(objHdrSmall) ? fragTyp : fragTypeNone;
+}
+
+nvm3_ObjectKey_t nvm3_objHdrGetKey(nvm3_ObjHdrSmallPtr_t objHdrSmall)
+{
+  return (nvm3_ObjectKey_t)((objHdrSmall->oh1 >> NVM3_OBJ_KEY_OFFSET) & NVM3_KEY_MASK);
+}
+
+bool nvm3_objHdrGetHdrIsLarge(nvm3_ObjHdrSmallPtr_t objHdrSmall)
+{
+  return hdrIsLarge(objHdrSmall);
+}
+
+size_t nvm3_objHdrGetHdrLen(nvm3_ObjHdrSmallPtr_t objHdrSmall)
+{
+  return nvm3_objHdrLen(hdrIsLarge(objHdrSmall));
+}
+
+size_t nvm3_objHdrGetDatLen(nvm3_ObjHdrLargePtr_t objHdrLarge)
+{
+  size_t len;
+
+  if (hdrIsLarge((nvm3_ObjHdrSmallPtr_t)objHdrLarge)) {
+    len = objHdrLarge->oh2 & NVM3_OBJ_LLEN_MASK;
+  } else {
+    len = objHdrLarge->oh1 & NVM3_OBJ_LEN_MASK;
+    len = (len > (size_t)objTypeDataSmall) ? (len - (size_t)objTypeDataSmall) : 0U;
+  }
+
+  return len;
+}
+
+nvm3_ObjType_t nvm3_objHdrGetType(nvm3_ObjHdrSmallPtr_t objHdrSmall)
+{
+  return hdrGetType(objHdrSmall);
+}
+
+void nvm3_objInit(nvm3_ObjPtr_t obj, nvm3_ObjPtr_t objAdr)
+{
+  // The sizeof(nvm3_Obj_t) is dependent on the page size.
+  (void)memset(obj, 0, nvm3_objHandleSize);
+  obj->key = NVM3_KEY_INVALID;
+  obj->objAdr = objAdr;
+  obj->isValid = false;
+  obj->totalLen = 0;
+  obj->nextObjAdr = NVM3_OBJ_PTR_INVALID;
+  obj->isFragmented = false;
+  obj->frag.isFirstFragFound = false;
+  obj->frag.isLastFragFound = false;
+  obj->frag.idx = 0;
+}
+
+nvm3_ObjType_t nvm3_objGroupToType(nvm3_ObjGroup_t objGroup, bool hdrIsLarge)
+{
+  nvm3_ObjType_t objType;
+
+  if (objGroup == objGroupDeleted) {
+    objType = objTypeDeleted;
+  } else if (objGroup == objGroupCounter) {
+    objType = hdrIsLarge ? objTypeCounterLarge : objTypeCounterSmall;
+  } else {
+    objType = hdrIsLarge ? objTypeDataLarge : objTypeDataSmall;
+  }
+
+  return objType;
+}
+
+nvm3_ObjGroup_t nvm3_objTypeToGroup(nvm3_ObjType_t objType)
+{
+  nvm3_ObjGroup_t objGroup;
+
+  switch (objType) {
+    case objTypeCounterSmall:
+      objGroup = objGroupCounter;
+      break;
+    case objTypeCounterLarge:
+      objGroup = objGroupCounter;
+      break;
+    case objTypeDataLarge:
+      objGroup = objGroupData;
+      break;
+    case objTypeRes_1:
+    case objTypeRes_2:
+    case objTypeRes_3:
+      objGroup = objGroupUnknown;
+      break;
+    case objTypeDeleted:
+      objGroup = objGroupDeleted;
+      break;
+    default:
+      objGroup = objGroupData;
+      break;
+  }
+
+  return objGroup;
+}

Libs/platform/emdrv/nvm3/src/nvm3_page.c

@@ -0,0 +1,375 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 page handling functions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <string.h>
+#include "nvm3_page.h"
+#include "nvm3_object.h"
+#include "nvm3_utils.h"
+#include "nvm3_trace.h"
+
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+
+//============================================================================
+
+#define H1_MAGIC_SHIFT          16          // The magic shift
+#define H1_MAGIC_V1             0xB29AU     // The magic marker
+#define H1_VERSION_V1           0x01U       // The first version of NVM3
+#define H4_BAD_MASK             0xffff0000U // The BAD mask
+#define H4_BAD_SHIFT            16          // The BAD shift
+#define H4_BAD_GOOD             0xFFFFU     // The page is good
+#define H4_BAD_NOTGOOD          0x0000U     // The page is not good
+#define H4_EIP_MASK             0xffffU     // The EIP mask
+#define H4_EIP_SET              0xA5A5U     // The page is scheduled for erase
+#define H4_EIP_CLEAR            0xFFFFU     // The page is not sceduled for erase
+#define H5_DEVICE_FAMILY_MASK   0x07FFU
+#define H5_WRITESIZE_SHIFT      11
+#define H5_WRITESIZE_MASK       0x0800U
+#define H5_MEMORYMAPPED_SHIFT   12
+#define H5_MEMORYMAPPED_MASK    0x1000U
+#define H5_PAGESIZE_SHIFT       13
+#define H5_PAGESIZE_MASK        0xE000U
+#define H5_DEVINFO_MASK         (H5_DEVICE_FAMILY_MASK | H5_WRITESIZE_MASK | H5_MEMORYMAPPED_MASK | H5_PAGESIZE_MASK)
+#if defined(NVM3_SECURITY)
+#define H5_SECTYPE_AEAD_SHIFT   16          // The AEAD shift
+#define H5_SECTYPE_AEAD_MASK    0x10000U    // The AEAD mask
+#define H5_SECTYPE_ENC_SHIFT    17          // The encryption shift
+#define H5_SECTYPE_ENC_MASK     0x20000U    // The encryption mask
+#endif
+
+//============================================================================
+
+typedef enum {
+  eraseCntNormal,
+  eraseCntInverted
+} EraseCnt_t;
+
+//============================================================================
+
+__STATIC_INLINE bool pageHdrErased(nvm3_PageHdr_t *pageHdr)
+{
+  return (pageHdr->data[0] == 0xFFFFFFFFU);
+}
+
+__STATIC_INLINE bool pageHdrMagicAndVersion(nvm3_PageHdr_t *pageHdr)
+{
+  uint16_t magic, version;
+
+  magic = (uint16_t)(pageHdr->data[0] >> H1_MAGIC_SHIFT);
+  version = (uint16_t)pageHdr->data[0];
+  return (magic == H1_MAGIC_V1) && (version == H1_VERSION_V1);
+}
+
+__STATIC_INLINE bool pageHdrIsPageBad(nvm3_PageHdr_t *pageHdr)
+{
+  uint32_t badPage = (pageHdr->data[3] & H4_BAD_MASK) >> H4_BAD_SHIFT;
+
+  return badPage != H4_BAD_GOOD;
+}
+
+__STATIC_INLINE bool pageHdrIsEraseInProgress(nvm3_PageHdr_t *pageHdr)
+{
+  uint16_t EIP = (pageHdr->data[3]);
+
+  return EIP != H4_EIP_CLEAR;
+}
+
+__STATIC_INLINE uint32_t pageHdrGetCounterBcod(uint32_t h)
+{
+  return (h >> NVM3_PAGE_COUNTER_SIZE) & NVM3_PAGE_BCCB_MASK;
+}
+
+__STATIC_INLINE uint32_t pageHdrGetCounterVal(uint32_t h, EraseCnt_t level)
+{
+  uint32_t cnt = (level == eraseCntInverted) ? ~h : h;
+  return cnt & NVM3_PAGE_COUNTER_MASK;
+}
+
+__STATIC_INLINE uint32_t pageHdrCounterMake(uint32_t cnt, EraseCnt_t level)
+{
+  uint8_t  BCCB;
+
+  if (level == eraseCntInverted) {
+    cnt = ~cnt;
+  }
+  cnt &= NVM3_PAGE_COUNTER_MASK;
+  BCCB = 0;
+  nvm3_utilsComputeBergerCode(&BCCB, &cnt, NVM3_PAGE_COUNTER_SIZE);
+  return ((uint32_t)BCCB << NVM3_PAGE_COUNTER_SIZE) | cnt;
+}
+
+// The page size field has a value from 0 to 7 describing page sizes from 512
+// to 65536 bytes. Note: The page size must be a power of 2.
+static uint16_t pageSizeToField(size_t pageSize)
+{
+  uint16_t field = 0U;
+
+  pageSize /= 512U;
+  for (;; ) {
+    pageSize /= 2U;
+    if (pageSize == 0U) {
+      break;
+    }
+    field++;
+  }
+
+  return field;
+}
+
+//============================================================================
+#if defined(NVM3_SECURITY)
+sl_status_t nvm3_pageHeaderWrite(const nvm3_HalHandle_t *hal, nvm3_HalPtr_t pageAdr, uint32_t eraseCnt, nvm3_HalInfo_t *halInfo, nvm3_SecurityType_t secType)
+#else
+sl_status_t nvm3_pageHeaderWrite(const nvm3_HalHandle_t *hal, nvm3_HalPtr_t pageAdr, uint32_t eraseCnt, nvm3_HalInfo_t *halInfo)
+#endif
+{
+  nvm3_PageHdr_t pageHdr;
+  uint32_t devInfo;
+  uint32_t formatInfo;
+  size_t ofs;
+  nvm3_HalPtr_t adr;
+  sl_status_t staWrite;
+  sl_status_t sta = SL_STATUS_OK;
+
+  // Create header
+  devInfo = ((pageSizeToField(halInfo->pageSize) << H5_PAGESIZE_SHIFT) & H5_PAGESIZE_MASK)
+            + (((halInfo->memoryMapped) << H5_MEMORYMAPPED_SHIFT) & H5_MEMORYMAPPED_MASK)
+            + (((halInfo->writeSize) << H5_WRITESIZE_SHIFT) & H5_WRITESIZE_MASK)
+            + ((halInfo->deviceFamilyPartNumber) & H5_DEVICE_FAMILY_MASK);
+#if defined(NVM3_SECURITY)
+  formatInfo = ((secType == NVM3_SECURITY_AEAD) ? 0 : 1) + 0xFFFEU;
+#else
+  formatInfo = 0xFFFFU;
+#endif
+  pageHdr.data[0] = (H1_MAGIC_V1 << H1_MAGIC_SHIFT) | H1_VERSION_V1;
+  pageHdr.data[1] = pageHdrCounterMake(eraseCnt, eraseCntNormal);
+  pageHdr.data[2] = pageHdrCounterMake(eraseCnt, eraseCntInverted);
+  pageHdr.data[3] = 0xffffffffU;
+  pageHdr.data[4] = (formatInfo << 16) | (devInfo);
+  //printf("-> hdrWr: adr=%p, cnt=%u, 1=0x%08x, 2=0x%08x\n", pageAdr, eraseCnt, pageHdr.data[1], pageHdr.data[2]);
+
+  // Write header in the following order: H5 -> H3 -> H2 -> H1
+  // Write H5
+  ofs = 4 * sizeof(uint32_t);
+  adr = (nvm3_HalPtr_t)((size_t)pageAdr + ofs);
+  staWrite = nvm3_halWriteWords(hal, adr, &(pageHdr.data[4]), 1);
+  if (staWrite != SL_STATUS_OK) {
+    sta = staWrite;
+  }
+
+  // Write H4
+  // Do not write 0xffffffff
+
+  // Write H3
+  ofs = 2 * sizeof(uint32_t);
+  adr = (nvm3_HalPtr_t)((size_t)pageAdr + ofs);
+  staWrite = nvm3_halWriteWords(hal, adr, &(pageHdr.data[2]), 1);
+  if (staWrite != SL_STATUS_OK) {
+    sta = staWrite;
+  }
+
+  // Write H2
+  ofs = 1 * sizeof(uint32_t);
+  adr = (nvm3_HalPtr_t)((size_t)pageAdr + ofs);
+  staWrite = nvm3_halWriteWords(hal, adr, &(pageHdr.data[1]), 1);
+  if (staWrite != SL_STATUS_OK) {
+    sta = staWrite;
+  }
+
+  // Write H1
+  ofs = 0;
+  adr = (nvm3_HalPtr_t)((size_t)pageAdr + ofs);
+  staWrite = nvm3_halWriteWords(hal, adr, &(pageHdr.data[0]), 1);
+  if (staWrite != SL_STATUS_OK) {
+    sta = staWrite;
+  }
+
+  return sta;
+}
+
+/*** Mark page as bad page */
+void nvm3_pageSetBad(const nvm3_HalHandle_t *hal, nvm3_HalPtr_t pageAdr)
+{
+  uint32_t  h4Rd;
+  uint32_t  h4Wr;
+  nvm3_HalPtr_t adr;
+
+  nvm3_tracePrint(NVM3_TRACE_LEVEL_WARNING, "nvm3_pageSetBad, pageAdr=0x%p.\n", pageAdr);
+
+  adr = (nvm3_HalPtr_t)((size_t)pageAdr + NVM3_PAGE_H4_OFFSET);
+  nvm3_halReadWords(hal, adr, &h4Rd, 1);
+
+  h4Wr = h4Rd & ~H4_BAD_MASK;
+  h4Wr |= (H4_BAD_NOTGOOD << H4_BAD_SHIFT);
+  (void)nvm3_halWriteWords(hal, adr, &h4Wr, 1);
+
+  // There is no recovery from a write error at this point.
+}
+
+sl_status_t nvm3_pageSetEip(const nvm3_HalHandle_t *hal, nvm3_HalPtr_t pageAdr)
+{
+  uint32_t  h4Rd;
+  uint32_t  h4Wr;
+  nvm3_HalPtr_t adr;
+  sl_status_t sta = SL_STATUS_OK;
+
+  nvm3_tracePrint(NVM3_TRACE_LEVEL_LOW, "  nvm3_pageSetEip, pageAdr=0x%p.\n", pageAdr);
+
+  adr = (nvm3_HalPtr_t)((size_t)pageAdr + NVM3_PAGE_H4_OFFSET);
+  nvm3_halReadWords(hal, adr, &h4Rd, 1);
+  if ((h4Rd & H4_EIP_MASK) == H4_EIP_CLEAR) {
+    h4Wr = (h4Rd & ~H4_EIP_MASK);
+    h4Wr |= H4_EIP_SET;
+    sta = nvm3_halWriteWords(hal, adr, &h4Wr, 1);
+  }
+
+  return sta;
+}
+
+uint32_t nvm3_pageGetEraseCnt(nvm3_PageHdr_t *pageHdr)
+{
+  uint8_t BCCB;
+
+  BCCB = 0;
+  nvm3_utilsComputeBergerCode(&BCCB, &(pageHdr->data[1]), NVM3_PAGE_COUNTER_SIZE);
+  if (BCCB == pageHdrGetCounterBcod(pageHdr->data[1])) {
+    return pageHdrGetCounterVal(pageHdr->data[1], eraseCntNormal);
+  }
+
+  BCCB = 0;
+  nvm3_utilsComputeBergerCode(&BCCB, &(pageHdr->data[2]), NVM3_PAGE_COUNTER_SIZE);
+  if (BCCB == pageHdrGetCounterBcod(pageHdr->data[2])) {
+    return pageHdrGetCounterVal(pageHdr->data[2], eraseCntInverted);
+  }
+
+  //printf(">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> ERROR: getEraseCount failed!\n");
+  return NVM3_ERASE_COUNT_INVALID;
+}
+
+nvm3_PageState_t nvm3_pageGetState(nvm3_PageHdr_t *pageHdr)
+{
+  nvm3_PageState_t pageState;
+  uint32_t eraseCnt = NVM3_ERASE_COUNT_INVALID;
+  bool pageHdrValid;
+
+  pageHdrValid = pageHdrMagicAndVersion(pageHdr);
+
+  if (pageHdrValid) {
+    eraseCnt = nvm3_pageGetEraseCnt(pageHdr);
+  }
+
+  if (eraseCnt != NVM3_ERASE_COUNT_INVALID) {
+    if (pageHdrIsPageBad(pageHdr)) {
+      pageState = nvm3_PageStateBad;
+    } else if (pageHdrIsEraseInProgress(pageHdr)) {
+      pageState = nvm3_PageStateGoodEip;
+    } else {
+      pageState = nvm3_PageStateGood;
+    }
+  } else {
+    if (pageHdrErased(pageHdr)) {
+      pageState = nvm3_PageStateInvalidErased;
+    } else {
+      pageState = nvm3_PageStateInvalidUnknown;
+    }
+  }
+
+  return pageState;
+}
+
+bool nvm3_pageStateIsGood(nvm3_PageState_t pageState)
+{
+  return ((pageState == nvm3_PageStateGood) || (pageState == nvm3_PageStateGoodEip));
+}
+
+bool nvm3_pageStateIsInvalid(nvm3_PageState_t pageState)
+{
+  return ((pageState == nvm3_PageStateInvalidErased) || (pageState == nvm3_PageStateInvalidUnknown));
+}
+
+nvm3_ObjPtr_t nvm3_pageGetFirstObj(nvm3_HalPtr_t pageAdr)
+{
+  return (nvm3_ObjPtr_t)((size_t)pageAdr + NVM3_PAGE_HEADER_SIZE);
+}
+
+#if defined(NVM3_SECURITY)
+sl_status_t nvm3_pageErase(const nvm3_HalHandle_t *hal, nvm3_HalPtr_t pageAdr, uint32_t eraseCnt, nvm3_HalInfo_t *halInfo, nvm3_SecurityType_t secType)
+#else
+sl_status_t nvm3_pageErase(const nvm3_HalHandle_t *hal, nvm3_HalPtr_t pageAdr, uint32_t eraseCnt, nvm3_HalInfo_t *halInfo)
+#endif
+{
+  sl_status_t sta;
+
+  nvm3_tracePrint(NVM3_TRACE_LEVEL_LOW, "  nvm3_pageErase: adr=0x%p, eraseCnt=%u.\n", pageAdr, eraseCnt);
+
+  // Erase
+  sta = nvm3_halPageErase(hal, pageAdr);
+  if (sta == SL_STATUS_OK) {
+    // Create new page header
+#if defined(NVM3_SECURITY)
+    sta = nvm3_pageHeaderWrite(hal, pageAdr, eraseCnt, halInfo, secType);
+#else
+    sta = nvm3_pageHeaderWrite(hal, pageAdr, eraseCnt, halInfo);
+#endif
+    if (sta != SL_STATUS_OK) {
+      nvm3_tracePrint(NVM3_TRACE_LEVEL_WARNING, "  erasePage: adr=0x%p, Write hdr ERROR, mark page as BAD.\n", pageAdr);
+      nvm3_pageSetBad(hal, pageAdr);
+    }
+  } else {
+    // Erasure failed, mark page as BAD
+    nvm3_tracePrint(NVM3_TRACE_LEVEL_WARNING, "  erasePage: adr=0x%p, Erase ERROR, page is marked as BAD.\n", pageAdr);
+    nvm3_pageSetBad(hal, pageAdr);
+  }
+
+  //nvm3_tracePrint("  erasePage: sta=%u.\n", sta);
+  return sta;
+}
+
+#if defined(NVM3_SECURITY)
+/***************************************************************************//**
+ * Get NVM3 security type.
+ *
+ * @param[in]  pageHdr     Page header of a valid page.
+ *
+ * @return                 Returns NVM3 security type.
+ ******************************************************************************/
+nvm3_SecurityType_t nvm3_pageGetSecType(nvm3_PageHdr_t *pageHdr)
+{
+  nvm3_SecurityType_t secType = NVM3_SECURITY_INVALID;
+
+  if (((pageHdr->data[4] & H5_SECTYPE_AEAD_MASK) >> H5_SECTYPE_AEAD_SHIFT) == 0) {
+    secType = NVM3_SECURITY_AEAD;
+  }
+
+  return secType;
+}
+#endif
+/** @endcond */

Libs/platform/emdrv/nvm3/src/nvm3_utils.c

@@ -0,0 +1,57 @@
+/***************************************************************************//**
+ * @file
+ * @brief NVM3 utility functions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include "nvm3_utils.h"
+
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+
+void nvm3_utilsComputeBergerCode(uint8_t *pResult, void *pInput, uint8_t numberOfBits)
+{
+  uint8_t sum;
+  uint32_t word = *((uint32_t *)pInput);
+  uint32_t mask;
+
+  // Clear bits that are outside the wanted bits
+  if (numberOfBits < 32U) {
+    mask = (1UL << numberOfBits) - 1U;
+    word = word & mask;
+  }
+
+  // Count bits set:
+  // From http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetNaive
+  word = word - ((word >> 1) & 0x55555555U);
+  word = (word & 0x33333333U) + ((word >> 2) & 0x33333333U);
+  sum = (uint8_t)((((word + (word >> 4)) & 0xF0F0F0FU) * 0x1010101U) >> 24U);
+
+  // Count bit cleared and accumulate
+  *pResult = *pResult + (numberOfBits - sum);
+}
+
+/// @endcond

Libs/platform/emdrv/uartdrv/inc/uartdrv.h

@@ -0,0 +1,470 @@
+/***************************************************************************//**
+ * @file
+ * @brief UARTDRV API definition.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef UARTDRV_H
+#define UARTDRV_H
+
+#if defined(SL_COMPONENT_CATALOG_PRESENT)
+#include "sl_component_catalog.h"
+#endif
+#if defined(SL_CATALOG_POWER_MANAGER_PRESENT)
+#include "sl_power_manager.h"
+#endif
+
+#include "em_device.h"
+#include "sl_device_peripheral.h"
+#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0))
+#include "em_usart.h"
+#endif
+#if defined(LEUART_COUNT) && (LEUART_COUNT > 0)
+#include "em_leuart.h"
+#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0))
+
+#if (_SILICON_LABS_32B_SERIES > 2)
+#define UARTDRV_USE_PERIPHERAL
+#include "sl_hal_eusart.h"
+#else
+#include "em_eusart.h"
+#endif
+#endif
+
+#include "sl_gpio.h"
+#include "sl_clock_manager.h"
+#include "ecode.h"
+#include "uartdrv_config.h"
+#include "dmadrv.h"
+#include "sl_enum.h"
+#include "sl_sleeptimer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup uartdrv
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup uartdrv_error_codes Error Codes
+ * @{
+ ******************************************************************************/
+#define ECODE_EMDRV_UARTDRV_OK                (ECODE_OK)                              ///< A successful return value.
+#define ECODE_EMDRV_UARTDRV_WAITING           (ECODE_EMDRV_UARTDRV_BASE | 0x00000001) ///< An operation is waiting in queue.
+#define ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE    (ECODE_EMDRV_UARTDRV_BASE | 0x00000002) ///< An illegal UART handle.
+#define ECODE_EMDRV_UARTDRV_PARAM_ERROR       (ECODE_EMDRV_UARTDRV_BASE | 0x00000003) ///< An illegal input parameter.
+#define ECODE_EMDRV_UARTDRV_BUSY              (ECODE_EMDRV_UARTDRV_BASE | 0x00000004) ///< The UART port is busy.
+#define ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION (ECODE_EMDRV_UARTDRV_BASE | 0x00000005) ///< An illegal operation on the UART port.
+#define ECODE_EMDRV_UARTDRV_IDLE              (ECODE_EMDRV_UARTDRV_BASE | 0x00000008) ///< No UART transfer is in progress.
+#define ECODE_EMDRV_UARTDRV_ABORTED           (ECODE_EMDRV_UARTDRV_BASE | 0x00000009) ///< A UART transfer has been aborted.
+#define ECODE_EMDRV_UARTDRV_QUEUE_FULL        (ECODE_EMDRV_UARTDRV_BASE | 0x0000000A) ///< A UART operation queue is full.
+#define ECODE_EMDRV_UARTDRV_QUEUE_EMPTY       (ECODE_EMDRV_UARTDRV_BASE | 0x0000000B) ///< A UART operation queue is empty.
+#define ECODE_EMDRV_UARTDRV_PARITY_ERROR      (ECODE_EMDRV_UARTDRV_BASE | 0x0000000C) ///< A UART parity error frame. Data is ignored.
+#define ECODE_EMDRV_UARTDRV_FRAME_ERROR       (ECODE_EMDRV_UARTDRV_BASE | 0x0000000D) ///< A UART frame error. Data is ignored.
+#define ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR   (ECODE_EMDRV_UARTDRV_BASE | 0x0000000E) ///< Unable to allocate DMA channels.
+#define ECODE_EMDRV_UARTDRV_CLOCK_ERROR       (ECODE_EMDRV_UARTDRV_BASE | 0x0000000F) ///< Unable to set a desired baudrate.
+/** @} (end addtogroup error codes) */
+
+/***************************************************************************//**
+ * @addtogroup uartdrv_status_codes Status Codes
+ * @{
+ ******************************************************************************/
+#define UARTDRV_STATUS_RXEN         (1 << 0)  ///< The receiver is enabled.
+#define UARTDRV_STATUS_TXEN         (1 << 1)  ///< The transmitter is enabled.
+#define UARTDRV_STATUS_RXBLOCK      (1 << 3)  ///< The receiver is blocked; incoming frames will be discarded.
+#define UARTDRV_STATUS_TXTRI        (1 << 4)  ///< The transmitter is tristated.
+#define UARTDRV_STATUS_TXC          (1 << 5)  ///< A transmit operation is complete. No more data is available in the transmit buffer and shift register.
+#define UARTDRV_STATUS_TXBL         (1 << 6)  ///< The transmit buffer is empty.
+#define UARTDRV_STATUS_RXDATAV      (1 << 7)  ///< Data is available in the receive buffer.
+#define UARTDRV_STATUS_RXFULL       (1 << 8)  ///< The receive buffer is full.
+#if defined(EUSART_STATUS_TXCANDTXIDLE)
+#define UARTDRV_STATUS_TXCANDTXIDLE (1 << 9)  ///< Set when both TXC and TXIDLE are set.
+#endif
+#define UARTDRV_STATUS_TXIDLE       (1 << 13) ///< The transmitter is idle.
+#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0))
+#define UARTDRV_STATUS_RXIDLE       (1 << 12) ///< The Receiver is idle.
+#endif
+/** @} (end addtogroup status codes) */
+
+typedef uint32_t UARTDRV_Count_t;     ///< A UART transfer count
+typedef uint32_t UARTDRV_Status_t;    ///< A UART status return type. Bitfield of UARTDRV_STATUS_* values.
+
+/**
+ * @enum UARTDRV_FlowControlType_t
+ * @brief UARTDRV Flow Control method.
+ */
+SL_ENUM(UARTDRV_FlowControlType_t) {
+  uartdrvFlowControlNone   = 0,   ///< None
+  uartdrvFlowControlSw     = 1,   ///< Software XON/XOFF
+  uartdrvFlowControlHw     = 2,   ///< nRTS/nCTS hardware handshake
+  uartdrvFlowControlHwUart = 3    ///< UART peripheral controls nRTS/nCTS
+};
+
+/// Flow Control state
+SL_ENUM(UARTDRV_FlowControlState_t) {
+  uartdrvFlowControlOn = 0,         ///< XON or nRTS/nCTS low
+  uartdrvFlowControlOff = 1,        ///< XOFF or nRTS/nCTS high
+  uartdrvFlowControlAuto = 2        ///< This driver controls the state.
+};
+
+/// Transfer abort type
+SL_ENUM(UARTDRV_AbortType_t) {
+  uartdrvAbortTransmit = 1,          ///< Abort current and queued transmit operations
+  uartdrvAbortReceive = 2,           ///< Abort current and queued receive operations
+  uartdrvAbortAll = 3                ///< Abort all current and queued operations
+};
+
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+/// Type of a UART peripheral
+SL_ENUM(UARTDRV_UartType_t) {
+#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0))
+  uartdrvUartTypeUart = 0,         ///< USART/UART peripheral
+#endif
+#if defined(LEUART_COUNT) && (LEUART_COUNT > 0)
+  uartdrvUartTypeLeuart = 1         ///< LEUART peripheral
+#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0))
+  uartdrvUartTypeEuart = 2         ///< EUART peripheral
+#endif
+};
+/// @endcond
+
+struct UARTDRV_HandleData;
+
+/***************************************************************************//**
+ * @brief
+ *  UARTDRV transfer completion callback function.
+ *
+ * @details
+ *  Called when a transfer is complete. An
+ *  application should check the transferStatus and itemsTransferred values.
+ *
+ * @param[in] handle
+ *   The UARTDRV device handle used to start the transfer.
+ *
+ * @param[in] transferStatus
+ *   Completion status of the transfer operation.
+ *
+ * @param[in] data
+ *   A pointer to the transfer data buffer.
+ *
+ * @param[in] transferCount
+ *   A number of bytes transferred.
+ ******************************************************************************/
+typedef void (*UARTDRV_Callback_t)(struct UARTDRV_HandleData *handle,
+                                   Ecode_t transferStatus,
+                                   uint8_t *data,
+                                   UARTDRV_Count_t transferCount);
+
+/// UART transfer buffer
+typedef struct {
+  uint8_t *data;                           ///< Transfer data buffer
+  UARTDRV_Count_t transferCount;           ///< Transfer item count
+  volatile UARTDRV_Count_t itemsRemaining; ///< Transfer items remaining
+  UARTDRV_Callback_t callback;             ///< Completion callback
+  Ecode_t transferStatus;                  ///< Completion status of the transfer operation
+} UARTDRV_Buffer_t;
+
+/// Transfer operation FIFO queue typedef
+typedef struct {
+  volatile uint16_t head;                  ///< An index of the next byte to send.
+  volatile uint16_t tail;                  ///< An index of the location to enqueue the next message.
+  volatile uint16_t used;                  ///< A number of bytes queued.
+  const uint16_t size;                     ///< FIFO size.
+  UARTDRV_Buffer_t fifo[1];                ///< FIFO of queued data. Actual size varies.
+} UARTDRV_Buffer_FifoQueue_t;
+
+/// Macros to define FIFO and buffer queues. typedef can't be used because the size
+/// of the FIFO array in the queues can change.
+#define DEFINE_BUF_QUEUE(qSize, qName) \
+  typedef struct {                     \
+    uint16_t head;                     \
+    uint16_t tail;                     \
+    volatile uint16_t used;            \
+    const uint16_t size;               \
+    UARTDRV_Buffer_t fifo[qSize];      \
+  } _##qName;                          \
+  static volatile _##qName qName =     \
+  {                                    \
+    .head = 0,                         \
+    .tail = 0,                         \
+    .used = 0,                         \
+    .size = qSize,                     \
+  }
+
+#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0))
+/**
+ * @struct UARTDRV_InitUart_t
+ * @brief A UART driver instance initialization structure.
+ *   LEUART driver instance initialization structure.
+ *   Contains a number of UARTDRV configuration options.
+ *   It is required for driver instance initialization.
+ *   This structure is passed to @ref UARTDRV_Init() when initializing a UARTDRV
+ *   instance.
+ */
+typedef struct {
+  USART_TypeDef              *port;             ///< The peripheral used for UART
+  uint32_t                   baudRate;          ///< UART baud rate
+#if defined(_USART_ROUTELOC0_MASK)
+  uint8_t                    portLocationTx;    ///< A location number for UART Tx pin.
+  uint8_t                    portLocationRx;    ///< A location number for UART Rx pin.
+#elif defined(_USART_ROUTE_MASK)
+  uint8_t                    portLocation;      ///< A location number for UART pins.
+#elif defined(_GPIO_USART_ROUTEEN_MASK)
+  sl_gpio_port_t             txPort;            ///< Port for UART Tx pin.
+  sl_gpio_port_t             rxPort;            ///< Port for UART Rx pin.
+  uint8_t                    txPin;             ///< Pin number for UART Tx.
+  uint8_t                    rxPin;             ///< Pin number for UART Rx.
+  uint8_t                    uartNum;           ///< UART instance number.
+#endif
+  USART_Stopbits_TypeDef     stopBits;          ///< A number of stop bits.
+  USART_Parity_TypeDef       parity;            ///< Parity configuration.
+  USART_OVS_TypeDef          oversampling;      ///< Oversampling mode.
+#if defined(USART_CTRL_MVDIS)
+  bool                       mvdis;             ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes.
+#endif
+  UARTDRV_FlowControlType_t  fcType;            ///< Flow control mode.
+  sl_gpio_port_t             ctsPort;           ///< A CTS pin port number.
+  uint8_t                    ctsPin;            ///< A CTS pin number.
+  sl_gpio_port_t             rtsPort;           ///< An RTS pin port number.
+  uint8_t                    rtsPin;            ///< An RTS pin number.
+  UARTDRV_Buffer_FifoQueue_t *rxQueue;          ///< A receive operation queue.
+  UARTDRV_Buffer_FifoQueue_t *txQueue;          ///< T transmit operation queue.
+#if defined(_USART_ROUTELOC1_MASK)
+  uint8_t                    portLocationCts;   ///< A location number for the UART CTS pin.
+  uint8_t                    portLocationRts;   ///< A location number for the UART RTS pin.
+#endif
+} UARTDRV_InitUart_t;
+#endif
+
+#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)
+/**
+ * @struct UARTDRV_InitLeuart_t
+ * @brief LEUART driver instance initialization structure.
+ *   LEUART driver instance initialization structure.
+ *   Contains a number of UARTDRV configuration options.
+ *   It is required to initialize a driver instance.
+ *   This structure is passed to @ref UARTDRV_InitLeuart() when initializing a UARTDRV
+ *   instance.
+ */
+typedef struct {
+  LEUART_TypeDef             *port;             ///< The peripheral used for LEUART
+  uint32_t                   baudRate;          ///< UART baud rate
+#if defined(_LEUART_ROUTELOC0_MASK)
+  uint8_t                    portLocationTx;    ///< Location number for LEUART Tx pin.
+  uint8_t                    portLocationRx;    ///< Location number for LEUART Rx pin.
+#else
+  uint8_t                    portLocation;      ///< Location number for LEUART pins
+#endif
+  LEUART_Stopbits_TypeDef    stopBits;          ///< Number of stop bits
+  LEUART_Parity_TypeDef      parity;            ///< Parity configuration
+  UARTDRV_FlowControlType_t  fcType;            ///< Flow control mode
+  sl_gpio_port_t             ctsPort;           ///< CTS pin port number
+  uint8_t                    ctsPin;            ///< CTS pin number
+  sl_gpio_port_t             rtsPort;           ///< RTS pin port number
+  uint8_t                    rtsPin;            ///< RTS pin number
+  UARTDRV_Buffer_FifoQueue_t *rxQueue;          ///< Receive operation queue
+  UARTDRV_Buffer_FifoQueue_t *txQueue;          ///< Transmit operation queue
+} UARTDRV_InitLeuart_t;
+#endif
+
+#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0))
+/// UART driver instance initialization structure.
+/// Contains a number of UARTDRV configuration options.
+/// It is required to initialize a driver instance.
+/// This structure is passed to @ref UARTDRV_InitEuart() when initializing a UARTDRV
+typedef struct {
+  EUSART_TypeDef                  *port;                ///< The peripheral used for EUART
+  bool                            useLowFrequencyMode;  ///< Clock configuration of the EUART
+  uint32_t                        baudRate;             ///< EUART baud rate
+  sl_gpio_port_t                  txPort;               ///< Port for UART Tx pin.
+  sl_gpio_port_t                  rxPort;               ///< Port for UART Rx pin.
+  uint8_t                         txPin;                ///< Pin number for UART Tx.
+  uint8_t                         rxPin;                ///< Pin number for UART Rx.
+  uint8_t                         uartNum;              ///< EUART instance number.
+#if defined(UARTDRV_USE_PERIPHERAL)
+  sl_hal_eusart_stop_bits_t       stopBits;             ///< Number of stop bits
+  sl_hal_eusart_parity_t          parity;               ///< Parity configuration
+  sl_hal_eusart_ovs_t             oversampling;         ///< Oversampling mode.
+  sl_hal_eusart_majority_vote_t   mvdis;                ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes.
+#else
+  EUSART_Stopbits_TypeDef         stopBits;             ///< Number of stop bits
+  EUSART_Parity_TypeDef           parity;               ///< Parity configuration
+  EUSART_OVS_TypeDef              oversampling;         ///< Oversampling mode.
+  EUSART_MajorityVote_TypeDef     mvdis;                ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes.
+#endif
+  UARTDRV_FlowControlType_t       fcType;               ///< Flow control mode
+  sl_gpio_port_t                  ctsPort;              ///< CTS pin port number
+  uint8_t                         ctsPin;               ///< CTS pin number
+  sl_gpio_port_t                  rtsPort;              ///< RTS pin port number
+  uint8_t                         rtsPin;               ///< RTS pin number
+  UARTDRV_Buffer_FifoQueue_t      *rxQueue;             ///< Receive operation queue
+  UARTDRV_Buffer_FifoQueue_t      *txQueue;             ///< Transmit operation queue
+} UARTDRV_InitEuart_t;
+#endif
+
+/// A UART driver instance handle data structure.
+/// Allocated by the application using UARTDRV.
+/// Several concurrent driver instances may exist in an application. The application must
+/// not modify the contents of this handle and should not depend on its values.
+typedef struct UARTDRV_HandleData{
+  /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+  union {
+#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0))
+    USART_TypeDef * uart;
+#endif
+#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)
+    LEUART_TypeDef * leuart;
+#endif
+#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0))
+    EUSART_TypeDef * euart;
+#endif
+    void * __reserved_space;
+  } peripheral;
+  uint8_t                       uartNum;           // UART instance number
+  unsigned int                  txDmaCh;           // A DMA ch assigned to Tx
+  unsigned int                  rxDmaCh;           // A DMA ch assigned to Rx
+  DMADRV_PeripheralSignal_t     txDmaSignal;       // A DMA Tx trigger source signal
+  DMADRV_PeripheralSignal_t     rxDmaSignal;       // A DMA Rx trigger source signal
+  UARTDRV_FlowControlState_t    fcSelfState;       // A current self flow control state
+  UARTDRV_FlowControlState_t    fcSelfCfg;         // A self flow control override configuration
+  UARTDRV_FlowControlState_t    fcPeerState;       // A current peer flow control state
+
+  sl_gpio_port_t                txPort;            // A Tx pin port number
+  sl_gpio_port_t                rxPort;            // An Rx pin port number
+  sl_gpio_port_t                ctsPort;           // A CTS pin port number
+  sl_gpio_port_t                rtsPort;           // An RTS pin port number
+  uint8_t                       txPin;             // A Tx pin number
+  uint8_t                       rxPin;             // An Tx pin number
+  uint8_t                       ctsPin;            // A CTS pin number
+  uint8_t                       rtsPin;            // An RTS pin number
+  sl_peripheral_t               usartPeripheral;   // Usart peripheral select
+  UARTDRV_Buffer_FifoQueue_t    *rxQueue;          // A receive operation queue
+  UARTDRV_Buffer_FifoQueue_t    *txQueue;          // A transmit operation queue
+  volatile bool                 rxDmaActive;       // A receive DMA is currently active
+  volatile bool                 txDmaActive;       // A transmit DMA is currently active
+  volatile uint8_t              txDmaPaused;       // A transmit DMA pause counter
+  bool                          IgnoreRestrain;    // A transmit does not respect uartdrvFlowControlOff
+  bool                          hasTransmitted;    // Indicates whether the handle has transmitted data
+  UARTDRV_FlowControlType_t     fcType;            // A flow control mode
+  UARTDRV_UartType_t            type;              // A type of UART
+  volatile int                  em1RequestCount;   // A EM1 request count for the handle
+  sl_sleeptimer_timer_handle_t  delayedTxTimer;    // A timer to wait for the last byte out
+  size_t                        sleep;             // Sleep state on isr return
+  /// @endcond
+} UARTDRV_HandleData_t;
+
+/// Handle pointer
+typedef UARTDRV_HandleData_t * UARTDRV_Handle_t;
+
+#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0))
+Ecode_t UARTDRV_InitUart(UARTDRV_Handle_t handle,
+                         const UARTDRV_InitUart_t * initData);
+#endif
+
+#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)
+Ecode_t UARTDRV_InitLeuart(UARTDRV_Handle_t handle,
+                           const UARTDRV_InitLeuart_t * initData);
+#endif
+
+#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0))
+Ecode_t UARTDRV_InitEuart(UARTDRV_Handle_t handle,
+                          const UARTDRV_InitEuart_t * initData);
+#endif
+Ecode_t UARTDRV_DeInit(UARTDRV_Handle_t handle);
+
+UARTDRV_Status_t UARTDRV_GetPeripheralStatus(UARTDRV_Handle_t handle);
+
+UARTDRV_Status_t UARTDRV_GetReceiveStatus(UARTDRV_Handle_t handle,
+                                          uint8_t **buffer,
+                                          UARTDRV_Count_t *bytesReceived,
+                                          UARTDRV_Count_t *bytesRemaining);
+
+UARTDRV_Status_t UARTDRV_GetTransmitStatus(UARTDRV_Handle_t handle,
+                                           uint8_t **buffer,
+                                           UARTDRV_Count_t *bytesSent,
+                                           UARTDRV_Count_t *bytesRemaining);
+
+uint8_t UARTDRV_GetReceiveDepth(UARTDRV_Handle_t handle);
+
+uint8_t UARTDRV_GetTransmitDepth(UARTDRV_Handle_t handle);
+
+Ecode_t UARTDRV_Transmit(UARTDRV_Handle_t handle,
+                         uint8_t *data,
+                         UARTDRV_Count_t count,
+                         UARTDRV_Callback_t callback);
+
+Ecode_t UARTDRV_Receive(UARTDRV_Handle_t handle,
+                        uint8_t *data,
+                        UARTDRV_Count_t count,
+                        UARTDRV_Callback_t callback);
+
+Ecode_t UARTDRV_TransmitB(UARTDRV_Handle_t handle,
+                          uint8_t *data,
+                          UARTDRV_Count_t count);
+
+Ecode_t UARTDRV_ReceiveB(UARTDRV_Handle_t handle,
+                         uint8_t *data,
+                         UARTDRV_Count_t count);
+
+Ecode_t UARTDRV_ForceTransmit(UARTDRV_Handle_t handle,
+                              uint8_t *data,
+                              UARTDRV_Count_t count);
+
+UARTDRV_Count_t UARTDRV_ForceReceive(UARTDRV_Handle_t handle,
+                                     uint8_t *data,
+                                     UARTDRV_Count_t maxLength);
+
+Ecode_t UARTDRV_Abort(UARTDRV_Handle_t handle, UARTDRV_AbortType_t type);
+
+Ecode_t UARTDRV_PauseTransmit(UARTDRV_Handle_t handle);
+
+Ecode_t UARTDRV_ResumeTransmit(UARTDRV_Handle_t handle);
+
+UARTDRV_FlowControlState_t UARTDRV_FlowControlGetSelfStatus(UARTDRV_Handle_t handle);
+
+UARTDRV_FlowControlState_t UARTDRV_FlowControlGetPeerStatus(UARTDRV_Handle_t handle);
+
+Ecode_t UARTDRV_FlowControlSet(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state);
+
+Ecode_t UARTDRV_FlowControlSetPeerStatus(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state);
+
+Ecode_t UARTDRV_FlowControlIgnoreRestrain(UARTDRV_Handle_t handle);
+
+#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT)
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_UARTDRV, SL_CODE_CLASS_TIME_CRITICAL)
+sl_power_manager_on_isr_exit_t sl_uartdrv_sleep_on_isr_exit(void);
+#endif
+
+/** @} (end addtogroup uartdrv) */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // UARTDRV_H

Libs/platform/hardware/board/inc/sl_board_control.h

@@ -0,0 +1,219 @@
+/***************************************************************************//**
+ * @file
+ * @brief Board Control API
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifndef SL_BOARD_CONTROL_H
+#define SL_BOARD_CONTROL_H
+
+#include "sl_status.h"
+#include "sl_enum.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup board_control Board Control
+ * @brief Functions to control Silicon Labs board features
+ * @{
+ ******************************************************************************/
+
+/// Board Sensor Type
+SL_ENUM_GENERIC(sl_board_sensor_t, int) {
+  SL_BOARD_SENSOR_RHT           = (1UL << 0UL),     ///< Relative Humidity and Temperature Sensor
+  SL_BOARD_SENSOR_LIGHT         = (1UL << 1UL),     ///< UV Index and Ambient Light Sensor
+  SL_BOARD_SENSOR_PRESSURE      = (1UL << 2UL),     ///< Barometric Pressure Sensor
+  SL_BOARD_SENSOR_HALL          = (1UL << 3UL),     ///< Hall Effect Sensor
+  SL_BOARD_SENSOR_GAS           = (1UL << 4UL),     ///< Gas Sensor
+  SL_BOARD_SENSOR_IMU           = (1UL << 5UL),     ///< Inertial Measurement Unit (Accelerometer/Gyroscope)
+  SL_BOARD_SENSOR_MICROPHONE    = (1UL << 6UL),     ///< Microphone
+};
+
+/// Board Memory Type
+SL_ENUM_GENERIC(sl_board_memory_t, int) {
+  SL_BOARD_MEMORY_SDCARD        = (1UL << 0UL),     ///< SD Card
+  SL_BOARD_MEMORY_QSPI          = (1UL << 1UL),     ///< Quad SPI Flash
+};
+
+/// Board Oscillator Type
+SL_ENUM_GENERIC(sl_board_oscillator_t, int) {
+  SL_BOARD_OSCILLATOR_TCXO      = (1UL << 0UL),     ///< TCXO
+};
+
+/***************************************************************************//**
+ * @brief Configure Virtual COM UART.
+ *
+ * @return Status code
+ * @retval SL_STATUS_OK VCOM was successfully enabled
+ * @retval SL_STATUS_FAIL Enabling VCOM failed
+ * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board
+ * @retval SL_STATUS_NOT_SUPPORTED VCOM enabled was not configured
+ ******************************************************************************/
+sl_status_t sl_board_configure_vcom(void);
+
+/***************************************************************************//**
+ * @brief Enable Virtual COM UART.
+ *
+ * @return Status code
+ * @retval SL_STATUS_OK VCOM was successfully enabled
+ * @retval SL_STATUS_FAIL Enabling VCOM failed
+ * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board
+ ******************************************************************************/
+sl_status_t sl_board_enable_vcom(void);
+
+/***************************************************************************//**
+ * @brief Disable Virtual COM UART.
+ *
+ * @return Status code
+ * @retval SL_STATUS_OK VCOM was successfully disabled
+ * @retval SL_STATUS_FAIL Disabling VCOM failed
+ * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board
+ ******************************************************************************/
+sl_status_t sl_board_disable_vcom(void);
+
+/***************************************************************************//**
+ * @brief Enable a sensor.
+ *
+ * @warning
+ *   On boards 4166A, 4184A, and 4184B sensors
+ *     - Pressure Sensor, RH/Temp Sensor, and UV/Ambient Light Sensor;
+ *     - UV/Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor;
+ *     - Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor
+ *   respectively, are tied to the same enable pin. Calling the enable function
+ *   for only one of these sensors has the side-effect of enabling all three;
+ *   and calling the disable function for only one of them has the
+ *   side-effect of disabling all three.
+ *   The latter scenario seems less than desirable.
+ *
+ * @param[in] sensor Sensor to enable
+ *
+ * @return Status code
+ * @retval SL_STATUS_OK Sensor was successfully enabled
+ * @retval SL_STATUS_FAIL Enabling sensor failed
+ * @retval SL_STATUS_NOT_AVAILABLE Sensor control is not available on this board
+ ******************************************************************************/
+sl_status_t sl_board_enable_sensor(sl_board_sensor_t sensor);
+
+/***************************************************************************//**
+ * @brief Disable a sensor.
+ *
+ * @warning
+ *   On boards 4166A, 4184A, and 4184B sensors
+ *     - Pressure Sensor, RH/Temp Sensor, and UV/Ambient Light Sensor;
+ *     - UV/Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor;
+ *     - Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor
+ *   respectively, are tied to the same enable pin. Calling the enable function
+ *   for only one of these sensors has the side-effect of enabling all three;
+ *   and calling the disable function for only one of them has the
+ *   side-effect of disabling all three.
+ *   The latter scenario seems less than desirable.
+ *
+ * @param[in] sensor Sensors to disable
+ *
+ * @return Status code
+ * @retval SL_STATUS_OK Sensor was successfully disabled
+ * @retval SL_STATUS_FAIL Disabling sensor failed
+ * @retval SL_STATUS_NOT_AVAILABLE Sensor control is not available on this board
+ ******************************************************************************/
+sl_status_t sl_board_disable_sensor(sl_board_sensor_t sensor);
+
+/***************************************************************************//**
+ * @brief Enable display.
+ *
+ * @return Status code
+ * @retval SL_STATUS_OK Display was successfully enabled
+ * @retval SL_STATUS_FAIL Enabling display failed
+ * @retval SL_STATUS_NOT_AVAILABLE Display control is not available on this board
+ ******************************************************************************/
+sl_status_t sl_board_enable_display(void);
+
+/***************************************************************************//**
+ * @brief Disable display.
+ *
+ * @return Status code
+ * @retval SL_STATUS_OK Display was successfully disabled
+ * @retval SL_STATUS_FAIL Disabling display failed
+ * @retval SL_STATUS_NOT_AVAILABLE Display control is not available on this board
+ ******************************************************************************/
+sl_status_t sl_board_disable_display(void);
+
+/***************************************************************************//**
+ * @brief Enable memory.
+ *
+ * @param[in] memory Memory to enable
+ *
+ * @return Status code
+ * @retval SL_STATUS_OK Memory was successfully enabled
+ * @retval SL_STATUS_FAIL Enabling memory failed
+ * @retval SL_STATUS_NOT_AVAILABLE Memory control is not available on this board
+ ******************************************************************************/
+sl_status_t sl_board_enable_memory(sl_board_memory_t memory);
+
+/***************************************************************************//**
+ * @brief Disable memory.
+ *
+ * @param[in] memory Memory to disable
+ *
+ * @return Status code
+ * @retval SL_STATUS_OK Memory was successfully disabled
+ * @retval SL_STATUS_FAIL Disabling memory failed
+ * @retval SL_STATUS_NOT_AVAILABLE Memory control is not available on this board
+ ******************************************************************************/
+sl_status_t sl_board_disable_memory(sl_board_memory_t memory);
+
+/***************************************************************************//**
+ * @brief Enable an oscillator.
+ *
+ * @param[in] oscillator Oscillator to enable
+ *
+ * @return Status code
+ * @retval SL_STATUS_OK Oscillator was successfully enabled
+ * @retval SL_STATUS_FAIL Enabling oscillator failed
+ * @retval SL_STATUS_NOT_AVAILABLE Oscillator control is not available on this board
+ ******************************************************************************/
+sl_status_t sl_board_enable_oscillator(sl_board_oscillator_t oscillator);
+
+/***************************************************************************//**
+ * @brief Disable a oscillator.
+ *
+ * @param[in] oscillator Oscillator to disable
+ *
+ * @return Status code
+ * @retval SL_STATUS_OK Oscillator was successfully disabled
+ * @retval SL_STATUS_FAIL Disabling oscillator failed
+ * @retval SL_STATUS_NOT_AVAILABLE Oscillator control is not available on this board
+ ******************************************************************************/
+sl_status_t sl_board_disable_oscillator(sl_board_oscillator_t oscillator);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // SL_BOARD_CONTROL_H

Libs/platform/hardware/board/inc/sl_board_init.h

@@ -0,0 +1,65 @@
+/***************************************************************************//**
+ * @file
+ * @brief Board Init
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifndef SL_BOARD_INIT_H
+#define SL_BOARD_INIT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup board_init Board Init
+ * @brief Initialization of Silicon Labs board features
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief Initialize board.
+ * @details
+ * Initialize a Silicon Labs board by enabling available and configured board
+ * features, in addition to performing necessary board errata fixes and setting
+ * default pin states.
+ ******************************************************************************/
+void sl_board_init(void);
+
+/***************************************************************************//**
+ * @brief Initialize board features that are required at early boot.
+ * @details
+ * Certain board features such as external oscillators may need to be powered
+ * before core device features, such as the clock tree, are configured.
+ ******************************************************************************/
+void sl_board_preinit(void);
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SL_BOARD_INIT_H

Libs/platform/hardware/board/src/sl_board_control_gpio.c

@@ -0,0 +1,489 @@
+/***************************************************************************//**
+ * @file
+ * @brief Board Control API
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#include "sl_board_control.h"
+#include "sl_board_control_config.h"
+#include "em_device.h"
+#include "sl_assert.h"
+#include "sl_gpio.h"
+
+sl_status_t sl_board_configure_vcom(void)
+{
+#if defined(SL_BOARD_ENABLE_VCOM) && SL_BOARD_ENABLE_VCOM
+  return sl_board_enable_vcom();
+#else
+  return SL_STATUS_NOT_SUPPORTED;
+#endif
+}
+
+sl_status_t sl_board_enable_vcom(void)
+{
+#if defined(SL_BOARD_ENABLE_VCOM_PORT)
+  sl_gpio_t enable_vcom_gpio = {
+    .port = SL_BOARD_ENABLE_VCOM_PORT,
+    .pin = SL_BOARD_ENABLE_VCOM_PIN,
+  };
+  sl_gpio_set_pin_mode(&enable_vcom_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+  return SL_STATUS_OK;
+#else
+  return SL_STATUS_NOT_AVAILABLE;
+#endif
+}
+
+sl_status_t sl_board_disable_vcom(void)
+{
+#if defined(SL_BOARD_ENABLE_VCOM_PORT)
+  sl_gpio_t disable_vcom_gpio = {
+    .port = SL_BOARD_ENABLE_VCOM_PORT,
+    .pin = SL_BOARD_ENABLE_VCOM_PIN,
+  };
+  sl_gpio_set_pin_mode(&disable_vcom_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+  return SL_STATUS_OK;
+#else
+  return SL_STATUS_NOT_AVAILABLE;
+#endif
+}
+
+sl_status_t sl_board_enable_display(void)
+{
+#if defined(SL_BOARD_ENABLE_DISPLAY_PORT)
+  sl_gpio_t enable_display_gpio = {
+    .port = SL_BOARD_ENABLE_DISPLAY_PORT,
+    .pin = SL_BOARD_ENABLE_DISPLAY_PIN,
+  };
+  sl_gpio_set_pin_mode(&enable_display_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+#if defined(SL_BOARD_SELECT_DISPLAY_PORT)
+  sl_gpio_t select_display_gpio;
+  select_display_gpio.port = SL_BOARD_SELECT_DISPLAY_PORT;
+  select_display_gpio.pin = SL_BOARD_SELECT_DISPLAY_PIN;
+  sl_gpio_set_pin_mode(&select_display_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+#endif
+  return SL_STATUS_OK;
+#else
+  return SL_STATUS_NOT_AVAILABLE;
+#endif
+}
+
+sl_status_t sl_board_disable_display(void)
+{
+#if defined(SL_BOARD_ENABLE_DISPLAY_PORT)
+  sl_gpio_t enable_display_gpio = {
+    .port = SL_BOARD_ENABLE_DISPLAY_PORT,
+    .pin = SL_BOARD_ENABLE_DISPLAY_PIN,
+  };
+  sl_gpio_set_pin_mode(&enable_display_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+#if defined(SL_BOARD_SELECT_DISPLAY_PORT)
+  sl_gpio_t select_display_gpio;
+  select_display_gpio.port = SL_BOARD_SELECT_DISPLAY_PORT;
+  select_display_gpio.pin = SL_BOARD_SELECT_DISPLAY_PIN;
+  sl_gpio_set_pin_mode(&select_display_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+#endif
+  return SL_STATUS_OK;
+#else
+  return SL_STATUS_NOT_AVAILABLE;
+#endif
+}
+
+sl_status_t sl_board_enable_sensor(sl_board_sensor_t sensor)
+{
+  sl_status_t status = SL_STATUS_NOT_AVAILABLE;
+
+#if defined(SL_BOARD_ENABLE_SENSOR_RHT_PORT)
+  sl_gpio_t enable_sensor_rht_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_RHT_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_RHT_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT)
+  sl_gpio_t enable_sensor_light_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_LIGHT_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_LIGHT_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT)
+  sl_gpio_t enable_sensor_pressure_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_HALL_PORT)
+  sl_gpio_t enable_sensor_hall_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_HALL_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_HALL_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_GAS_PORT)
+  sl_gpio_t enable_sensor_gas_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_GAS_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_GAS_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_IMU_PORT)
+  sl_gpio_t enable_sensor_imu_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_IMU_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_IMU_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT)
+  sl_gpio_t enable_sensor_microphone_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN,
+  };
+#endif
+
+  switch (sensor) {
+    case SL_BOARD_SENSOR_RHT:
+    #if defined(SL_BOARD_ENABLE_SENSOR_RHT_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_rht_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_SENSOR_LIGHT:
+    #if defined(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_light_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_SENSOR_PRESSURE:
+    #if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_pressure_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_SENSOR_HALL:
+    #if defined(SL_BOARD_ENABLE_SENSOR_HALL_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_hall_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_SENSOR_GAS:
+    #if defined(SL_BOARD_ENABLE_SENSOR_GAS_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_gas_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_SENSOR_IMU:
+    #if defined(SL_BOARD_ENABLE_SENSOR_IMU_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_imu_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_SENSOR_MICROPHONE:
+    #if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_microphone_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    default:
+      EFM_ASSERT(false);  // Should not happen
+      break;
+  }
+
+  return status;
+}
+
+sl_status_t sl_board_disable_sensor(sl_board_sensor_t sensor)
+{
+  sl_status_t status = SL_STATUS_NOT_AVAILABLE;
+
+#if defined(SL_BOARD_ENABLE_SENSOR_RHT_PORT)
+  sl_gpio_t enable_sensor_rht_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_RHT_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_RHT_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT)
+  sl_gpio_t enable_sensor_light_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_LIGHT_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_LIGHT_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT)
+  sl_gpio_t enable_sensor_pressure_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_HALL_PORT)
+  sl_gpio_t enable_sensor_hall_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_HALL_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_HALL_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_GAS_PORT)
+  sl_gpio_t enable_sensor_gas_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_GAS_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_GAS_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_IMU_PORT)
+  sl_gpio_t enable_sensor_imu_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_IMU_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_IMU_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT)
+  sl_gpio_t enable_sensor_microphone_gpio = {
+    .port = SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT,
+    .pin = SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN,
+  };
+#endif
+
+  switch (sensor) {
+    case SL_BOARD_SENSOR_RHT:
+    #if defined(SL_BOARD_ENABLE_SENSOR_RHT_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_rht_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_SENSOR_LIGHT:
+    #if defined(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_light_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_SENSOR_PRESSURE:
+    #if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_pressure_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_SENSOR_HALL:
+    #if defined(SL_BOARD_ENABLE_SENSOR_HALL_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_hall_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_SENSOR_GAS:
+    #if defined(SL_BOARD_ENABLE_SENSOR_GAS_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_gas_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_SENSOR_IMU:
+    #if defined(SL_BOARD_ENABLE_SENSOR_IMU_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_imu_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_SENSOR_MICROPHONE:
+    #if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT)
+      sl_gpio_set_pin_mode(&enable_sensor_microphone_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    default:
+      EFM_ASSERT(false);  // Should not happen
+      break;
+  }
+
+  return status;
+}
+
+sl_status_t sl_board_enable_memory(sl_board_memory_t memory)
+{
+  sl_status_t status = SL_STATUS_NOT_AVAILABLE;
+
+#if defined(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT)
+  sl_gpio_t enable_memory_sdcard_gpio = {
+    .port = SL_BOARD_ENABLE_MEMORY_SDCARD_PORT,
+    .pin = SL_BOARD_ENABLE_MEMORY_SDCARD_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_MEMORY_QSPI_PORT)
+  sl_gpio_t enable_memory_qspi_gpio = {
+    .port = SL_BOARD_ENABLE_MEMORY_QSPI_PORT,
+    .pin = SL_BOARD_ENABLE_MEMORY_QSPI_PIN,
+  };
+#endif
+
+  switch (memory) {
+    case SL_BOARD_MEMORY_SDCARD:
+    #if defined(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT)
+      sl_gpio_set_pin_mode(&enable_memory_sdcard_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_MEMORY_QSPI:
+    #if defined(SL_BOARD_ENABLE_MEMORY_QSPI_PORT)
+      sl_gpio_set_pin_mode(&enable_memory_qspi_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    default:
+      EFM_ASSERT(false); // Should not happen
+      break;
+  }
+
+  return status;
+}
+
+sl_status_t sl_board_disable_memory(sl_board_memory_t memory)
+{
+  sl_status_t status = SL_STATUS_NOT_AVAILABLE;
+
+#if defined(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT)
+  sl_gpio_t enable_memory_sdcard_gpio = {
+    .port = SL_BOARD_ENABLE_MEMORY_SDCARD_PORT,
+    .pin = SL_BOARD_ENABLE_MEMORY_SDCARD_PIN,
+  };
+#endif
+#if defined(SL_BOARD_ENABLE_MEMORY_QSPI_PORT)
+  sl_gpio_t enable_memory_qspi_gpio = {
+    .port = SL_BOARD_ENABLE_MEMORY_QSPI_PORT,
+    .pin = SL_BOARD_ENABLE_MEMORY_QSPI_PIN,
+  };
+#endif
+
+  switch (memory) {
+    case SL_BOARD_MEMORY_SDCARD:
+    #if defined(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT)
+      sl_gpio_set_pin_mode(&enable_memory_sdcard_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    case SL_BOARD_MEMORY_QSPI:
+    #if defined(SL_BOARD_ENABLE_MEMORY_QSPI_PORT)
+      sl_gpio_set_pin_mode(&enable_memory_qspi_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    default:
+      EFM_ASSERT(false);  // Should not happen
+      break;
+  }
+
+  return status;
+}
+
+sl_status_t sl_board_enable_oscillator(sl_board_oscillator_t oscillator)
+{
+  sl_status_t status = SL_STATUS_NOT_AVAILABLE;
+
+  switch (oscillator) {
+    case SL_BOARD_OSCILLATOR_TCXO:
+    #if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT)
+      sl_gpio_t enable_oscillator_tcxo_gpio = {
+        .port = SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT,
+        .pin = SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN,
+      };
+      sl_gpio_set_pin_mode(&enable_oscillator_tcxo_gpio, SL_GPIO_MODE_PUSH_PULL, 1);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    default:
+      EFM_ASSERT(false);  // Should not happen
+      break;
+  }
+
+  return status;
+}
+
+sl_status_t sl_board_disable_oscillator(sl_board_oscillator_t oscillator)
+{
+  sl_status_t status = SL_STATUS_NOT_AVAILABLE;
+
+  switch (oscillator) {
+    case SL_BOARD_OSCILLATOR_TCXO:
+    #if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT)
+      sl_gpio_t enable_oscillator_tcxo_gpio = {
+        .port = SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT,
+        .pin = SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN,
+      };
+      sl_gpio_set_pin_mode(&enable_oscillator_tcxo_gpio, SL_GPIO_MODE_PUSH_PULL, 0);
+      status = SL_STATUS_OK;
+    #else
+      EFM_ASSERT(false);
+    #endif
+      break;
+
+    default:
+      EFM_ASSERT(false); // Should not happen
+      break;
+  }
+
+  return status;
+}

Libs/platform/hardware/board/src/sl_board_init.c

@@ -0,0 +1,98 @@
+/***************************************************************************//**
+ * @file
+ * @brief Board Init
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#include "sl_board_control.h"
+#include "sl_board_control_config.h"
+
+#include "sl_clock_manager.h"
+
+#if defined(SL_COMPONENT_CATALOG_PRESENT)
+#include "sl_component_catalog.h"
+#endif
+
+#if defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT) || defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_EUSART_PRESENT)
+#include "sl_mx25_flash_shutdown.h"
+#endif
+
+void sl_board_default_init(void);
+
+void sl_board_init(void)
+{
+  sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO);
+
+  // Errata fixes and default pin states
+  sl_board_default_init();
+
+#if defined(SL_BOARD_ENABLE_SENSOR_RHT) && SL_BOARD_ENABLE_SENSOR_RHT
+  sl_board_enable_sensor(SL_BOARD_SENSOR_RHT);
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_LIGHT) && SL_BOARD_ENABLE_SENSOR_LIGHT
+  sl_board_enable_sensor(SL_BOARD_SENSOR_LIGHT);
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE) && SL_BOARD_ENABLE_SENSOR_PRESSURE
+  sl_board_enable_sensor(SL_BOARD_SENSOR_PRESSURE);
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_HALL) && SL_BOARD_ENABLE_SENSOR_HALL
+  sl_board_enable_sensor(SL_BOARD_SENSOR_HALL);
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_GAS) && SL_BOARD_ENABLE_SENSOR_GAS
+  sl_board_enable_sensor(SL_BOARD_SENSOR_GAS);
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_IMU) && SL_BOARD_ENABLE_SENSOR_IMU
+  sl_board_enable_sensor(SL_BOARD_SENSOR_IMU);
+#endif
+#if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE) && SL_BOARD_ENABLE_SENSOR_MICROPHONE
+  sl_board_enable_sensor(SL_BOARD_SENSOR_MICROPHONE);
+#endif
+
+#if defined(SL_BOARD_ENABLE_DISPLAY) && SL_BOARD_ENABLE_DISPLAY
+  sl_board_enable_display();
+#endif
+
+#if defined(SL_BOARD_ENABLE_MEMORY_SDCARD) && SL_BOARD_ENABLE_MEMORY_SDCARD
+  sl_board_enable_memory(SL_BOARD_MEMORY_SDCARD);
+#endif
+#if defined(SL_BOARD_ENABLE_MEMORY_QSPI) && SL_BOARD_ENABLE_MEMORY_QSPI
+  sl_board_enable_memory(SL_BOARD_MEMORY_QSPI);
+#endif
+
+#if (defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT) || defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_EUSART_PRESENT)) && \
+    defined(SL_BOARD_DISABLE_MEMORY_SPI) && SL_BOARD_DISABLE_MEMORY_SPI
+  sl_mx25_flash_shutdown();
+#endif
+}
+
+void sl_board_preinit(void)
+{
+  sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO);
+
+#if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO) && SL_BOARD_ENABLE_OSCILLATOR_TCXO
+  sl_board_enable_oscillator(SL_BOARD_OSCILLATOR_TCXO);
+#endif
+}

Libs/platform/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_eusart/sl_mx25_flash_shutdown.h

@@ -0,0 +1,65 @@
+/***************************************************************************//**
+ * @file
+ * @brief MX25 flash shutdown
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef  SL_MX25_FLASH_SHUTDOWN_H
+#define  SL_MX25_FLASH_SHUTDOWN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "em_device.h"
+#include "sl_mx25_flash_shutdown_eusart_config.h"
+
+/***************************************************************************//**
+ * @addtogroup mx25_flash_shutdown MX25 SPI Flash Shutdown
+ * @brief  Provide a function to put the MX25 SPI flash into deep power down
+ * mode to reduce power consumption.
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *    Put the MX25 SPI flash into deep power down mode.
+ *
+ * This function initializes SPI communication with the MX25 flash and sends
+ * the deep power-down instruction, which sets the device to minimal
+ * power consumption. The SPI communication is disabled to free the USART.
+ ******************************************************************************/
+void sl_mx25_flash_shutdown(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif // SL_MX25_FLASH_SHUTDOWN_H

Libs/platform/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_eusart/sl_mx25_flash_shutdown.c

@@ -0,0 +1,175 @@
+/***************************************************************************//**
+ * @file
+ * @brief MX25 flash shutdown
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include "sl_clock_manager.h"
+#include "sl_gpio.h"
+#include "sl_udelay.h"
+#include "sl_mx25_flash_shutdown.h"
+
+#if defined(_SILICON_LABS_32B_SERIES_2)
+#include "em_eusart.h"
+#else
+#include "sl_hal_eusart.h"
+#endif
+
+#include "stddef.h"
+
+// Fallback to baudrate of 8 MHz if not defined for backwards compatibility
+#ifndef SL_MX25_FLASH_SHUTDOWN_BAUDRATE
+#define SL_MX25_FLASH_SHUTDOWN_BAUDRATE   7500000
+#endif
+
+// Define usart clock
+#ifndef SL_MX25_FLASH_SHUTDOWN_SCLK
+#define MERGE(x, y)   x##y
+#define EUSART_CLOCK(n) MERGE(SL_BUS_CLOCK_EUSART, n)
+#define SL_MX25_FLASH_SHUTDOWN_SCLK EUSART_CLOCK(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO)
+#endif
+
+#ifdef SL_MX25_FLASH_SHUTDOWN_PERIPHERAL
+static void cs_low(void)
+{
+  sl_gpio_t mx25_flash_shutdown_cs_gpio = {
+    .port = SL_MX25_FLASH_SHUTDOWN_CS_PORT,
+    .pin = SL_MX25_FLASH_SHUTDOWN_CS_PIN,
+  };
+  sl_gpio_clear_pin(&mx25_flash_shutdown_cs_gpio);
+}
+
+static void cs_high(void)
+{
+  sl_gpio_t mx25_flash_shutdown_cs_gpio = {
+    .port = SL_MX25_FLASH_SHUTDOWN_CS_PORT,
+    .pin = SL_MX25_FLASH_SHUTDOWN_CS_PIN,
+  };
+  sl_gpio_set_pin(&mx25_flash_shutdown_cs_gpio);
+}
+#endif
+
+/***************************************************************************//**
+ *    Puts the MX25 into deep power down mode.
+ ******************************************************************************/
+void sl_mx25_flash_shutdown(void)
+{
+#ifdef SL_MX25_FLASH_SHUTDOWN_PERIPHERAL
+
+#if defined(_SILICON_LABS_32B_SERIES_2)
+  // Init flash
+  EUSART_SpiInit_TypeDef init = EUSART_SPI_MASTER_INIT_DEFAULT_HF;
+  EUSART_SpiAdvancedInit_TypeDef advancedInit = EUSART_SPI_ADVANCED_INIT_DEFAULT;
+
+  sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO);
+  sl_clock_manager_enable_bus_clock(SL_MX25_FLASH_SHUTDOWN_SCLK);
+
+  advancedInit.msbFirst     = true;
+  advancedInit.autoCsEnable = false;
+  init.bitRate = SL_MX25_FLASH_SHUTDOWN_BAUDRATE;
+
+  init.advancedSettings = &advancedInit;
+
+  EUSART_SpiInit(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL, &init);
+
+#else
+  // Init flash
+  sl_hal_eusart_spi_config_t init = SL_HAL_EUSART_SPI_MASTER_INIT_DEFAULT_HF;
+  sl_hal_eusart_spi_advanced_config_t advancedInit = SL_HAL_EUSART_SPI_ADVANCED_INIT_DEFAULT;
+
+  sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO);
+  sl_clock_manager_enable_bus_clock(SL_MX25_FLASH_SHUTDOWN_SCLK);
+
+  advancedInit.msb_first     = true;
+  advancedInit.auto_cs_enable = false;
+
+  init.advanced_config = &advancedInit;
+
+  sl_hal_eusart_init_spi(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL, &init);
+  sl_hal_eusart_enable(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL);
+  sl_hal_eusart_enable_tx(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL);
+  sl_hal_eusart_enable_rx(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL);
+#endif
+
+  // IO config
+  sl_gpio_set_pin_mode(&(sl_gpio_t) {SL_MX25_FLASH_SHUTDOWN_TX_PORT, SL_MX25_FLASH_SHUTDOWN_TX_PIN }, SL_GPIO_MODE_PUSH_PULL, 1);
+  sl_gpio_set_pin_mode(&(sl_gpio_t) {SL_MX25_FLASH_SHUTDOWN_RX_PORT, SL_MX25_FLASH_SHUTDOWN_RX_PIN }, SL_GPIO_MODE_INPUT, 0);
+  sl_gpio_set_pin_mode(&(sl_gpio_t) {SL_MX25_FLASH_SHUTDOWN_SCLK_PORT, SL_MX25_FLASH_SHUTDOWN_SCLK_PIN }, SL_GPIO_MODE_PUSH_PULL, 1);
+  sl_gpio_set_pin_mode(&(sl_gpio_t) {SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN }, SL_GPIO_MODE_PUSH_PULL, 1);
+
+  GPIO->EUSARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].SCLKROUTE  = ((SL_MX25_FLASH_SHUTDOWN_SCLK_PORT << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT)
+                                                                        | (SL_MX25_FLASH_SHUTDOWN_SCLK_PIN  << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT));
+  GPIO->EUSARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].RXROUTE   = ((SL_MX25_FLASH_SHUTDOWN_RX_PORT << _GPIO_EUSART_RXROUTE_PORT_SHIFT)
+                                                                       | (SL_MX25_FLASH_SHUTDOWN_RX_PIN  << _GPIO_EUSART_RXROUTE_PIN_SHIFT));
+  GPIO->EUSARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].TXROUTE   = ((SL_MX25_FLASH_SHUTDOWN_TX_PORT << _GPIO_EUSART_TXROUTE_PORT_SHIFT)
+                                                                       | (SL_MX25_FLASH_SHUTDOWN_TX_PIN  << _GPIO_EUSART_TXROUTE_PIN_SHIFT));
+  GPIO->EUSARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].ROUTEEN   = (GPIO_EUSART_ROUTEEN_RXPEN
+                                                                       | GPIO_EUSART_ROUTEEN_TXPEN
+                                                                       | GPIO_EUSART_ROUTEEN_SCLKPEN);
+
+  // Wait for flash warm-up
+  sl_udelay_wait(800);               // wait for tVSL=800us
+
+  // Wake up flash in case the device is in deep power down mode already.
+  cs_low();
+  sl_udelay_wait(20);                  // wait for tCRDP=20us
+  cs_high();
+  sl_udelay_wait(35);                  // wait for tRDP=35us
+
+  // Chip select go low to start a flash command
+  cs_low();
+
+  // Deep Power Down Mode command (0xB9)
+#if defined(_SILICON_LABS_32B_SERIES_2)
+  EUSART_Spi_TxRx(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL, 0xB9);
+#else
+  sl_hal_eusart_spi_tx_rx(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL, 0xB9);
+#endif
+
+  // Chip select go high to end a flash command
+  cs_high();
+
+  // Deinit flash
+  sl_gpio_set_pin_mode(&(sl_gpio_t) {SL_MX25_FLASH_SHUTDOWN_TX_PORT, SL_MX25_FLASH_SHUTDOWN_TX_PIN }, SL_GPIO_MODE_DISABLED, 0);
+  sl_gpio_set_pin_mode(&(sl_gpio_t) {SL_MX25_FLASH_SHUTDOWN_RX_PORT, SL_MX25_FLASH_SHUTDOWN_RX_PIN }, SL_GPIO_MODE_DISABLED, 0);
+  sl_gpio_set_pin_mode(&(sl_gpio_t) {SL_MX25_FLASH_SHUTDOWN_SCLK_PORT, SL_MX25_FLASH_SHUTDOWN_SCLK_PIN }, SL_GPIO_MODE_DISABLED, 1);
+  sl_gpio_set_pin_mode(&(sl_gpio_t) {SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN }, SL_GPIO_MODE_DISABLED, 1);
+
+#if defined(_SILICON_LABS_32B_SERIES_2)
+  EUSART_Reset(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL);
+#else
+  sl_hal_eusart_reset(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL);
+#endif
+
+  GPIO->EUSARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].ROUTEEN  = _GPIO_EUSART_ROUTEEN_RESETVALUE;
+  GPIO->EUSARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].SCLKROUTE = _GPIO_EUSART_SCLKROUTE_RESETVALUE;
+  GPIO->EUSARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].RXROUTE  = _GPIO_EUSART_RXROUTE_RESETVALUE;
+  GPIO->EUSARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].TXROUTE  = _GPIO_EUSART_TXROUTE_RESETVALUE;
+
+  sl_clock_manager_disable_bus_clock(SL_MX25_FLASH_SHUTDOWN_SCLK);
+#endif
+}

Libs/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h

@@ -0,0 +1,857 @@
+/***************************************************************************//**
+ * @file
+ * @brief This file contains the type definitions for EFR32xG2x chip-specific
+ *   aspects of RAIL.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef  SLI_LIBRARY_BUILD
+
+// This file should not be included when doing SLI_LIBRARY_BUILDs
+
+#else//!SLI_LIBRARY_BUILD
+
+#ifndef __RAIL_CHIP_SPECIFIC_H_
+#if !defined(__RAIL_TYPES_H__) && !defined(DOXYGEN_SHOULD_SKIP_THIS)
+#warning rail_chip_specific.h should only be included by rail_types.h
+#include "rail_types.h" // Force rail_chip_specific.h only within rail_types.h
+#else // __RAIL_TYPES_H__
+/// Include guard
+#define __RAIL_CHIP_SPECIFIC_H_
+#include "sl_status.h"
+#include "rail_features.h"
+#ifdef RAIL_INTERNAL_BUILD
+#include "rail_chip_specific_internal.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+ * General Structures
+ *****************************************************************************/
+/**
+ * @addtogroup General_EFR32XG2X EFR32xG2x
+ * @ingroup General
+ * @{
+ * @brief Types specific to the EFR32xG2x for general configuration.
+ */
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+/**
+ * @def RAIL_EFR32XG21_STATE_BUFFER_BYTES
+ * @brief The EFR32xG21 series size needed for
+ *   \ref RAIL_StateBufferEntry_t::bufferBytes.
+ */
+#define RAIL_EFR32XG21_STATE_BUFFER_BYTES 592
+
+/**
+ * @def RAIL_EFR32XG22_STATE_BUFFER_BYTES
+ * @brief The EFR32xG22 series size needed for
+ *   \ref RAIL_StateBufferEntry_t::bufferBytes.
+ */
+#define RAIL_EFR32XG22_STATE_BUFFER_BYTES 608
+
+/**
+ * @def RAIL_EFR32XG23_STATE_BUFFER_BYTES
+ * @brief The EFR32xG23 series size needed for
+ *   \ref RAIL_StateBufferEntry_t::bufferBytes.
+ */
+#define RAIL_EFR32XG23_STATE_BUFFER_BYTES 616
+
+/**
+ * @def RAIL_EFR32XG24_STATE_BUFFER_BYTES
+ * @brief The EFR32xG24 series size needed for
+ *   \ref RAIL_StateBufferEntry_t::bufferBytes.
+ */
+#define RAIL_EFR32XG24_STATE_BUFFER_BYTES 632
+
+/**
+ * @def RAIL_EFR32XG25_STATE_BUFFER_BYTES
+ * @brief The EFR32xG25 series size needed for
+ *   \ref RAIL_StateBufferEntry_t::bufferBytes.
+ */
+#define RAIL_EFR32XG25_STATE_BUFFER_BYTES 632
+
+/**
+ * @def RAIL_EFR32XG26_STATE_BUFFER_BYTES
+ * @brief The EFR32xG26 series size needed for
+ *   \ref RAIL_StateBufferEntry_t::bufferBytes.
+ */
+#define RAIL_EFR32XG26_STATE_BUFFER_BYTES 632
+
+/**
+ * @def RAIL_EFR32XG27_STATE_BUFFER_BYTES
+ * @brief The EFR32xG27 series size needed for
+ *   \ref RAIL_StateBufferEntry_t::bufferBytes.
+ */
+#define RAIL_EFR32XG27_STATE_BUFFER_BYTES 608
+
+/**
+ * @def RAIL_EFR32XG28_STATE_BUFFER_BYTES
+ * @brief The EFR32xG28 series size needed for
+ *   \ref RAIL_StateBufferEntry_t::bufferBytes.
+ */
+#define RAIL_EFR32XG28_STATE_BUFFER_BYTES 624
+
+/**
+ * @def RAIL_EFR32XG29_STATE_BUFFER_BYTES
+ * @brief The EFR32XG29 series size needed for
+ *   \ref RAIL_StateBufferEntry_t::bufferBytes.
+ */
+#define RAIL_EFR32XG29_STATE_BUFFER_BYTES 608
+
+#ifndef RAIL_STATE_BUFFER_BYTES
+/**
+ * @def RAIL_STATE_BUFFER_BYTES
+ * @brief The size needed for \ref RAIL_StateBufferEntry_t::bufferBytes
+ *   on this platform for this radio. This compile-time size may be slightly
+ *   larger than what \ref RAIL_GetStateBufferSize() determines at run-time.
+ */
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1)
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG21_STATE_BUFFER_BYTES
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 2)
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG22_STATE_BUFFER_BYTES
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG23_STATE_BUFFER_BYTES
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG24_STATE_BUFFER_BYTES
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG25_STATE_BUFFER_BYTES
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 6)
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG26_STATE_BUFFER_BYTES
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG27_STATE_BUFFER_BYTES
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG28_STATE_BUFFER_BYTES
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG29_STATE_BUFFER_BYTES
+#else
+#define RAIL_STATE_BUFFER_BYTES 0 // Sate Doxygen
+#error "Unsupported platform!"
+#endif
+#endif //#ifndef RAIL_STATE_BUFFER_BYTES
+
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+/**
+ * @def RAIL_SEQ_IMAGE_1
+ * @brief A macro for the first sequencer image.
+ */
+#define RAIL_SEQ_IMAGE_1 1
+
+/**
+ * @def RAIL_SEQ_IMAGE_2
+ * @brief A macro for the second sequencer image.
+ */
+#define RAIL_SEQ_IMAGE_2 2
+
+#ifndef RAIL_INTERNAL_BUILD
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6))
+/**
+ * @def RAIL_SEQ_IMAGE_PA_10_DBM
+ * @brief A chip-specific macro for the sequencer image used on EFR32xG24 and EFR32xG26 OPNs
+ *   with a 10 dBm PA.
+ */
+#define RAIL_SEQ_IMAGE_PA_10_DBM RAIL_SEQ_IMAGE_1
+
+/**
+ * @def RAIL_SEQ_IMAGE_PA_20_DBM
+ * @brief A chip-specific macro for the sequencer image used on EFR32xG24 and EFR32xG26 OPNs
+ *   with a 20 dBm PA.
+ */
+#define RAIL_SEQ_IMAGE_PA_20_DBM RAIL_SEQ_IMAGE_2
+
+/**
+ * @def RAIL_SEQ_IMAGE_COUNT
+ * @brief A macro for the total number of sequencer images supported on the
+ *   platform.
+ */
+#define RAIL_SEQ_IMAGE_COUNT 2
+
+#else //((_SILICON_LABS_32B_SERIES_2_CONFIG != 4) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 6))
+
+/**
+ * @def RAIL_SEQ_IMAGE_DEFAULT
+ * @brief A chip-specific macro for the default sequencer image on platforms
+ *   that support only one sequencer image.
+ */
+#define RAIL_SEQ_IMAGE_DEFAULT RAIL_SEQ_IMAGE_1
+
+/**
+ * @def RAIL_SEQ_IMAGE_COUNT
+ * @brief A macro for the total number of sequencer images supported on the
+ *   platform.
+ */
+#define RAIL_SEQ_IMAGE_COUNT 1
+#endif //((_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6))
+#endif //RAIL_INTERNAL_BUILD
+
+/**
+ * @struct RAIL_RffpllConfig_t
+ * @brief Stores information relevant to the Radio-Friendly Frequency
+ *   Phase-Locked Loop (RFFPLL) for the PHY configuration currently loaded in
+ *   memory.
+ */
+typedef struct {
+  /** Divider X (Modem Clock), Divider Y (M33 System Clock), and Divider N (Feedback) values. */
+  uint32_t dividers;
+  /** Radio clock frequency in Hz. */
+  uint32_t radioFreqHz;
+  /** System clock frequency in Hz. */
+  uint32_t sysclkFreqHz;
+} RAIL_RffpllConfig_t;
+
+/**
+ * @def RAIL_RFFPLL_DIVIDERX_MASK
+ * @brief Bit mask for RFFPLL DIVX in \ref RAIL_RffpllConfig_t::dividers.
+ */
+#define RAIL_RFFPLL_DIVIDERX_MASK   0x000000FFUL
+
+/**
+ * @def RAIL_RFFPLL_DIVIDERX_SHIFT
+ * @brief Shift value for RFFPLL DIVX in \ref RAIL_RffpllConfig_t::dividers.
+ */
+#define RAIL_RFFPLL_DIVIDERX_SHIFT  0
+
+/**
+ * @def RAIL_RFFPLL_DIVIDERY_MASK
+ * @brief Bit mask for RFFPLL DIVY in \ref RAIL_RffpllConfig_t::dividers.
+ */
+#define RAIL_RFFPLL_DIVIDERY_MASK   0x0000FF00UL
+
+/**
+ * @def RAIL_RFFPLL_DIVIDERY_SHIFT
+ * @brief Shift value for RFFPLL DIVY in \ref RAIL_RffpllConfig_t::dividers.
+ */
+#define RAIL_RFFPLL_DIVIDERY_SHIFT  8
+
+/**
+ * @def RAIL_RFFPLL_DIVIDERN_MASK
+ * @brief Bit mask for RFFPLL DIVN in \ref RAIL_RffpllConfig_t::dividers.
+ */
+#define RAIL_RFFPLL_DIVIDERN_MASK   0x00FF0000UL
+
+/**
+ * @def RAIL_RFFPLL_DIVIDERN_SHIFT
+ * @brief Shift value for RFFPLL DIVN in \ref RAIL_RffpllConfig_t::dividers.
+ */
+#define RAIL_RFFPLL_DIVIDERN_SHIFT  16
+
+/**
+ * @typedef RAIL_TimerTick_t
+ * @brief Internal RAIL hardware timer tick that drives the RAIL timebase.
+ *   A tick is roughly 0.5 microseconds but it wraps somewhat before
+ *   0xFFFFFFFF giving a time range of about 17 minutes.
+ *
+ * @note \ref RAIL_TimerTicksToUs() can be used to convert the delta between
+ *   two \ref RAIL_TimerTick_t values to microseconds.
+ */
+typedef uint32_t RAIL_TimerTick_t;
+
+/**
+ * @def RAIL_GetTimerTick(timerTickType)
+ * @brief The RAIL hardware timer ticks value.
+ *
+ * @note timerTickType is added for compatibility reasons and is ignored here;
+ *   this gets the equivalent of \ref RAIL_TIMER_TICK_DEFAULT.
+ */
+#define RAIL_GetTimerTick(timerTickType) (*RAIL_TimerTick)
+
+/**
+ * A global pointer to the memory address of the 32-bit
+ * \ref RAIL_TimerTick_t internal RAIL hardware timer that drives
+ * the RAIL timebase.
+ * Equivalent to \ref RAIL_TimerTick_t for its granularity and range.
+ */
+extern const volatile uint32_t *RAIL_TimerTick;
+
+/**
+ * A global pointer to the memory address of the internal RAIL hardware timer
+ * that captures the latest RX packet reception time.
+ * See \ref RAIL_TimerTick_t for its granularity and range.
+ *
+ * @note This would not include the RX chain delay, so may not exactly
+ *   correspond to the \ref RAIL_Time_t packet timestamp available within
+ *   \ref RAIL_RxPacketDetails_t::timeReceived which reflects the actual
+ *   on-air time that the packet finished.
+ */
+extern const volatile uint32_t *RAIL_RxPacketTimestamp;
+
+/**
+ * Get elapsed time, in microseconds, between two \ref RAIL_TimerTick_t ticks.
+ *
+ * @param[in] startTick Tick recorded at the start of the operation.
+ * @param[in] endTick Tick recorded at the end of the operation.
+ * @return The elapsed time, in microseconds, between two timer ticks.
+ */
+RAIL_Time_t RAIL_TimerTicksToUs(RAIL_TimerTick_t startTick,
+                                RAIL_TimerTick_t endTick);
+
+/**
+ * Get \ref RAIL_TimerTick_t tick corresponding to a \ref RAIL_Time_t time.
+ *
+ * @param[in] microseconds Time in microseconds.
+ * @return The \ref RAIL_TimerTick_t tick corresponding to the
+ *   \ref RAIL_Time_t time.
+ */
+RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds);
+
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+/** @} */ // end of group General_EFR32XG2X
+
+/******************************************************************************
+ * Multiprotocol
+ *****************************************************************************/
+/**
+ * @addtogroup Multiprotocol_EFR32XG2X EFR32xG2x
+ * @ingroup Multiprotocol
+ * @{
+ * @brief EFR32xG2x-specific multiprotocol support defines.
+ */
+
+/**
+ * @def TRANSITION_TIME_US
+ * @brief Time it takes to take care of protocol switching.
+ */
+#if _SILICON_LABS_32B_SERIES_2_CONFIG > 1
+// XG22 + devices
+#define TRANSITION_TIME_US 510
+#else
+// XG21
+#define TRANSITION_TIME_US 500
+#endif
+
+/** @} */ // end of group Multiprotocol_EFR32XG2X
+
+/******************************************************************************
+ * Calibration
+ *****************************************************************************/
+/**
+ * @addtogroup Calibration_EFR32XG2X EFR32xG2x
+ * @ingroup Calibration
+ * @{
+ * @brief EFR32xG2x-specific Calibrations.
+ */
+
+/**
+ * @def RAIL_RF_PATHS_2P4GIG
+ * @brief Indicates the number of 2.4 GHz RF Paths suppported.
+ */
+#ifndef RAIL_RF_PATHS_2P4GIG
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6))
+#define RAIL_RF_PATHS_2P4GIG 2
+#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)   \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)   \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+#define RAIL_RF_PATHS_2P4GIG 1
+#else
+#define RAIL_RF_PATHS_2P4GIG 0
+#endif
+#endif//RAIL_RF_PATHS_2P4GHZ
+
+/**
+ * @def RAIL_RF_PATHS_SUBGIG
+ * @brief Indicates the number of Sub-GHz RF Paths supported.
+ */
+#ifndef RAIL_RF_PATHS_SUBGHZ
+#if _SILICON_LABS_32B_SERIES_2_CONFIG == 3
+#define RAIL_RF_PATHS_SUBGIG 2
+#elif  _SILICON_LABS_32B_SERIES_2_CONFIG == 5
+#define RAIL_RF_PATHS_SUBGIG 2
+#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 8
+#define RAIL_RF_PATHS_SUBGIG 1
+#else
+#define RAIL_RF_PATHS_SUBGIG 0
+#endif
+#endif//RAIL_RF_PATHS_SUBGHZ
+
+/**
+ * @def RAIL_RF_PATHS
+ * @brief Indicates the number of RF Paths supported.
+ */
+#define RAIL_RF_PATHS (RAIL_RF_PATHS_SUBGIG + RAIL_RF_PATHS_2P4GIG)
+
+#if     (RAIL_RF_PATHS > RAIL_MAX_RF_PATHS)
+#error "Update rail_types.h RAIL_MAX_RF_PATHS"
+#endif
+
+/**
+ * @def RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+ * @brief Indicates this version of RAIL supports IR calibration on multiple RF paths
+ * Needed for backwards compatibility.
+ */
+#if RAIL_RF_PATHS > 1
+#define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 1
+#else
+#ifdef  DOXYGEN_SHOULD_SKIP_THIS // Leave undefined except for doxygen
+#define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 0
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+#endif //RAIL_RF_PATHS
+
+/**
+ * @struct RAIL_ChannelConfigEntryAttr
+ * @brief A channel configuration entry attribute structure. Items listed
+ *  are designed to be altered and updated during run-time.
+ */
+struct RAIL_ChannelConfigEntryAttr {
+  /** IR calibration attributes specific to each channel configuration entry. */
+ #if     RAIL_SUPPORTS_OFDM_PA
+  RAIL_IrCalValues_t calValues;
+ #else//!RAIL_SUPPORTS_OFDM_PA
+  RAIL_RxIrCalValues_t calValues;
+ #endif//RAIL_SUPPORTS_OFDM_PA
+};
+
+/** @} */ // end of group Calibration_EFR32XG2X
+
+/******************************************************************************
+ * Transmit
+ *****************************************************************************/
+/**
+ * @addtogroup PA_EFR32XG2X EFR32xG2x
+ * @ingroup PA
+ * @{
+ * @brief Types specific to the EFR32xG2x for dealing with the on-chip PAs.
+ */
+
+#ifndef RAIL_TX_POWER_LEVEL_2P4_HP_MAX
+#if _SILICON_LABS_32B_SERIES_2_CONFIG == 1
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX     (180U)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN     (1U)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_MP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_MP_MAX     (90U)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_MP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_MP_MIN     (1U)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX     (64U)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN     (0U)
+#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6))
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_HP mode.
+ *  EFR32xG24: capable of 20dBm max output power has max powerlevel:180
+ *  EFR32xG24: capable of 10dBm max output power has max powerlevel:90
+ *  EFR32xG26: capable of 20dBm max output power has max powerlevel:180
+ *  EFR32xG26: capable of 10dBm max output power has max powerlevel:90
+ */
+#if defined (_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \
+  && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM > 10)
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX     (180U)
+#else
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX     (90U)
+#endif
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN     (0U)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX     (15U)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN     (0U)
+#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)   \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9))
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX     (127U)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN     (0U)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX     (15U)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN     (0U)
+#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 8
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX     (240)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN     (1U)
+#else //EFR32xG23
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX     (240)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN     (1U)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_MP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_MP_MAX     (RAIL_TX_POWER_LEVEL_2P4_HP_MAX)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_MP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_MP_MIN     (RAIL_TX_POWER_LEVEL_2P4_HP_MIN)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX     (RAIL_TX_POWER_LEVEL_2P4_HP_MAX)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN     (RAIL_TX_POWER_LEVEL_2P4_HP_MIN)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_LLP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_LLP_MAX     (RAIL_TX_POWER_LEVEL_2P4_HP_MAX)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4GIG_LLP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_LLP_MIN     (RAIL_TX_POWER_LEVEL_2P4_HP_MIN)
+#endif //_SILICON_LABS_32B_SERIES_2_CONFIG
+#endif //RAIL_TX_POWER_LEVEL_2P4_HP_MAX
+
+#if RAIL_SUPPORTS_SUBGHZ_BAND
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when using
+ * a Sub-GHz PA mode.
+ */
+#ifndef RAIL_SUBGIG_MAX
+#if _SILICON_LABS_32B_SERIES_2_CONFIG == 3 || _SILICON_LABS_32B_SERIES_2_CONFIG == 8
+#define RAIL_SUBGIG_MAX 240U
+#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 5
+#define RAIL_SUBGIG_MAX 79U
+#else
+#define RAIL_SUBGIG_MAX 0U
+#endif
+#endif//RAIL_SUBGIG_MAX
+
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when using
+ * a Sub-GHz PA mode.
+ */
+#define RAIL_SUBGIG_MIN 1U
+
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX (RAIL_SUBGIG_MAX)
+
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN (RAIL_SUBGIG_MIN)
+
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_MP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MAX (RAIL_SUBGIG_MAX)
+
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_MP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MIN (RAIL_SUBGIG_MIN)
+
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MAX (RAIL_SUBGIG_MAX)
+
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MIN (RAIL_SUBGIG_MIN)
+
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_LLP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MAX (RAIL_SUBGIG_MAX)
+
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_LLP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MIN (RAIL_SUBGIG_MIN)
+#endif //RAIL_SUPPORTS_SUBGHZ_BAND
+
+#if RAIL_SUPPORTS_OFDM_PA
+#if _SILICON_LABS_32B_SERIES_2_CONFIG == 5
+#define RAIL_OFDM_PA_MAX      204U
+#define RAIL_OFDM_PA_MULT     5U
+#define RAIL_OFDM_PA_MIN      0U
+#endif
+
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE mode.
+ */
+#define RAIL_TX_POWER_LEVEL_OFDM_PA_MAX (RAIL_OFDM_PA_MAX)
+
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE mode.
+ */
+#define RAIL_TX_POWER_LEVEL_OFDM_PA_MIN (RAIL_OFDM_PA_MIN)
+#endif //RAIL_SUPPORTS_OFDM_PA
+
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_HP_MAX      RAIL_TX_POWER_LEVEL_2P4_HP_MAX
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_HP_MIN      RAIL_TX_POWER_LEVEL_2P4_HP_MIN
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_MP_MAX      RAIL_TX_POWER_LEVEL_2P4_MP_MAX
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_MP_MIN      RAIL_TX_POWER_LEVEL_2P4_MP_MIN
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_LP_MAX      RAIL_TX_POWER_LEVEL_2P4_LP_MAX
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_LP_MIN      RAIL_TX_POWER_LEVEL_2P4_LP_MIN
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_MAX  RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_MIN  RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN
+
+/**
+ * The number of PA's on this chip (including Virtual PAs).
+ */
+#ifndef RAIL_NUM_PA
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9))
+#define RAIL_NUM_PA (2U)
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
+#define RAIL_NUM_PA (4U)
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)
+#define RAIL_NUM_PA (5U)
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define RAIL_NUM_PA (4U)
+#else
+#define RAIL_NUM_PA (3U)
+#endif
+#endif //#ifndef RAIL_NUM_PA
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+// Only those supported per-platform are defined, for use with #ifdef in
+// apps or librail code.
+#if     RAIL_SUPPORTS_2P4GHZ_BAND
+#define RAIL_TX_POWER_MODE_2P4GIG_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HP)
+#define RAIL_TX_POWER_MODE_2P4_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HP)
+#if     _SILICON_LABS_32B_SERIES_2_CONFIG == 1
+#define RAIL_TX_POWER_MODE_2P4GIG_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_MP)
+#define RAIL_TX_POWER_MODE_2P4_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_MP)
+#endif//_SILICON_LABS_32B_SERIES_2_CONFIG == 1
+#if     ((_SILICON_LABS_32B_SERIES_2_CONFIG != 3) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 8))
+#define RAIL_TX_POWER_MODE_2P4GIG_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_LP)
+#define RAIL_TX_POWER_MODE_2P4_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_LP)
+#endif//((_SILICON_LABS_32B_SERIES_2_CONFIG != 3) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 8))
+#define RAIL_TX_POWER_MODE_2P4GIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HIGHEST)
+#define RAIL_TX_POWER_MODE_2P4_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HIGHEST)
+#endif//RAIL_SUPPORTS_2P4GHZ_BAND
+
+#if     RAIL_SUPPORTS_SUBGHZ_BAND
+#if     RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+#define RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE)
+#else//!RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+#define RAIL_TX_POWER_MODE_SUBGIG_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_HP)
+#define RAIL_TX_POWER_MODE_SUBGIG ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG)
+#define RAIL_TX_POWER_MODE_SUBGIG_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_MP)
+#define RAIL_TX_POWER_MODE_SUBGIG_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_LP)
+#define RAIL_TX_POWER_MODE_SUBGIG_LLP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_LLP)
+#endif//RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+#define RAIL_TX_POWER_MODE_SUBGIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_HIGHEST)
+#endif//RAIL_SUPPORTS_SUBGHZ_BAND
+#if     RAIL_SUPPORTS_OFDM_PA
+#if     RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+#define RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE)
+#define RAIL_TX_POWER_MODE_OFDM_PA  ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA)
+#endif//RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+#endif//RAIL_SUPPORTS_OFDM_PA
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+/** Convenience macro for any mapping table mode. */
+#define RAIL_POWER_MODE_IS_ANY_DBM_POWERSETTING_MAPPING_TABLE(x) \
+  (((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE)        \
+   || ((x) == RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE))
+
+/** Convenience macro to check if the power mode supports raw setting. */
+#define RAIL_POWER_MODE_SUPPORTS_RAW_SETTING(x)           \
+  (((x) != RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \
+   && ((x) != RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE))
+/** @} */ // end of group PA_EFR32XG2X
+
+/******************************************************************************
+ * RX Channel Hopping
+ *****************************************************************************/
+/**
+ * @addtogroup Rx_Channel_Hopping_EFR32XG2X EFR32xG2x
+ * @ingroup Rx_Channel_Hopping
+ * @{
+ * @brief EFR32xG2x-specific RX channel hopping.
+ */
+
+#if _SILICON_LABS_32B_SERIES_2_CONFIG == 8
+/// The static amount of memory needed per channel for channel hopping, measured
+/// in 32 bit words, regardless of the size of radio configuration structures.
+#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (65U)
+#else
+/// The static amount of memory needed per channel for channel hopping, measured
+/// in 32 bit words, regardless of the size of radio configuration structures.
+#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (56U)
+#endif
+
+#if     (RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL \
+         > RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE)
+#error "Update rail_types.h RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE"
+#endif
+
+/** @} */  // end of group Rx_Channel_Hopping_EFR32XG2X
+
+/******************************************************************************
+ * Sleep Structures
+ *****************************************************************************/
+/**
+ * @addtogroup Sleep_EFR32XG2X EFR32xG2x
+ * @ingroup Sleep
+ * @{
+ * @brief EFR32xG2x-specific Sleeping.
+ */
+
+/// Default PRS channel to use when configuring sleep
+#define RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT  (7U)
+
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9))
+/// Default RTCC channel to use when configuring sleep
+#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (1U)
+#else
+/// Default RTCC channel to use when configuring sleep
+#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (0U)
+#endif
+
+/** @} */ // end of group Sleep_EFR32XG2X
+
+/******************************************************************************
+ * State Transitions
+ *****************************************************************************/
+/**
+ * @addtogroup State_Transitions_EFR32XG2X EFR32xG2x
+ * @ingroup State_Transitions
+ * @{
+ * @brief EFR32xG2x-specific State Transitions.
+ */
+
+/**
+ * @def RAIL_MINIMUM_TRANSITION_US
+ * @brief The minimum value for a consistent RAIL transition
+ * @note Transitions may need to be slower than this when using longer
+ *   \ref RAIL_TxPowerConfig_t::rampTime values
+ */
+#define RAIL_MINIMUM_TRANSITION_US (100U)
+
+/**
+ * @def RAIL_MAXIMUM_TRANSITION_US
+ * @brief The maximum value for a consistent RAIL transition
+ */
+#define RAIL_MAXIMUM_TRANSITION_US (1000000U)
+
+/**
+ * Internal Radio State type mapping for EFR32 chips.
+ */
+typedef RAIL_RadioStateEfr32_t RAIL_RacRadioState_t;
+
+/** @} */ // end of group State_Transitions_EFR32XG2X
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__RAIL_TYPES_H__
+
+#endif //__RAIL_CHIP_SPECIFIC_H_
+
+#endif //SLI_LIBRARY_BUILD

Libs/platform/radio/rail_lib/common/rail_assert_error_codes.h

@@ -0,0 +1,445 @@
+/***************************************************************************//**
+ * @file
+ * @brief Definition of error codes that occur in RAIL.
+ *   This file is purely informational and optional -
+ *   it need not be included even if rail_assert libraries are included.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __RAIL_ASSERT_ERROR_CODES_H__
+#define __RAIL_ASSERT_ERROR_CODES_H__
+
+#include "rail_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup Assertions
+ * @{
+ */
+
+/**
+ * Enumeration of all possible error codes from RAIL_ASSERT.
+ */
+RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t)
+{
+  /** Appended info missing from RX packet. */
+  RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING = 0,
+  /** Receive FIFO too small for IR calibration. */
+  RAIL_ASSERT_FAILED_RX_FIFO_BYTES = 1,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_2 = 2,
+  /** Receive FIFO entry has invalid status. */
+  RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS = 3,
+  /** Receive FIFO entry bad packet length. */
+  RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH = 4,
+  /** Unable to configure radio for IR calibration. */
+  RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR = 5,
+  /** Reached unexpected state while handling RX FIFO events. */
+  RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO = 6,
+  /** Reached unexpected state while handling RXLEN FIFO events. */
+  RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO = 7,
+  /** Reached unexpected state while handling TX FIFO events. */
+  RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO = 8,
+  /** Reached unexpected state while handling TX ACK FIFO events. */
+  RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO = 9,
+  /** Invalid memory region accessed. */
+  RAIL_ASSERT_INVALID_MEMORY_ACCESS = 10,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_11 = 11,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_12 = 12,
+  /** Error synchronizing the RAIL timebase after sleep. */
+  RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP = 13,
+  /** VCO frequency outside supported range. */
+  RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY = 14,
+  /** Radio active while changing channels. */
+  RAIL_ASSERT_FAILED_RAC_STATE = 15,
+  /** Invalid Synth VCOCTRL field calculation. */
+  RAIL_ASSERT_FAILED_SYNTH_INVALID_VCOCTRL = 16,
+  /** Nested attempt to lock the sequencer. */
+  RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK = 17,
+  /** RSSI averaging enabled without a valid callback. */
+  RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE = 18,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_19 = 19,
+  /** Unable to seed radio pseudo random number generator. */
+  RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED = 20,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_21 = 21,
+  /** Invalid timer channel specified. */
+  RAIL_ASSERT_FAILED_PROTIMER_CHANNEL = 22,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_23 = 23,
+  /** LBT config exceeds register size. */
+  RAIL_ASSERT_FAILED_BASECNTTOP = 24,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_25 = 25,
+  /** Could not synchronize RAIL timebase with the RTC. */
+  RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED = 26,
+  /** Clock source not ready. */
+  RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY = 27,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_28 = 28,
+  /** NULL was supplied as a RAIL_Handle_t argument. */
+  RAIL_ASSERT_NULL_HANDLE = 29,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_30 = 30,
+  /** API improperly called while protocol inactive. */
+  RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG = 31,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_32 = 32,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_33 = 33,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_34 = 34,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_35 = 35,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_36 = 36,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_37 = 37,
+  /** Failed to enable synth for transmit. */
+  RAIL_ASSERT_FAILED_TX_SYNTH_ENABLE = 38,
+  /** This function is deprecated and must not be called. */
+  RAIL_ASSERT_DEPRECATED_FUNCTION = 39,
+  /** Multiprotocol task started with no event to run. */
+  RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT = 40,
+  /** Invalid interrupt enabled. */
+  RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED = 41,
+  /** Invalid assert, no longer used. */
+  RAIL_ASSERT_UNUSED_42 = 42,
+  /** Division by zero. */
+  RAIL_ASSERT_DIVISION_BY_ZERO = 43,
+  /** Function cannot be called without access to the hardware. */
+  RAIL_ASSERT_CANT_USE_HARDWARE = 44,
+  /** Pointer parameter was passed as NULL. */
+  RAIL_ASSERT_NULL_PARAMETER = 45,
+  /** Secure Element fault */
+  RAIL_ASSERT_SECURE_ELEMENT_FAULT = 46,
+  /** Synth radio config buffer for channel hopping too small. */
+  RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER = 47,
+  /** Buffer provided for RX Channel Hopping is too small. */
+  RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT = 48,
+  /** Invalid action was attempted on a module. */
+  RAIL_ASSERT_INVALID_MODULE_ACTION = 49,
+  /** The radio config for this channel is not compatible with channel hopping. */
+  RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG = 50,
+  /** Channel change failed. */
+  RAIL_ASSERT_CHANNEL_CHANGE_FAILED = 51,
+  /** Attempted to read invalid register. */
+  RAIL_ASSERT_INVALID_REGISTER = 52,
+  /** CP/DMA Invalid error. */
+  RAIL_ASSERT_CP_DMA_INTERNAL_GENERIC_ERROR = 53,
+  /** DMP radio config caching failed. */
+  RAIL_ASSERT_CACHE_CONFIG_FAILED = 54,
+  /** NULL was supplied as a RAIL_StateTransitions_t argument. */
+  RAIL_ASSERT_NULL_TRANSITIONS = 55,
+  /** LDMA transfer failed. */
+  RAIL_ASSERT_BAD_LDMA_TRANSFER = 56,
+  /** Attempted to wake up with invalid RTCC sync data. */
+  RAIL_ASSERT_INVALID_RTCC_SYNC_VALUES = 57,
+  /** Radio sequencer hit a fault condition. */
+  RAIL_ASSERT_SEQUENCER_FAULT = 58,
+  /** Bus fault. */
+  RAIL_ASSERT_BUS_ERROR = 59,
+  /** The current radio config cannot be used with packet filtering. */
+  RAIL_ASSERT_INVALID_FILTERING_CONFIG = 60,
+  /** Retiming configuration error. */
+  RAIL_ASSERT_RETIMING_CONFIG = 61,
+  /** TX CRC configuration is corrupt. */
+  RAIL_ASSERT_FAILED_TX_CRC_CONFIG = 62,
+  /** The current PA config does not allow for this operation. */
+  RAIL_ASSERT_INVALID_PA_OPERATION = 63,
+  /** The sequencer selected an invalid PA. */
+  RAIL_ASSERT_SEQ_INVALID_PA_SELECTED = 64,
+  /** Invalid/unsupported channel config. */
+  RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG = 65,
+  /** Radio Calculator configuration HFXO frequency mismatch with chip */
+  RAIL_ASSERT_INVALID_XTAL_FREQUENCY = 66,
+  /** Internal error. */
+  RAIL_ASSERT_INTERNAL_GENERIC_ERROR = 67,
+  /** Software modem image does not support requested modulation  */
+  RAIL_ASSERT_UNSUPPORTED_SOFTWARE_MODEM_MODULATION = 68,
+  /** Failed to disable RTCC synchronization. */
+  RAIL_ASSERT_FAILED_RTCC_SYNC_STOP = 69,
+  /** Multitimer linked list corrupted. */
+  RAIL_ASSERT_FAILED_MULTITIMER_CORRUPT = 70,
+  /** Unable to configure radio for temperature calibration. */
+  RAIL_ASSERT_FAILED_TEMPCAL_ERROR = 71,
+  /** Invalid VDET configuration. */
+  RAIL_ASSERT_INVALID_VDET_CONFIGURATION = 72,
+  /** Invalid RFFPLL configuration. */
+  RAIL_ASSERT_INVALID_RFFPLL_CONFIGURATION = 73,
+  /** Secure access fault. */
+  RAIL_ASSERT_SECURE_ACCESS_FAULT = 74,
+  /** SYSRTC0 not running. */
+  RAIL_ASSERT_FAILED_SYSRTC0_NOT_RUNNING = 75,
+  /** Radio Configurator not updated. */
+  RAIL_ASSERT_RADIO_CONFIG_NOT_UP_TO_DATE = 76,
+  /** Failed to set the event for configurable RSSI threshold. */
+  RAIL_ASSERT_FAILED_RSSI_THRESHOLD = 77,
+  /** Intended and actual Z-Wave region configuration mismatch. */
+  RAIL_ASSERT_INCORRECT_ZWAVE_REGION = 78,
+  /** Attempted to sleep with stale RTCC synchronization data */
+  RAIL_ASSERT_FAILED_RTCC_SYNC_STALE_DATA = 79,
+  /** Attempted to clear LOG2X4 with a DEC1 value not equal to 0 */
+  RAIL_ASSERT_INVALID_LOG2X4_CLEAR_CONDITION = 80,
+  /** Failed to complete DMA write */
+  RAIL_ASSERT_FAILED_DMA_WRITE_INCOMPLETE = 81,
+  /** RAIL does not support this Radio Calculator configuration */
+  RAIL_ASSERT_CALCULATOR_NOT_SUPPORTED = 82,
+  /** Invalid binary image was loaded onto the sequencer */
+  RAIL_ASSERT_INVALID_SEQUENCER_IMAGE = 83,
+  /** No common or protocol image selected to be loaded onto the sequencer */
+  RAIL_ASSERT_MISSING_SEQUENCER_IMAGE = 84,
+  /** Software modem image invalid or missing */
+  RAIL_ASSERT_INVALID_OR_MISSING_SOFTWARE_MODEM_IMAGE = 85,
+  /** The sequencer user generated error. */
+  RAIL_ASSERT_SEQ_USER_SEQUENCER_GENERIC_ERROR = 86,
+};
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+#define RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING               ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING)
+#define RAIL_ASSERT_FAILED_RX_FIFO_BYTES                       ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RX_FIFO_BYTES)
+#define RAIL_ASSERT_UNUSED_2                                   ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_2)
+#define RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS          ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS)
+#define RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH                   ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH)
+#define RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR)
+#define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO            ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO)
+#define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO         ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO)
+#define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO            ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO)
+#define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO         ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO)
+#define RAIL_ASSERT_INVALID_MEMORY_ACCESS                      ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_MEMORY_ACCESS)
+#define RAIL_ASSERT_UNUSED_11                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_11)
+#define RAIL_ASSERT_UNUSED_12                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_12)
+#define RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP                    ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP)
+#define RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY                 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY)
+#define RAIL_ASSERT_FAILED_RAC_STATE                           ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RAC_STATE)
+#define RAIL_ASSERT_FAILED_SYNTH_INVALID_VCOCTRL               ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYNTH_INVALID_VCOCTRL)
+#define RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK               ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK)
+#define RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE                   ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE)
+#define RAIL_ASSERT_UNUSED_19                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_19)
+#define RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED                ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED)
+#define RAIL_ASSERT_UNUSED_21                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_21)
+#define RAIL_ASSERT_FAILED_PROTIMER_CHANNEL                    ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_PROTIMER_CHANNEL)
+#define RAIL_ASSERT_UNUSED_23                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_23)
+#define RAIL_ASSERT_FAILED_BASECNTTOP                          ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_BASECNTTOP)
+#define RAIL_ASSERT_UNUSED_25                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_25)
+#define RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED                    ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED)
+#define RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY              ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY)
+#define RAIL_ASSERT_UNUSED_28                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_28)
+#define RAIL_ASSERT_NULL_HANDLE                                ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_HANDLE)
+#define RAIL_ASSERT_UNUSED_30                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_30)
+#define RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG                    ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG)
+#define RAIL_ASSERT_UNUSED_32                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_32)
+#define RAIL_ASSERT_UNUSED_33                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_33)
+#define RAIL_ASSERT_UNUSED_34                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_34)
+#define RAIL_ASSERT_UNUSED_35                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_35)
+#define RAIL_ASSERT_UNUSED_36                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_36)
+#define RAIL_ASSERT_UNUSED_37                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_37)
+#define RAIL_ASSERT_FAILED_TX_SYNTH_ENABLE                     ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_TX_SYNTH_ENABLE)
+#define RAIL_ASSERT_DEPRECATED_FUNCTION                        ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_DEPRECATED_FUNCTION)
+#define RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT                     ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT)
+#define RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED           ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED)
+#define RAIL_ASSERT_UNUSED_42                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_42)
+#define RAIL_ASSERT_DIVISION_BY_ZERO                           ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_DIVISION_BY_ZERO)
+#define RAIL_ASSERT_CANT_USE_HARDWARE                          ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CANT_USE_HARDWARE)
+#define RAIL_ASSERT_NULL_PARAMETER                             ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_PARAMETER)
+#define RAIL_ASSERT_SECURE_ELEMENT_FAULT                       ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SECURE_ELEMENT_FAULT)
+#define RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER            ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER)
+#define RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT           ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT)
+#define RAIL_ASSERT_INVALID_MODULE_ACTION                      ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_MODULE_ACTION)
+#define RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG       ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG)
+#define RAIL_ASSERT_CHANNEL_CHANGE_FAILED                      ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_CHANGE_FAILED)
+#define RAIL_ASSERT_INVALID_REGISTER                           ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_REGISTER)
+#define RAIL_ASSERT_CP_DMA_INTERNAL_GENERIC_ERROR              ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CP_DMA_INTERNAL_GENERIC_ERROR)
+#define RAIL_ASSERT_CACHE_CONFIG_FAILED                        ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CACHE_CONFIG_FAILED)
+#define RAIL_ASSERT_NULL_TRANSITIONS                           ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_TRANSITIONS)
+#define RAIL_ASSERT_BAD_LDMA_TRANSFER                          ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_BAD_LDMA_TRANSFER)
+#define RAIL_ASSERT_INVALID_RTCC_SYNC_VALUES                   ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_RTCC_SYNC_VALUES)
+#define RAIL_ASSERT_SEQUENCER_FAULT                            ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SEQUENCER_FAULT)
+#define RAIL_ASSERT_BUS_ERROR                                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_BUS_ERROR)
+#define RAIL_ASSERT_INVALID_FILTERING_CONFIG                   ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_FILTERING_CONFIG)
+#define RAIL_ASSERT_RETIMING_CONFIG                            ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_RETIMING_CONFIG)
+#define RAIL_ASSERT_FAILED_TX_CRC_CONFIG                       ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_TX_CRC_CONFIG)
+#define RAIL_ASSERT_INVALID_PA_OPERATION                       ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_PA_OPERATION)
+#define RAIL_ASSERT_SEQ_INVALID_PA_SELECTED                    ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SEQ_INVALID_PA_SELECTED)
+#define RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG              ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG)
+#define RAIL_ASSERT_INVALID_XTAL_FREQUENCY                     ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_XTAL_FREQUENCY)
+#define RAIL_ASSERT_INTERNAL_GENERIC_ERROR                     ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INTERNAL_GENERIC_ERROR)
+#define RAIL_ASSERT_UNSUPPORTED_SOFTWARE_MODEM_MODULATION      ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNSUPPORTED_SOFTWARE_MODEM_MODULATION)
+#define RAIL_ASSERT_FAILED_RTCC_SYNC_STOP                      ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_SYNC_STOP)
+#define RAIL_ASSERT_FAILED_MULTITIMER_CORRUPT                  ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_MULTITIMER_CORRUPT)
+#define RAIL_ASSERT_FAILED_TEMPCAL_ERROR                       ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_TEMPCAL_ERROR)
+#define RAIL_ASSERT_INVALID_VDET_CONFIGURATION                 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_VDET_CONFIGURATION)
+#define RAIL_ASSERT_INVALID_RFFPLL_CONFIGURATION               ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_RFFPLL_CONFIGURATION)
+#define RAIL_ASSERT_SECURE_ACCESS_FAULT                        ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SECURE_ACCESS_FAULT)
+#define RAIL_ASSERT_FAILED_SYSRTC0_NOT_RUNNING                 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYSRTC0_NOT_RUNNING)
+#define RAIL_ASSERT_RADIO_CONFIG_NOT_UP_TO_DATE                ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_RADIO_CONFIG_NOT_UP_TO_DATE)
+#define RAIL_ASSERT_FAILED_RSSI_THRESHOLD                      ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RSSI_THRESHOLD)
+#define RAIL_ASSERT_INCORRECT_ZWAVE_REGION                     ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INCORRECT_ZWAVE_REGION)
+#define RAIL_ASSERT_FAILED_RTCC_SYNC_STALE_DATA                ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_SYNC_STALE_DATA)
+#define RAIL_ASSERT_INVALID_LOG2X4_CLEAR_CONDITION             ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_LOG2X4_CLEAR_CONDITION)
+#define RAIL_ASSERT_FAILED_DMA_WRITE_INCOMPLETE                ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_DMA_WRITE_INCOMPLETE)
+#define RAIL_ASSERT_CALCULATOR_NOT_SUPPORTED                   ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CALCULATOR_NOT_SUPPORTED)
+#define RAIL_ASSERT_INVALID_SEQUENCER_IMAGE                    ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_SEQUENCER_IMAGE)
+#define RAIL_ASSERT_MISSING_SEQUENCER_IMAGE                    ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_MISSING_SEQUENCER_IMAGE)
+#define RAIL_ASSERT_INVALID_OR_MISSING_SOFTWARE_MODEM_IMAGE    ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_OR_MISSING_SOFTWARE_MODEM_IMAGE)
+#define RAIL_ASSERT_SEQ_USER_SEQUENCER_GENERIC_ERROR           ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SEQ_USER_SEQUENCER_GENERIC_ERROR)
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+/// Use this define to create an array of error messages that map to the codes
+/// in \ref RAIL_AssertErrorCodes_t. You can use these to print slightly more
+/// detailed error strings related to a particular assert error code if desired.
+/// For example, you could implement your assert failed callback as follows to
+/// make use of this.
+/// @code{.c}
+/// void RAILCb_AssertFailed(RAIL_Handle_t railHandle, RAIL_AssertErrorCodes_t errorCode)
+/// {
+///   static const char* railErrorMessages[] = RAIL_ASSERT_ERROR_MESSAGES;
+///   const char *errorMessage = "Unknown";
+///
+///   // If this error code is within the range of known error messages then use
+///   // the appropriate error message.
+///   if (errorCode < (sizeof(railErrorMessages) / sizeof(char*))) {
+///     errorMessage = railErrorMessages[errorCode];
+///   }
+///   printf("RAIL ASSERT %u: %s\n", errorCode, errorMessage);
+///
+///   // Reset the chip since an assert is a fatal error
+///   NVIC_SystemReset();
+/// }
+/// @endcode
+///
+#define RAIL_ASSERT_ERROR_MESSAGES {                                                   \
+    /* 0*/ "Appended info missing from RX packet",                                     \
+    /* 1*/ "Receive FIFO too small for IR calibration",                                \
+    /* 2*/ "Invalid assert, no longer used",                                           \
+    /* 3*/ "Receive FIFO entry has invalid status",                                    \
+    /* 4*/ "Receive FIFO entry bad packet length",                                     \
+    /* 5*/ "Unable to configure radio for IR calibration",                             \
+    /* 6*/ "Reached unexpected state while handling RX FIFO events",                   \
+    /* 7*/ "Reached unexpected state while handling RXLEN FIFO events",                \
+    /* 8*/ "Reached unexpected state while handling TX FIFO events",                   \
+    /* 9*/ "Reached unexpected state while handling TX ACK FIFO events",               \
+    /*10*/ "Invalid memory region accessed",                                           \
+    /*11*/ "Invalid assert, no longer used",                                           \
+    /*12*/ "Invalid assert, no longer used",                                           \
+    /*13*/ "Error synchronizing the RAIL timebase after sleep",                        \
+    /*14*/ "VCO frequency outside supported range",                                    \
+    /*15*/ "Radio active while changing channels",                                     \
+    /*16*/ "Invalid Synth VCOCTRL field calculation",                                  \
+    /*17*/ "Nested attempt to lock the sequencer",                                     \
+    /*18*/ "RSSI averaging enabled without a valid callback",                          \
+    /*19*/ "Invalid assert, no longer used",                                           \
+    /*20*/ "Unable to seed radio pseudo random number generator",                      \
+    /*21*/ "Invalid assert, no longer used",                                           \
+    /*22*/ "Invalid timer channel specified",                                          \
+    /*23*/ "Invalid assert, no longer used",                                           \
+    /*24*/ "LBT config exceeds register size",                                         \
+    /*25*/ "Invalid assert, no longer used",                                           \
+    /*26*/ "Could not synchronize RAIL timebase with the RTC",                         \
+    /*27*/ "Clock source not ready",                                                   \
+    /*28*/ "Invalid assert, no longer used",                                           \
+    /*29*/ "NULL was supplied as a RAIL_Handle_t argument",                            \
+    /*30*/ "Invalid assert, no longer used",                                           \
+    /*31*/ "API improperly called while protocol inactive",                            \
+    /*32*/ "Invalid assert, no longer used",                                           \
+    /*33*/ "Invalid assert, no longer used",                                           \
+    /*34*/ "Invalid assert, no longer used",                                           \
+    /*35*/ "Invalid assert, no longer used",                                           \
+    /*36*/ "Invalid assert, no longer used",                                           \
+    /*37*/ "Invalid assert, no longer used",                                           \
+    /*38*/ "Failed to enable synth for transmit.",                                     \
+    /*39*/ "This function is deprecated and must not be called",                       \
+    /*40*/ "Multiprotocol task started with no event to run",                          \
+    /*41*/ "Invalid interrupt enabled",                                                \
+    /*42*/ "Invalid assert, no longer used",                                           \
+    /*43*/ "Division by zero",                                                         \
+    /*44*/ "Function cannot be called without access to the hardware",                 \
+    /*45*/ "Pointer parameter was passed as NULL",                                     \
+    /*46*/ "Secure Element fault",                                                     \
+    /*47*/ "Synth radio config buffer for channel hopping too small",                  \
+    /*48*/ "Buffer provided for RX Channel Hopping is too small",                      \
+    /*49*/ "Invalid action was attempted on a module",                                 \
+    /*50*/ "The radio config for this channel is not compatible with channel hopping", \
+    /*51*/ "Channel change failed",                                                    \
+    /*52*/ "Attempted to read invalid register",                                       \
+    /*53*/ "CP/DMA Generic internal error",                                            \
+    /*54*/ "DMP radio config caching failed",                                          \
+    /*55*/ "NULL was supplied as a RAIL_StateTransitions_t argument",                  \
+    /*56*/ "LDMA transfer failed",                                                     \
+    /*57*/ "Attempted to wake up with invalid RTCC sync data",                         \
+    /*58*/ "Radio sequencer hit a fault condition",                                    \
+    /*59*/ "Bus fault",                                                                \
+    /*60*/ "The current radio config cannot be used with packet filtering",            \
+    /*61*/ "Retiming configuration error",                                             \
+    /*62*/ "TX CRC configuration is corrupt",                                          \
+    /*63*/ "The current PA config does not allow for this operation",                  \
+    /*64*/ "The sequencer selected an invalid PA",                                     \
+    /*65*/ "Invalid/unsupported channel config",                                       \
+    /*66*/ "Radio Calculator configuration HFXO frequency mismatch with chip",         \
+    /*67*/ "Generic internal error",                                                   \
+    /*68*/ "Software modem image does not support requested modulation",               \
+    /*69*/ "Failed to disable RTCC synchronization",                                   \
+    /*70*/ "Multitimer linked list corrupted",                                         \
+    /*71*/ "Unable to configure radio for temperature calibration",                    \
+    /*72*/ "Invalid VDET configuration",                                               \
+    /*73*/ "PHY and System RFFPLL settings do not match",                              \
+    /*74*/ "Secure access fault",                                                      \
+    /*75*/ "SYSRTC0 not running",                                                      \
+    /*76*/ "Radio Configurator not updated",                                           \
+    /*77*/ "Failed to set the event for configurable RSSI threshold",                  \
+    /*78*/ "Intended and actual Z-Wave region configuration mismatch",                 \
+    /*79*/ "Attempted to sleep with stale RTCC synchronization data",                  \
+    /*80*/ "Attempted to clear LOG2X4 with a DEC1 value not equal to 0",               \
+    /*81*/ "Failed to complete DMA write",                                             \
+    /*82*/ "RAIL does not support this Radio Calculator configuration",                \
+    /*83*/ "Invalid binary image loaded on sequencer",                                 \
+    /*84*/ "No common or protocol image selected to be loaded onto the sequencer",     \
+    /*85*/ "Software modem image invalid or missing",                                  \
+    /*86*/ "The sequencer user generated error",                                       \
+}
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Undocumented RAIL 2.x internal symbol renaming
+#define RAIL_AssertErrorCode  sli_rail_assert_error_code
+#define RAIL_AssertLineNumber sli_rail_assert_line_number
+#define RAIL_AssertRailHandle sli_rail_assert_rail_handle
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+/** @} */ // end of Assertions
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __RAIL_ASSERT_ERROR_CODES_H__

Libs/platform/radio/rail_lib/common/rail_features.h

@@ -0,0 +1,952 @@
+/***************************************************************************//**
+ * @file
+ * @brief Auxiliary header for the RAIL library. Includes consistent definitions
+ *   of features available across different chips.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __RAIL_FEATURES_H__
+#define __RAIL_FEATURES_H__
+
+#include "em_device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup RAIL_API
+ * @{
+ */
+
+/******************************************************************************
+ * RAIL Features
+ *****************************************************************************/
+/**
+ * @addtogroup Features
+ * @brief Overview of support for various features across hardware platforms.
+ *   These defines can be used at compile time to determine which
+ *   features are available on your platform. However, keep in mind that
+ *   these defines hold true for chip families. Your specific part
+ *   may have further restrictions (band limitations, power amplifier
+ *   restrictions, and so on) on top of those listed below, for which
+ *   runtime RAIL_*Supports*() APIs can be used to check availability
+ *   on a particular chip (after \ref RAIL_Init() has been called).
+ *   In general, an attempt to call an API that is not supported on your
+ *   chip family as listed below will result in a
+ *   \ref RAIL_STATUS_INVALID_CALL.
+ * @{
+ */
+
+/// Boolean to indicate whether the selected chip supports both Sub-GHz and 2.4 GHz bands.
+/// See also runtime refinement \ref RAIL_SupportsDualBand().
+#if ((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \
+  || ((FEAT_RF_2G4 == 1) && (FEAT_RF_SUBG == 1)))
+#define RAIL_SUPPORTS_DUAL_BAND 1
+#else
+#define RAIL_SUPPORTS_DUAL_BAND 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_DUAL_BAND.
+#define RAIL_FEAT_DUAL_BAND_RADIO RAIL_SUPPORTS_DUAL_BAND
+
+/// Boolean to indicate whether the selected chip supports the 2.4 GHz band.
+/// See also runtime refinement \ref RAIL_Supports2p4GHzBand().
+#if (((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \
+  || (_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_2G4HZ))    \
+  || (FEAT_RF_2G4 == 1))
+#define RAIL_SUPPORTS_2P4GHZ_BAND 1
+#else
+#define RAIL_SUPPORTS_2P4GHZ_BAND 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_2P4GHZ_BAND.
+#define RAIL_FEAT_2G4_RADIO RAIL_SUPPORTS_2P4GHZ_BAND
+
+/// Boolean to indicate whether the selected chip supports Sub-GHz bands.
+/// See also runtime refinement \ref RAIL_SupportsSubGHzBand().
+#if (((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \
+  || (_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_SUBGHZ))   \
+  || (FEAT_RF_SUBG == 1))
+#define RAIL_SUPPORTS_SUBGHZ_BAND 1
+#else
+#define RAIL_SUPPORTS_SUBGHZ_BAND 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_SUBGHZ_BAND.
+#define RAIL_FEAT_SUBGIG_RADIO RAIL_SUPPORTS_SUBGHZ_BAND
+
+/// Boolean to indicate whether the selected chip supports OFDM PA.
+/// See also runtime refinement \ref RAIL_SupportsOFDMPA().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define RAIL_SUPPORTS_OFDM_PA 1
+#else
+#define RAIL_SUPPORTS_OFDM_PA 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// bit masked address filtering.
+/// See also runtime refinement \ref RAIL_SupportsAddrFilterAddressBitMask().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)   \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300))
+#define RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK 1
+#else
+#define RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// address filter mask information for incoming packets in
+/// \ref RAIL_RxPacketInfo_t::filterMask and
+/// \ref RAIL_IEEE802154_Address_t::filterMask.
+/// See also runtime refinement \ref RAIL_SupportsAddrFilterMask().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
+#define RAIL_SUPPORTS_ADDR_FILTER_MASK 1
+#else
+#define RAIL_SUPPORTS_ADDR_FILTER_MASK 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// alternate power settings for the Power Amplifier.
+/// See also runtime refinement \ref RAIL_SupportsAlternateTxPower().
+#if ((_SILICON_LABS_32B_SERIES_1_CONFIG > 1)  \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+#define RAIL_SUPPORTS_ALTERNATE_TX_POWER 1
+#else
+#define RAIL_SUPPORTS_ALTERNATE_TX_POWER 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_ALTERNATE_TX_POWER.
+#define RAIL_FEAT_ALTERNATE_POWER_TX_SUPPORTED RAIL_SUPPORTS_ALTERNATE_TX_POWER
+
+/// Boolean to indicate whether the selected chip supports antenna diversity.
+/// See also runtime refinement \ref RAIL_SupportsAntennaDiversity().
+#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) \
+  || (_SILICON_LABS_32B_SERIES == 2))
+#define RAIL_SUPPORTS_ANTENNA_DIVERSITY 1
+#else
+#define RAIL_SUPPORTS_ANTENNA_DIVERSITY 0
+#endif
+
+/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY.
+#define RAIL_FEAT_ANTENNA_DIVERSITY RAIL_SUPPORTS_ANTENNA_DIVERSITY
+
+/// Boolean to indicate whether the selected chip supports internal RF path diversity.
+/// See also runtime refinement \ref RAIL_SupportsPathDiversity().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+#define RAIL_SUPPORTS_PATH_DIVERSITY 1
+#else
+#define RAIL_SUPPORTS_PATH_DIVERSITY 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports channel hopping.
+/// See also runtime refinement \ref RAIL_SupportsChannelHopping().
+#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG >= 1) \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300))
+#define RAIL_SUPPORTS_CHANNEL_HOPPING 1
+#else
+#define RAIL_SUPPORTS_CHANNEL_HOPPING 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_CHANNEL_HOPPING.
+#define RAIL_FEAT_CHANNEL_HOPPING RAIL_SUPPORTS_CHANNEL_HOPPING
+
+/// Boolean to indicate whether the selected chip supports dual sync words.
+/// See also runtime refinement \ref RAIL_SupportsDualSyncWords().
+#if 1
+#define RAIL_SUPPORTS_DUAL_SYNC_WORDS 1
+#else
+#define RAIL_SUPPORTS_DUAL_SYNC_WORDS 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports automatic transitions
+/// from TX to TX.
+/// See also runtime refinement \ref RAIL_SupportsTxToTx().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
+#define RAIL_SUPPORTS_TX_TO_TX 1
+#else
+#define RAIL_SUPPORTS_TX_TO_TX 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports \ref RAIL_TX_REPEAT_OPTION_START_TO_START.
+/// See also runtime refinement \ref RAIL_SupportsTxRepeatStartToStart().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
+#define RAIL_SUPPORTS_TX_REPEAT_START_TO_START RAIL_SUPPORTS_TX_TO_TX
+#else
+#define RAIL_SUPPORTS_TX_REPEAT_START_TO_START 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports thermistor measurements.
+/// See also runtime refinement \ref RAIL_SupportsExternalThermistor().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9))
+#define RAIL_SUPPORTS_EXTERNAL_THERMISTOR 1
+#else
+#define RAIL_SUPPORTS_EXTERNAL_THERMISTOR 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR.
+#define RAIL_FEAT_EXTERNAL_THERMISTOR RAIL_SUPPORTS_EXTERNAL_THERMISTOR
+
+/// Boolean to indicate whether the selected chip supports HFXO compensation.
+/// See also runtime refinement \ref RAIL_SupportsHFXOCompensation().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define RAIL_SUPPORTS_HFXO_COMPENSATION RAIL_SUPPORTS_EXTERNAL_THERMISTOR
+#else
+#define RAIL_SUPPORTS_HFXO_COMPENSATION 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports AUXADC measurements.
+/// See also runtime refinement \ref RAIL_SupportsAuxAdc().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9))
+#define RAIL_SUPPORTS_AUXADC 1
+#else
+#define RAIL_SUPPORTS_AUXADC 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports a high-precision
+/// LFRCO.
+/// Best to use the runtime refinement \ref RAIL_SupportsPrecisionLFRCO()
+/// because some chip revisions do not support it.
+#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9))
+#define RAIL_SUPPORTS_PRECISION_LFRCO 1
+#else
+#define RAIL_SUPPORTS_PRECISION_LFRCO 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports radio entropy.
+/// See also runtime refinement \ref RAIL_SupportsRadioEntropy().
+#ifndef FPGA
+#define RAIL_SUPPORTS_RADIO_ENTROPY 1
+#else
+#define RAIL_SUPPORTS_RADIO_ENTROPY 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// RFSENSE Energy Detection Mode.
+/// See also runtime refinement \ref RAIL_SupportsRfSenseEnergyDetection().
+#if ((_SILICON_LABS_32B_SERIES == 1)          \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9))
+#define RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION 1
+#else
+#define RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// RFSENSE Selective(OOK) Mode.
+/// See also runtime refinement \ref RAIL_SupportsRfSenseSelectiveOok().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9))
+#define RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK 1
+#else
+#define RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK.
+#define RAIL_FEAT_RFSENSE_SELECTIVE_OOK_MODE_SUPPORTED \
+  RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK
+
+/// Boolean to indicate whether the selected chip supports the
+/// VDET voltage measurement feature.
+/// See also runtime refinement \ref RAIL_SupportsVdet().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define RAIL_SUPPORTS_VDET 1
+#else
+#define RAIL_SUPPORTS_VDET 0
+#endif
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/// Boolean to indicate whether the selected chip supports the User Sequencer
+/// See also runtime refinement \ref RAIL_SupportsUserSequencer().
+#if (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300)
+#define RAIL_SUPPORTS_USER_SEQUENCER 1
+#else
+#define RAIL_SUPPORTS_USER_SEQUENCER 0
+#endif
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+// BLE features
+// Some features may not be available on all platforms
+// due to radio hardware limitations.
+
+/// Boolean to indicate whether the selected chip supports BLE.
+/// See also runtime refinement \ref RAIL_SupportsProtocolBLE().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 4)
+#define RAIL_SUPPORTS_PROTOCOL_BLE RAIL_SUPPORTS_2P4GHZ_BAND
+#else
+#define RAIL_SUPPORTS_PROTOCOL_BLE 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports BLE 1 Mbps
+/// Non-Viterbi PHY.
+/// See also runtime refinement \ref RAIL_BLE_Supports1MbpsNonViterbi().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 1)
+#define RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports BLE 1 Mbps Viterbi
+/// PHY.
+/// See also runtime refinement \ref RAIL_BLE_Supports1MbpsViterbi().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
+#define RAIL_BLE_SUPPORTS_1MBPS_VITERBI RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define RAIL_BLE_SUPPORTS_1MBPS_VITERBI 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports BLE 1 Mbps operation.
+/// See also runtime refinement \ref RAIL_BLE_Supports1Mbps().
+#define RAIL_BLE_SUPPORTS_1MBPS \
+  (RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI || RAIL_BLE_SUPPORTS_1MBPS_VITERBI)
+
+/// Boolean to indicate whether the selected chip supports BLE 2 Mbps
+/// Non-Viterbi PHY.
+/// See also runtime refinement \ref RAIL_BLE_Supports2MbpsNonViterbi().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2)
+#define RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports BLE 2 Mbps Viterbi
+/// PHY.
+/// See also runtime refinement \ref RAIL_BLE_Supports2MbpsViterbi().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
+#define RAIL_BLE_SUPPORTS_2MBPS_VITERBI RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define RAIL_BLE_SUPPORTS_2MBPS_VITERBI 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports BLE 2 Mbps operation.
+/// See also runtime refinement \ref RAIL_BLE_Supports2Mbps().
+#define RAIL_BLE_SUPPORTS_2MBPS \
+  (RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI || RAIL_BLE_SUPPORTS_2MBPS_VITERBI)
+
+/// Boolean to indicate whether the selected chip supports BLE
+/// Antenna Switching needed for Angle-of-Arrival receives or
+/// Angle-of-Departure transmits.
+/// See also runtime refinement \ref RAIL_BLE_SupportsAntennaSwitching().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300))
+#define RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports the BLE Coded PHY
+/// used for Long-Range.
+/// See also runtime refinement \ref RAIL_BLE_SupportsCodedPhy().
+#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300))
+#define RAIL_BLE_SUPPORTS_CODED_PHY RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define  RAIL_BLE_SUPPORTS_CODED_PHY 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_CODED_PHY.
+#define RAIL_FEAT_BLE_CODED RAIL_BLE_SUPPORTS_CODED_PHY
+
+/// Boolean to indicate whether the selected chip supports the BLE Simulscan PHY
+/// used for simultaneous BLE 1 Mbps and Coded PHY reception.
+/// See also runtime refinement \ref RAIL_BLE_SupportsSimulscanPhy().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300))
+#define RAIL_BLE_SUPPORTS_SIMULSCAN_PHY RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define RAIL_BLE_SUPPORTS_SIMULSCAN_PHY 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports BLE
+/// CTE (Constant Tone Extension) needed for Angle-of-Arrival/Departure
+/// transmits.
+/// See also runtime refinement \ref RAIL_BLE_SupportsCte().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300))
+#define RAIL_BLE_SUPPORTS_CTE RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define RAIL_BLE_SUPPORTS_CTE 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports the
+/// Quuppa PHY.
+/// See also runtime refinement \ref RAIL_BLE_SupportsQuuppa().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9))
+#define RAIL_BLE_SUPPORTS_QUUPPA RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define RAIL_BLE_SUPPORTS_QUUPPA 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports BLE
+/// IQ Sampling needed for Angle-of-Arrival/Departure receives.
+/// See also runtime refinement \ref RAIL_BLE_SupportsIQSampling().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300))
+#define RAIL_BLE_SUPPORTS_IQ_SAMPLING RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define RAIL_BLE_SUPPORTS_IQ_SAMPLING 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports some BLE AOX
+/// features.
+#define RAIL_BLE_SUPPORTS_AOX          \
+  (RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING \
+   || RAIL_BLE_SUPPORTS_IQ_SAMPLING    \
+   || RAIL_BLE_SUPPORTS_CTE)
+
+/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_AOX
+#define RAIL_FEAT_BLE_AOX_SUPPORTED RAIL_BLE_SUPPORTS_AOX
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/// Boolean to indicate whether the selected chip supports BLE
+/// CS (Channel Sounding).
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)
+#define RAIL_BLE_SUPPORTS_CS RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define RAIL_BLE_SUPPORTS_CS 0
+#endif
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+/// Boolean to indicate whether the selected chip supports BLE PHY switch to RX
+/// functionality, which is used to switch BLE PHYs at a specific time
+/// to receive auxiliary packets.
+/// See also runtime refinement \ref RAIL_BLE_SupportsPhySwitchToRx().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
+#define RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX.
+#define RAIL_FEAT_BLE_PHY_SWITCH_TO_RX RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX
+
+// IEEE 802.15.4 features
+// Some features may not be available on all platforms
+// due to radio hardware limitations.
+
+/// Boolean to indicate whether the selected chip supports IEEE 802.15.4.
+/// See also runtime refinement \ref RAIL_SupportsProtocolIEEE802154().
+#if 1
+#define RAIL_SUPPORTS_PROTOCOL_IEEE802154 1
+#else
+#define RAIL_SUPPORTS_PROTOCOL_IEEE802154 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports the
+/// 802.15.4 Wi-Fi Coexistence PHY.
+/// See also runtime refinement \ref RAIL_IEEE802154_SupportsCoexPhy().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG > 1)
+#define RAIL_IEEE802154_SUPPORTS_COEX_PHY (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND)
+#else
+#define RAIL_IEEE802154_SUPPORTS_COEX_PHY 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY.
+#define RAIL_FEAT_802154_COEX_PHY RAIL_IEEE802154_SUPPORTS_COEX_PHY
+
+/// Boolean to indicate whether the selected chip supports
+/// the IEEE 802.15.4 2.4 GHz band variant.
+/// See also runtime refinement \ref RAIL_SupportsIEEE802154Band2P4().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG != 3)
+#define RAIL_SUPPORTS_IEEE802154_BAND_2P4 (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND)
+#else
+#define RAIL_SUPPORTS_IEEE802154_BAND_2P4 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// the IEEE 802.15.4 2.4 RX channel switching.
+/// See also runtime refinement \ref RAIL_IEEE802154_SupportsRxChannelSwitching().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 1) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6))
+#define RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING (RAIL_SUPPORTS_IEEE802154_BAND_2P4)
+#else
+#define RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports a front end module.
+/// See also runtime refinement \ref RAIL_IEEE802154_SupportsFemPhy().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG != 8)
+#define RAIL_IEEE802154_SUPPORTS_FEM_PHY (RAIL_SUPPORTS_IEEE802154_BAND_2P4)
+#else
+#define RAIL_IEEE802154_SUPPORTS_FEM_PHY 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// IEEE 802.15.4E-2012 feature subset needed for Zigbee R22 GB868.
+/// See also runtime refinement \ref
+/// RAIL_IEEE802154_SupportsESubsetGB868().
+#if 1
+#define RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 RAIL_SUPPORTS_PROTOCOL_IEEE802154
+#else
+#define RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 0
+#endif
+/// Backwards-compatible synonym of \ref
+/// RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868.
+#define RAIL_FEAT_IEEE802154_E_GB868_SUPPORTED \
+  RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868
+
+/// Boolean to indicate whether the selected chip supports
+/// IEEE 802.15.4E-2012 Enhanced ACKing.
+/// See also runtime refinement \ref
+/// RAIL_IEEE802154_SupportsEEnhancedAck().
+#if 1
+#define RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868
+#else
+#define RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK 0
+#endif
+/// Backwards-compatible synonym of \ref
+/// RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK.
+#define RAIL_FEAT_IEEE802154_E_ENH_ACK_SUPPORTED \
+  RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK
+
+/// Boolean to indicate whether the selected chip supports
+/// receiving IEEE 802.15.4E-2012 Multipurpose frames.
+/// See also runtime refinement \ref
+/// RAIL_IEEE802154_SupportsEMultipurposeFrames().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
+#define RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868
+#else
+#define RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES 0
+#endif
+/// Backwards-compatible synonym of \ref
+/// RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES.
+#define RAIL_FEAT_IEEE802154_MULTIPURPOSE_FRAME_SUPPORTED \
+  RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES
+
+/// Boolean to indicate whether the selected chip supports
+/// IEEE 802.15.4G-2012 feature subset needed for Zigbee R22 GB868.
+/// See also runtime refinement \ref
+/// RAIL_IEEE802154_SupportsGSubsetGB868().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG != 3)
+#define RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 \
+  ((RAIL_SUPPORTS_PROTOCOL_IEEE802154 != 0) && (RAIL_SUPPORTS_SUBGHZ_BAND != 0))
+#else
+#define RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 0
+#endif
+/// Backwards-compatible synonym of \ref
+/// RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868.
+#define RAIL_FEAT_IEEE802154_G_GB868_SUPPORTED \
+  RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868
+
+/// Boolean to indicate whether the selected chip supports
+/// dynamic FEC
+/// See also runtime refinement \ref
+/// RAIL_IEEE802154_SupportsGDynFec().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG > 1) \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300))
+#define RAIL_IEEE802154_SUPPORTS_G_DYNFEC \
+  RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868  // limit to Sub-GHz for now
+#else
+#define RAIL_IEEE802154_SUPPORTS_G_DYNFEC 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// Wi-SUN mode switching
+/// See also runtime refinement \ref
+/// RAIL_IEEE802154_SupportsGModeSwitch().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+#define RAIL_IEEE802154_SUPPORTS_G_MODESWITCH \
+  RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868  // limit to Sub-GHz for now
+#else
+#define RAIL_IEEE802154_SUPPORTS_G_MODESWITCH 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// IEEE 802.15.4G-2012 reception and transmission of frames
+/// with 4-byte CRC.
+/// See also runtime refinement \ref RAIL_IEEE802154_SupportsG4ByteCrc().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
+#define RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868
+#else
+#define RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC.
+#define RAIL_FEAT_IEEE802154_G_4BYTE_CRC_SUPPORTED \
+  RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC
+
+/// Boolean to indicate whether the selected chip supports
+/// IEEE 802.15.4G-2012 reception of unwhitened frames.
+/// See also runtime refinement \ref
+/// RAIL_IEEE802154_SupportsGUnwhitenedRx().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
+#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868
+#else
+#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX 0
+#endif
+/// Backwards-compatible synonym of \ref
+/// RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX.
+#define RAIL_FEAT_IEEE802154_G_UNWHITENED_RX_SUPPORTED \
+  RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX
+
+/// Boolean to indicate whether the selected chip supports
+/// IEEE 802.15.4G-2012 transmission of unwhitened frames.
+/// See also runtime refinement \ref
+/// RAIL_IEEE802154_SupportsGUnwhitenedTx().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
+#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868
+#else
+#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX 0
+#endif
+/// Backwards-compatible synonym of \ref
+/// RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX.
+#define RAIL_FEAT_IEEE802154_G_UNWHITENED_TX_SUPPORTED \
+  RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX
+
+/// Boolean to indicate whether the selected chip supports
+/// canceling the frame-pending lookup event
+/// \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND
+/// when the radio transitions to a state that renders the
+/// the reporting of this event moot (i.e., too late for
+/// the stack to influence the outgoing ACK).
+/// See also runtime refinement \ref
+/// RAIL_IEEE802154_SupportsCancelFramePendingLookup().
+#if 1
+#define RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP RAIL_SUPPORTS_PROTOCOL_IEEE802154
+#else
+#define RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP 0
+#endif
+/// Backwards-compatible synonym of \ref
+/// RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP.
+#define RAIL_FEAT_IEEE802154_CANCEL_FP_LOOKUP_SUPPORTED \
+  RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP
+
+/// Boolean to indicate whether the selected chip supports
+/// early triggering of the frame-pending lookup event
+/// \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND
+/// just after MAC address fields have been received.
+/// See also runtime refinement \ref
+/// RAIL_IEEE802154_SupportsEarlyFramePendingLookup().
+#if 1
+#define RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP RAIL_SUPPORTS_PROTOCOL_IEEE802154
+#else
+#define RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP 0
+#endif
+/// Backwards-compatible synonym of \ref
+/// RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP.
+#define RAIL_FEAT_IEEE802154_EARLY_FP_LOOKUP_SUPPORTED \
+  RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP
+
+/// Boolean to indicate whether the selected chip supports dual PA configs for mode switch
+/// or concurrent mode.
+/// See also runtime refinement \ref RAIL_IEEE802154_SupportsDualPaConfig().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG 1
+#else
+#define RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports the pa power setting table.
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300))
+#define RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 1
+#else
+#define RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 0
+#endif
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/// Boolean to indicate whether the selected chip uses the common PA interface.
+/// This feature is available when the configuration for Silicon Labs Series 3
+/// devices is set to 1, enabling the use of a unified Power Amplifier (PA) interface
+/// across different configurations.
+#if (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300)
+#define RAIL_SUPPORTS_COMMON_PA_INTERFACE 1
+#else
+#define RAIL_SUPPORTS_COMMON_PA_INTERFACE 0
+#endif
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/// Boolean to indicate whether the selected chip supports
+/// IEEE802.15.4 2.4 GHz at 2 Mbps
+/// See also runtime refinement \ref
+/// RAIL_IEEE802154_Supports2MbpsPhy().
+#if    (_SILICON_LABS_32B_SERIES_1_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 1)   \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6)   \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300)
+#define RAIL_IEEE802154_SUPPORTS_2MBPS_PHY \
+  (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND)
+#else
+#define RAIL_IEEE802154_SUPPORTS_2MBPS_PHY 0
+#endif
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+/// Boolean to indicate whether the selected chip supports IEEE 802.15.4 PHY
+/// with custom settings
+#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_1_CONFIG == 3))
+#define RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND)
+#else
+#define RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY 0
+#endif
+
+// Wi_SUN features
+
+/// Boolean to indicate whether the selected chip supports
+/// Wi-SUN
+/// See also runtime refinement \ref
+/// RAIL_SupportsProtocolWiSUN().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+#define RAIL_SUPPORTS_PROTOCOL_WI_SUN 1
+#else
+#define RAIL_SUPPORTS_PROTOCOL_WI_SUN 0
+#endif
+
+// WMBUS features
+
+/// Boolean to indicate whether the selected chip supports WMBUS simultaneous
+/// M2O RX of T and C modes set by \ref RAIL_WMBUS_Config().
+/// See also runtime refinement \ref RAIL_WMBUS_SupportsSimultaneousTCRx().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+#define RAIL_WMBUS_SUPPORTS_SIMULTANEOUS_T_C_RX 1
+#else
+#define RAIL_WMBUS_SUPPORTS_SIMULTANEOUS_T_C_RX 0
+#endif
+
+// Z-Wave features
+// Some features may not be available on all platforms
+// due to radio hardware limitations.
+
+/// Boolean to indicate whether the selected chip supports Z-Wave.
+/// See also runtime refinement \ref RAIL_SupportsProtocolZWave().
+#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+#define RAIL_SUPPORTS_PROTOCOL_ZWAVE RAIL_SUPPORTS_SUBGHZ_BAND
+#else
+#define RAIL_SUPPORTS_PROTOCOL_ZWAVE 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_PROTOCOL_ZWAVE.
+#define RAIL_FEAT_ZWAVE_SUPPORTED RAIL_SUPPORTS_PROTOCOL_ZWAVE
+
+/// Boolean to indicate whether the selected chip supports energy detect PHY.
+/// See also runtime refinement \ref RAIL_ZWAVE_SupportsEnergyDetectPhy().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 3)
+#define RAIL_ZWAVE_SUPPORTS_ED_PHY RAIL_SUPPORTS_PROTOCOL_ZWAVE
+#else
+#define RAIL_ZWAVE_SUPPORTS_ED_PHY 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports concurrent PHY.
+/// See also runtime refinement \ref RAIL_ZWAVE_SupportsConcPhy().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+#define RAIL_ZWAVE_SUPPORTS_CONC_PHY RAIL_SUPPORTS_PROTOCOL_ZWAVE
+#else
+#define RAIL_ZWAVE_SUPPORTS_CONC_PHY 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports SQ-based PHY.
+/// See also runtime refinement \ref RAIL_SupportsSQPhy().
+#if (((_SILICON_LABS_32B_SERIES_2_CONFIG >= 3)  \
+  && (_SILICON_LABS_32B_SERIES_2_CONFIG != 7)   \
+  && (_SILICON_LABS_32B_SERIES_2_CONFIG != 9))  \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300))
+#define RAIL_SUPPORTS_SQ_PHY 1
+#else
+#define RAIL_SUPPORTS_SQ_PHY 0
+#endif
+
+/// Boolean to indicate whether the code supports Z-Wave
+/// region information in PTI and
+/// newer \ref RAIL_ZWAVE_RegionConfig_t structure
+/// See also runtime refinement \ref RAIL_ZWAVE_SupportsRegionPti().
+#if 1
+#define RAIL_ZWAVE_SUPPORTS_REGION_PTI RAIL_SUPPORTS_PROTOCOL_ZWAVE
+#else
+#define RAIL_ZWAVE_SUPPORTS_REGION_PTI 0
+#endif
+/// Backwards-compatible synonym of \ref RAIL_ZWAVE_SUPPORTS_REGION_PTI.
+#define RAIL_FEAT_ZWAVE_REGION_PTI RAIL_ZWAVE_SUPPORTS_REGION_PTI
+
+/// Boolean to indicate whether the selected chip supports raw RX data
+/// sources other than \ref RAIL_RxDataSource_t::RX_PACKET_DATA.
+/// See also runtime refinement \ref RAIL_SupportsRxRawData().
+#if (_SILICON_LABS_32B_SERIES_3_CONFIG == 0)
+#define RAIL_SUPPORTS_RX_RAW_DATA 1
+#else
+#define RAIL_SUPPORTS_RX_RAW_DATA 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// direct mode.
+/// See also runtime refinement \ref RAIL_SupportsDirectMode().
+#if ((_SILICON_LABS_32B_SERIES == 1)          \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+#define RAIL_SUPPORTS_DIRECT_MODE 1
+#else
+#define RAIL_SUPPORTS_DIRECT_MODE 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// RX direct mode data to FIFO.
+/// See also runtime refinement \ref RAIL_SupportsRxDirectModeDataToFifo().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+#define RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO 1
+#else
+#define RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO 0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// MFM protocol.
+/// See also runtime refinement \ref RAIL_SupportsMfm().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+#define RAIL_SUPPORTS_MFM 1
+#else
+#define RAIL_SUPPORTS_MFM 0
+#endif
+
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 4)   \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6)   \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) \
+  || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300))
+/// Boolean to indicate whether the selected chip supports
+/// 802.15.4 signal detection
+#define RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER  (RAIL_SUPPORTS_PROTOCOL_IEEE802154)
+/// Boolean to indicate whether the selected chip supports
+/// BLE signal detection
+#define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER         (RAIL_SUPPORTS_PROTOCOL_BLE)
+#else
+/// Boolean to indicate whether the selected chip supports
+/// 802.15.4 signal detection
+#define RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER  0
+/// Boolean to indicate whether the selected chip supports
+/// BLE signal detection
+#define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER         0
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// configurable RSSI threshold set by \ref RAIL_SetRssiDetectThreshold().
+/// See also runtime refinement \ref RAIL_SupportsRssiDetectThreshold().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5))
+#define RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD (1U)
+#else
+#define RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD (0U)
+#endif
+
+/// Boolean to indicate whether the selected chip supports
+/// thermal protection set by \ref RAIL_ConfigThermalProtection().
+/// See also runtime refinement \ref RAIL_SupportsThermalProtection().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+  #define RAIL_SUPPORTS_THERMAL_PROTECTION  (1U)
+#else
+  #define RAIL_SUPPORTS_THERMAL_PROTECTION  (0U)
+#endif
+
+/// Boolean to indicate whether the selected chip supports fast RX-to-RX enabled by
+/// \ref RAIL_RX_OPTION_FAST_RX2RX.
+/// See also runtime refinement \ref RAIL_SupportsFastRx2Rx().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
+  #define RAIL_SUPPORTS_FAST_RX2RX  (1U)
+#else
+  #define RAIL_SUPPORTS_FAST_RX2RX  (0U)
+#endif
+
+/// Boolean to indicate whether the selected chip supports collision detection
+/// enabled by \ref RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION
+/// See also runtime refinement \ref RAIL_SupportsCollisionDetection().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+  #define RAIL_SUPPORTS_COLLISION_DETECTION  (1U)
+#else
+  #define RAIL_SUPPORTS_COLLISION_DETECTION  (0U)
+#endif
+
+/// Boolean to indicate whether the selected chip supports Sidewalk protocol.
+/// See also runtime refinement \ref RAIL_SupportsProtocolSidewalk().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+  #define RAIL_SUPPORTS_PROTOCOL_SIDEWALK (1U)
+#else
+  #define RAIL_SUPPORTS_PROTOCOL_SIDEWALK (0U)
+#endif
+
+/// Boolean to indicate whether the selected chip supports TrustZone secure
+/// configuration of peripherals used by RAIL.
+/// See also runtime refinement \ref RAIL_SupportsTrustZoneSecurePeripherals().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)
+  #define RAIL_SUPPORTS_TRUSTZONE_SECURE_PERIPHERALS (1U)
+#else
+  #define RAIL_SUPPORTS_TRUSTZONE_SECURE_PERIPHERALS (0U)
+#endif
+
+/// Boolean to indicate whether the selected chip supports automatic PRS LNA
+/// bypass for external FEM.
+/// See also runtime refinement \ref RAIL_SupportsPrsLnaBypass().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+  #define RAIL_SUPPORTS_PRS_LNA_BYPASS (1U)
+#else
+  #define RAIL_SUPPORTS_PRS_LNA_BYPASS (0U)
+#endif
+
+/** @} */ // end of group Features
+
+/** @} */ // end of group RAIL_API
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __RAIL_FEATURES_H__

Libs/platform/radio/rail_lib/common/rail_mfm.h

@@ -0,0 +1,193 @@
+/***************************************************************************//**
+ * @file
+ * @brief The MFM specific header file for the RAIL library.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __RAIL_MFM_H__
+#define __RAIL_MFM_H__
+
+#include "rail_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @addtogroup MFM Multi-Level Frequency Modulation
+/// @ingroup Protocol_Specific
+/// @brief MFM configuration routines
+///
+/// @note This feature is only supported on EFR32xG23 devices.
+///
+/// This feature can be used to directly control the TX interpolation filter
+/// input to allow for a more flexible frequency modulation scheme than the
+/// standard MODEM. When doing this, the MFM buffer is treated as an array
+/// of 8-bit signed data used as normalized frequency deviation to the SYNTH
+/// frequency to directly control the interpolation filter input.
+/// No support for frame handling, coding, nor shaping is supported.
+/// Only compatible with FSK modulations.
+///
+/// The functions in this group configure RAIL Multi-Level Frequency Modulation (MFM)
+/// hardware acceleration features.
+///
+/// To configure MFM functionality, the application must first set up
+/// a RAIL instance with \ref RAIL_Init() and other setup functions.
+/// Before enabling MFM, a ping-pong buffer (called buffer0 and buffer1
+/// below) must be configured via \ref RAIL_SetMfmPingPongFifo() and
+/// populated with the initial buffer content.
+/// MFM is enabled by setting \ref RAIL_TxDataSource_t::TX_MFM_DATA using
+/// \ref RAIL_ConfigData() and is activated when transmit is started by
+/// \ref RAIL_StartTx(). Once transmitting the data in the ping-pong buffers,
+/// RAIL will manage them so it looks like a continuous transmission to the
+/// receiver. Every time one of the ping-pong buffers has been transmitted,
+/// \ref RAIL_EVENT_MFM_TX_BUFFER_DONE is triggered so the application can
+/// update the data in that buffer without the need to start/stop the
+/// transmission. \ref RAIL_EVENT_MFM_TX_BUFFER_DONE can be enable with \ref
+/// RAIL_ConfigEvents().
+/// Use \ref RAIL_StopTx() to finish transmitting.
+/// @code{.c}
+/// #define MFM_RAW_BUF_WORDS 128
+/// extern RAIL_Handle_t railHandle;
+/// uint8_t txCount = 0;
+/// uint32_t mfmPingPongBuffers[2][MFM_RAW_BUF_WORDS];
+///
+/// typedef struct mfmConfigApp {
+///   RAIL_MFM_PingPongBufferConfig_t buffer;
+///   RAIL_StateTiming_t timings;
+///   RAIL_DataConfig_t dataConfig;
+/// } mfmConfigApp_t;
+///
+/// static mfmConfigApp_t mfmConfig = {
+///   .buffer = {
+///     .pBuffer0 = (&mfmPingPongBuffers[0]),
+///     .pBuffer1 = (&mfmPingPongBuffers[1]),
+///     .bufferSizeWords = MFM_RAW_BUF_WORDS,
+///   },
+///   .timings = {
+///     .idleToTx = 100,
+///     .idleToRx = 0,
+///     .rxToTx = 0,
+///     .txToRx = 0,
+///     .rxSearchTimeout = 0,
+///     .txToRxSearchTimeout = 0
+///   },
+///   .dataConfig = {
+///     .txSource = TX_MFM_DATA,
+///     .rxSource = RX_PACKET_DATA,
+///     .txMethod = PACKET_MODE,
+///     .rxMethod = PACKET_MODE,
+///   },
+/// };
+///
+/// // Main RAIL events handler callback
+/// static void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events)
+/// {
+///   // Increment TX counter
+///   if (events & RAIL_EVENT_MFM_BUF_DONE) {
+///       txCount++;
+///       return;
+///     }
+///   }
+/// }
+///
+/// void mfmInit(void)
+/// {
+///   // initialize MFM
+///   uint32_t idx;
+///   uint32_t *pDst0 = mfmConfig.buffer.pBuffer0;
+///   uint32_t *pDst1 = mfmConfig.buffer.pBuffer1;
+///   for (idx = 0; idx < (mfmConfig.buffer.bufferSizeWords / 4); idx++) {
+///     pDst0[4 * idx + 0] = 0x755A3100;
+///     pDst1[4 * idx + 0] = 0x755A3100;
+///     pDst0[4 * idx + 1] = 0x315A757F;
+///     pDst1[4 * idx + 1] = 0x315A757F;
+///     pDst0[4 * idx + 2] = 0x8BA6CF00;
+///     pDst1[4 * idx + 2] = 0x8BA6CF00;
+///     pDst0[4 * idx + 3] = 0xCFA68B81;
+///     pDst1[4 * idx + 3] = 0xCFA68B81;
+///   }
+///
+///   RAIL_Status_t status;
+///   status = RAIL_SetMfmPingPongFifo(railHandle, &mfmConfig.buffer);
+///   assert(status == RAIL_STATUS_NO_ERROR);
+///
+///   status = RAIL_SetStateTiming(railHandle, &mfmConfig.timings);
+///   assert(status == RAIL_STATUS_NO_ERROR);
+///
+///   mfmConfig.dataConfig.txSource = TX_MFM_DATA;
+///   status = RAIL_ConfigData(railHandle, &mfmConfig.dataConfig);
+///   assert(status == RAIL_STATUS_NO_ERROR);
+///
+///   // start transmitting
+///   status = RAIL_StartTx(railHandle, 0, 0, NULL);
+///   assert(status == RAIL_STATUS_NO_ERROR);
+/// }
+///
+/// void mfmDeInit(void)
+/// {
+///   RAIL_Status_t status;
+///   status = RAIL_StopTx(railHandle, RAIL_STOP_MODES_ALL);
+///   assert(status == RAIL_STATUS_NO_ERROR);
+///
+///   mfmConfig.dataConfig.txSource = TX_PACKET_DATA;
+///   status = RAIL_ConfigData(railHandle, &mfmConfig.dataConfig);
+///   assert(status == RAIL_STATUS_NO_ERROR);
+/// }
+/// @endcode
+///
+/// @{
+
+/**
+ * @struct RAIL_MFM_PingPongBufferConfig_t
+ * @brief A configuration structure for MFM Ping-pong buffer in RAIL.
+ */
+typedef struct RAIL_MFM_PingPongBufferConfig {
+  /** Pointer to buffer 0. Must be 32-bit aligned. */
+  uint32_t *pBuffer0;
+  /** Pointer to buffer 1. Must be 32-bit aligned. */
+  uint32_t *pBuffer1;
+  /** Size of each buffer in 32-bit words. */
+  uint32_t bufferSizeWords;
+} RAIL_MFM_PingPongBufferConfig_t;
+
+/**
+ * Set MFM ping-pong buffer.
+ *
+ * @param[in] railHandle A handle of RAIL instance.
+ * @param[in] config A non-NULL pointer to the MFM ping-pong buffer configuration structure.
+ * @return Status code indicating success of the function call.
+ */
+RAIL_Status_t RAIL_SetMfmPingPongFifo(RAIL_Handle_t railHandle,
+                                      const RAIL_MFM_PingPongBufferConfig_t *config);
+
+/** @} */ // end of MFM
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __RAIL_MFM_H__

Libs/platform/radio/rail_lib/plugin/pa-conversions/efr32xg24/sl_rail_util_pa_curves_10dbm.h

@@ -0,0 +1,116 @@
+/***************************************************************************//**
+ * @file
+ * @brief PA power conversion curves used by Silicon Labs PA power conversion
+ *   functions.
+ * @details This file contains the curves needed convert PA power levels to
+ *   dBm powers.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __PA_CURVES_H_
+#define __PA_CURVES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RAIL_PA_CURVES_PIECEWISE_SEGMENTS (9U)
+#define RAIL_PA_CURVES_LP_VALUES (16U)
+
+#define RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER      100
+#define RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER      -300
+#define RAIL_PA_CURVES_2P4_HP_VBAT_CURVES \
+  { { 255, 100, 22 },                     \
+    { 90, 1960, -116460 },                \
+    { 36, 567, -7935 },                   \
+    { 22, 288, 6929 },                    \
+    { 16, 192, 9881 },                    \
+    { 11, 134, 10360 },                   \
+    { 8, 89, 9610 },                      \
+    { 6, 69, 8821 },                      \
+    { 4, 18, 5138 } }
+
+#define RAIL_PA_CURVES_2P4_LP_VBAT_MAX_POWER      0
+#define RAIL_PA_CURVES_2P4_LP_VBAT_MIN_POWER      -260
+#define RAIL_PA_CURVES_2P4_LP_VBAT_CURVES \
+  {                                       \
+    -252, /*! Power Level 0 */            \
+    -149, /*! Power Level 1 */            \
+    -97,  /*! Power Level 2 */            \
+    -69,  /*! Power Level 3 */            \
+    -52,  /*! Power Level 4 */            \
+    -40,  /*! Power Level 5 */            \
+    -32,  /*! Power Level 6 */            \
+    -26,  /*! Power Level 7 */            \
+    -22,  /*! Power Level 8 */            \
+    -18,  /*! Power Level 9 */            \
+    -15,  /*! Power Level 10 */           \
+    -13,  /*! Power Level 11 */           \
+    -11,  /*! Power Level 12 */           \
+    -9,  /*! Power Level 13 */            \
+    -8,   /*! Power Level 14 */           \
+    -7,   /*! Power Level 15 */           \
+  }
+// *INDENT-OFF*
+// Macro to declare the variables needed to initialize RAIL_TxPowerCurvesConfig_t for use in
+// RAIL_InitTxPowerCurves, assuming battery powered operation
+#define RAIL_DECLARE_TX_POWER_VBAT_CURVES_ALT                                  \
+  static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHp = {                 \
+    RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER,                                      \
+    RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER,                                      \
+    RAIL_PA_CURVES_2P4_HP_VBAT_CURVES,                                         \
+  };                                                                           \
+  static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] =             \
+    RAIL_PA_CURVES_2P4_LP_VBAT_CURVES;
+// *INDENT-OFF*
+
+#define RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT                                \
+  {                                                                            \
+    .curves = {                                                                \
+      {                                                                        \
+        .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,                       \
+        .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS,                         \
+        .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN,                                 \
+        .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX,                                 \
+        .conversion = { .powerCurve = &RAIL_piecewiseDataHp },                 \
+      },                                                                       \
+      {                                                                        \
+        .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE,                          \
+        .segments = 0U,                                                        \
+        .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN,                                 \
+        .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX,                                 \
+        .conversion = { .mappingTable = &RAIL_curves24Lp[0] },                 \
+      },                                                                        \
+    }                                                                          \
+  }
+// *INDENT-OFF*
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Libs/platform/radio/rail_lib/plugin/pa-conversions/efr32xg24/sl_rail_util_pa_curves_20dbm.h

@@ -0,0 +1,140 @@
+/***************************************************************************//**
+ * @file
+ * @brief PA power conversion curves used by Silicon Labs PA power conversion
+ *   functions.
+ * @details This file contains the curves needed convert PA power levels to
+ *   dBm powers.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __PA_CURVES_H_
+#define __PA_CURVES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RAIL_PA_CURVES_PIECEWISE_SEGMENTS (8U)
+#define RAIL_PA_CURVES_LP_VALUES (16U)
+
+#define RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER      200
+#define RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER      -338
+#define RAIL_PA_CURVES_2P4_HP_VBAT_CURVES \
+  { { 180, 2280, -291457 },               \
+    { 78, 770, -46749 },                  \
+    { 44, 431, -6673 },                   \
+    { 27, 255, 6886 },                    \
+    { 17, 167, 10458 },                   \
+    { 10, 98, 10261 },                    \
+    { 6, 59, 8616 },                      \
+    { 3, 11, 3745 } }
+
+#define RAIL_PA_CURVES_2P4_HP_DCDC_MAX_POWER      200
+#define RAIL_PA_CURVES_2P4_HP_DCDC_MIN_POWER      -338
+#define RAIL_PA_CURVES_2P4_HP_DCDC_CURVES \
+  { { 180, 2263, -287605 },               \
+    { 78, 783, -47869 },                  \
+    { 45, 432, -6351 },                   \
+    { 26, 255, 7104 },                    \
+    { 17, 167, 10595 },                   \
+    { 10, 98, 10336 },                    \
+    { 6, 59, 8671 },                      \
+    { 3, 11, 3757 } }
+
+#define RAIL_PA_CURVES_2P4_LP_VBAT_MAX_POWER      0
+#define RAIL_PA_CURVES_2P4_LP_VBAT_MIN_POWER      -260
+#define RAIL_PA_CURVES_2P4_LP_VBAT_CURVES \
+  {                                       \
+    -250, /*! Power Level 0 */            \
+    -148, /*! Power Level 1 */            \
+    -95,  /*! Power Level 2 */            \
+    -68,  /*! Power Level 3 */            \
+    -51,  /*! Power Level 4 */            \
+    -40,  /*! Power Level 5 */            \
+    -32,  /*! Power Level 6 */            \
+    -26,  /*! Power Level 7 */            \
+    -22,  /*! Power Level 8 */            \
+    -18,  /*! Power Level 9 */            \
+    -16,  /*! Power Level 10 */           \
+    -13,  /*! Power Level 11 */           \
+    -12,  /*! Power Level 12 */           \
+    -10,  /*! Power Level 13 */           \
+    -9,   /*! Power Level 14 */           \
+    -9,   /*! Power Level 15 */           \
+  }
+
+// *INDENT-OFF*
+// Macro to declare the variables needed to initialize RAIL_TxPowerCurvesConfig_t for use in
+// RAIL_InitTxPowerCurves, assuming battery powered operation
+#define RAIL_DECLARE_TX_POWER_VBAT_CURVES_ALT                                  \
+  static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = {             \
+    RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER,                                      \
+    RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER,                                      \
+    RAIL_PA_CURVES_2P4_HP_VBAT_CURVES,                                         \
+  };                                                                           \
+  static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] =             \
+    RAIL_PA_CURVES_2P4_LP_VBAT_CURVES;
+// *INDENT-OFF*
+
+// Macro to declare the variables needed to initialize RAIL_TxPowerCurvesConfig_t for use in
+// RAIL_InitTxPowerCurves, assuming battery powered operation
+#define RAIL_DECLARE_TX_POWER_DCDC_CURVES_ALT                                  \
+  static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpDcdc = {             \
+    RAIL_PA_CURVES_2P4_HP_DCDC_MAX_POWER,                                      \
+    RAIL_PA_CURVES_2P4_HP_DCDC_MIN_POWER,                                      \
+    RAIL_PA_CURVES_2P4_HP_DCDC_CURVES,                                         \
+  };                                                                           \
+  static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] =             \
+    RAIL_PA_CURVES_2P4_LP_VBAT_CURVES;
+// *INDENT-OFF*
+
+#define RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT                                \
+  {                                                                            \
+    .curves = {                                                                \
+      {                                                                        \
+        .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,                       \
+        .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS,                         \
+        .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN,                                 \
+        .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX,                                 \
+        .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat},              \
+      },                                                                       \
+      {                                                                        \
+        .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE,                          \
+        .segments = 0U,                                                        \
+        .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN,                                 \
+        .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX,                                 \
+        .conversion = { .mappingTable = &RAIL_curves24Lp[0] },                 \
+      },                                                                       \
+    }                                                                          \
+  }
+// *INDENT-OFF*
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Libs/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c

@@ -0,0 +1,801 @@
+/***************************************************************************//**
+ * @file
+ * @brief PA power conversion functions provided to the customer as source for
+ *   highest level of customization.
+ * @details This file contains the curves and logic that convert PA power
+ *   levels to dBm powers.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+// For details on how to use this plugin, see
+//   https://www.silabs.com/documents/public/application-notes/an1127-power-amplifier-power-conversion-functions.pdf
+
+#include "em_device.h"
+#if defined(_SILICON_LABS_32B_SERIES_2) || defined(SIMULATION_DEVICE)
+#include "em_cmu.h"
+#else
+#include "sl_clock_manager.h"
+#endif
+
+#include "pa_conversions_efr32.h"
+#include "rail.h"
+
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+
+static RAIL_TxPowerCurvesConfigAlt_t powerCurvesState;
+
+// Make sure SUPPORTED_PA_INDICES match the per-platform PA curves
+// provided by RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT and resulting
+// RAIL_TxPowerCurvesConfigAlt_t!
+#ifndef SUPPORTED_PA_INDICES
+#if defined(_SILICON_LABS_32B_SERIES_1)
+#define SUPPORTED_PA_INDICES {                   \
+    0U,        /* 2P4GIG_HP  */                  \
+    RAIL_NUM_PA, /* 2P4GIG_MP  */                \
+    1U,        /* 2P4GIG_LP  */                  \
+    RAIL_NUM_PA, /* 2P4GIG_LLP */                \
+    RAIL_NUM_PA, /* 2P4GIG_HIGHEST */            \
+    RAIL_NUM_PA, /* SUBGIG_POWERSETTING_TABLE */ \
+    2U,        /* SUBGIG_HP */                   \
+    /* The rest are unsupported */               \
+}
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 1)
+#define SUPPORTED_PA_INDICES {     \
+    0U,        /* 2P4GIG_HP  */    \
+    1U,        /* 2P4GIG_MP  */    \
+    2U,        /* 2P4GIG_LP  */    \
+    /* The rest are unsupported */ \
+}
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 2)
+#define SUPPORTED_PA_INDICES {     \
+    0U,        /* 2P4GIG_HP  */    \
+    RAIL_NUM_PA, /* 2P4GIG_MP  */  \
+    1U,        /* 2P4GIG_LP  */    \
+    /* The rest are unsupported */ \
+}
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
+#define SUPPORTED_PA_INDICES {                   \
+    RAIL_NUM_PA, /* 2P4GIG_HP  */                \
+    RAIL_NUM_PA, /* 2P4GIG_MP  */                \
+    RAIL_NUM_PA, /* 2P4GIG_LP  */                \
+    RAIL_NUM_PA, /* 2P4GIG_LLP */                \
+    RAIL_NUM_PA, /* 2P4GIG_HIGHEST */            \
+    RAIL_NUM_PA, /* SUBGIG_POWERSETTING_TABLE */ \
+    0U,        /* SUBGIG_HP */                   \
+    1U,        /* SUBGIG_MP */                   \
+    2U,        /* SUBGIG_LP */                   \
+    3U,        /* SUBGIG_LLP */                  \
+    /* The rest are unsupported */               \
+}
+#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) || !defined(_SILICON_LABS_32B_SERIES_2))
+#define SUPPORTED_PA_INDICES {     \
+    0U,        /* 2P4GIG_HP  */    \
+    RAIL_NUM_PA, /* 2P4GIG_MP  */  \
+    1U,        /* 2P4GIG_LP  */    \
+    /* The rest are unsupported */ \
+}
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define SUPPORTED_PA_INDICES {                  \
+    RAIL_NUM_PA, /* 2P4GIG_HP  */               \
+    RAIL_NUM_PA, /* 2P4GIG_MP  */               \
+    RAIL_NUM_PA, /* 2P4GIG_LP  */               \
+    RAIL_NUM_PA, /* 2P4GIG_LLP */               \
+    RAIL_NUM_PA, /* 2P4GIG_HIGHEST */           \
+    0U,        /* SUBGIG_POWERSETTING_TABLE */  \
+    RAIL_NUM_PA, /* SUBGIG_HP */                \
+    RAIL_NUM_PA, /* SUBGIG_MP */                \
+    RAIL_NUM_PA, /* SUBGIG_LP */                \
+    RAIL_NUM_PA, /* SUBGIG_LLP */               \
+    RAIL_NUM_PA, /* SUBGIG_HIGHEST */           \
+    1U,        /* OFDM_PA_POWERSETTING_TABLE */ \
+}
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)
+#define SUPPORTED_PA_INDICES {     \
+    0U,        /* 2P4GIG_HP  */    \
+    RAIL_NUM_PA, /* 2P4GIG_MP  */  \
+    1U,        /* 2P4GIG_LP  */    \
+    /* The rest are unsupported */ \
+}
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)
+#define SUPPORTED_PA_INDICES {                   \
+    0U,        /* 2P4GIG_HP  */                  \
+    RAIL_NUM_PA, /* 2P4GIG_MP  */                \
+    RAIL_NUM_PA, /* 2P4GIG_LP  */                \
+    RAIL_NUM_PA, /* 2P4GIG_LLP */                \
+    RAIL_NUM_PA, /* 2P4GIG_HIGHEST */            \
+    RAIL_NUM_PA, /* SUBGIG_POWERSETTING_TABLE */ \
+    1U,        /* SUBGIG_HP */                   \
+    2U,        /* SUBGIG_MP */                   \
+    3U,        /* SUBGIG_LP */                   \
+    4U,        /* SUBGIG_LLP */                  \
+    /* The rest are unsupported */               \
+}
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)
+#define SUPPORTED_PA_INDICES {     \
+    0U,        /* 2P4GIG_HP  */    \
+    RAIL_NUM_PA, /* 2P4GIG_MP  */  \
+    1U,        /* 2P4GIG_LP  */    \
+    /* The rest are unsupported */ \
+}
+#else
+#error "unknown platform"
+#endif
+#endif
+
+static const uint8_t supportedPaIndices[] = SUPPORTED_PA_INDICES;
+
+#if defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
+  #define PA_CONVERSION_MINIMUM_PWRLVL 1U
+#else
+  #define PA_CONVERSION_MINIMUM_PWRLVL 0U
+#endif
+
+//   This macro is defined when Silicon Labs builds this into the library as WEAK
+//   to ensure it can be overriden by customer versions of these functions. The macro
+//   should *not* be defined in a customer build.
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurves_t *RAIL_GetTxPowerCurve(RAIL_TxPowerMode_t mode)
+{
+  static RAIL_TxPowerCurves_t powerCurves;
+  RAIL_TxPowerLevel_t maxPowerLevel, minPowerLevel;
+  if (RAIL_SupportsTxPowerModeAlt(RAIL_EFR32_HANDLE,
+                                  &mode,
+                                  &maxPowerLevel,
+                                  &minPowerLevel)
+      && (mode < sizeof(supportedPaIndices))
+      && (supportedPaIndices[mode] < RAIL_NUM_PA)) {
+    const RAIL_PaDescriptor_t *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]];
+    const RAIL_TxPowerCurveAlt_t *curve = modeInfo->conversion.powerCurve;
+    // Check for an invalid power curve
+    if (curve == NULL) {
+      return NULL;
+    }
+
+#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+    if (modeInfo->algorithm == RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) {
+      powerCurves.maxPower = modeInfo->maxPowerDbm;
+      powerCurves.minPower = modeInfo->minPowerDbm;
+      // Mapping table does not have RAIL_TxPowerCurveSegment_t segments
+      powerCurves.powerParams = NULL;
+    } else
+#endif
+    {
+      powerCurves.maxPower = curve->maxPower;
+      powerCurves.minPower = curve->minPower;
+      powerCurves.powerParams = &curve->powerParams[0];
+    }
+    return &powerCurves;
+  }
+  return NULL;
+}
+
+// This function will not be supported for any parts after efr32xg1x
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+RAIL_Status_t RAIL_InitTxPowerCurves(const RAIL_TxPowerCurvesConfig_t *config)
+{
+#ifdef _SILICON_LABS_32B_SERIES_1
+  // First PA is 2.4 GHz high power, using a piecewise fit
+  RAIL_PaDescriptor_t *current = &powerCurvesState.curves[0];
+  current->algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR;
+  current->segments = config->piecewiseSegments;
+  current->min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN;
+  current->max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX;
+  static RAIL_TxPowerCurveAlt_t txPower2p4 = {
+    .minPower = 0U,
+    .maxPower = 0U,
+    .powerParams = { // The current max number of piecewise segments is 8
+      { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U },
+      { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U },
+    }
+  };
+  txPower2p4.maxPower = config->txPowerSgCurves->maxPower;
+  txPower2p4.minPower = config->txPowerSgCurves->minPower;
+  (void) memcpy(&txPower2p4.powerParams[0],
+                config->txPowerSgCurves->powerParams,
+                config->piecewiseSegments * sizeof(RAIL_TxPowerCurveSegment_t));
+  current->conversion.powerCurve = &txPower2p4;
+
+  // Second PA is 2.4 GHz low power, using a mapping table
+  current = &powerCurvesState.curves[1];
+  current->algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE;
+  current->segments = 0U;
+  current->min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN;
+  current->max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX;
+  current->conversion.mappingTable = config->txPower24LpCurves;
+
+  // Third and final PA is Sub-GHz, using a piecewise fit
+  current = &powerCurvesState.curves[2];
+  current->algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR;
+  current->segments = config->piecewiseSegments;
+  current->min = RAIL_TX_POWER_LEVEL_SUBGIG_MIN;
+  current->max = RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX;
+  static RAIL_TxPowerCurveAlt_t txPowerSubGig = {
+    .minPower = 0U,
+    .maxPower = 0U,
+    .powerParams = { // The current max number of piecewise segments is 8
+      { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U },
+      { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U },
+    }
+  };
+  txPowerSubGig.maxPower = config->txPowerSgCurves->maxPower;
+  txPowerSubGig.minPower = config->txPowerSgCurves->minPower;
+  (void) memcpy(&txPowerSubGig.powerParams[0],
+                config->txPowerSgCurves->powerParams,
+                config->piecewiseSegments * sizeof(RAIL_TxPowerCurveSegment_t));
+  current->conversion.powerCurve = &txPowerSubGig;
+
+  return RAIL_STATUS_NO_ERROR;
+#else
+  (void) config;
+  return RAIL_STATUS_INVALID_CALL;
+#endif
+}
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+RAIL_Status_t RAIL_InitTxPowerCurvesAlt(const RAIL_TxPowerCurvesConfigAlt_t *config)
+{
+  RAIL_Status_t status = RAIL_VerifyTxPowerCurves(config);
+  if (status == RAIL_STATUS_NO_ERROR) {
+    powerCurvesState = *config;
+  }
+  return status;
+}
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+const RAIL_PaPowerSetting_t *RAIL_GetPowerSettingTable(RAIL_Handle_t railHandle, RAIL_TxPowerMode_t mode,
+                                                       RAIL_TxPower_t *minPower, RAIL_TxPower_t *maxPower,
+                                                       RAIL_TxPowerLevel_t *step)
+{
+  (void)railHandle;
+#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+  if ((mode < sizeof(supportedPaIndices))
+      && (supportedPaIndices[mode] < RAIL_NUM_PA)) {
+    RAIL_PaDescriptor_t *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]];
+    *minPower = modeInfo->minPowerDbm;
+    *maxPower = modeInfo->maxPowerDbm;
+    *step = modeInfo->step;
+    return (RAIL_PaPowerSetting_t*)(modeInfo->conversion.mappingTable);
+  }
+  return NULL;
+#else
+  (void)mode;
+  (void)minPower;
+  (void)maxPower;
+  (void)step;
+  return NULL;
+#endif
+}
+#endif // RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+RAIL_Status_t RAIL_ConvertDbmToPowerSettingEntry(RAIL_Handle_t railHandle,
+                                                 RAIL_TxPowerMode_t mode,
+                                                 RAIL_TxPower_t power,
+                                                 RAIL_TxPowerSettingEntry_t *powerSettingInfo)
+{
+  (void)railHandle;
+#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+  if ((mode < sizeof(supportedPaIndices))
+      && (supportedPaIndices[mode] < RAIL_NUM_PA)) {
+    RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]];
+    if (modeInfo->algorithm == RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) {
+      RAIL_TxPower_t minPower = modeInfo->minPowerDbm;
+      RAIL_TxPower_t maxPower = modeInfo->maxPowerDbm;
+      RAIL_TxPowerLevel_t step = modeInfo->step;
+
+      // Cap the power to within the range of the mapping table
+      if (power < minPower) {
+        power = minPower;
+      } else if (power > maxPower) {
+        power = maxPower;
+      } else {
+        // Power level is within bounds (MISRA required else)
+      }
+
+      // Calculate indices
+      uint32_t maxIndex = (uint32_t)((maxPower - minPower) / step);
+      uint32_t powerIndex = (uint32_t)((power - minPower) / step);
+
+      // Ensure powerIndex is within bounds
+      if (powerIndex > maxIndex) {
+        powerIndex = maxIndex;
+      }
+
+      RAIL_PaPowerSetting_t powerSetting = modeInfo->conversion.mappingTable[powerIndex];
+
+      while ((powerIndex > 0U)
+             && (powerSetting == (RAIL_PaPowerSetting_t)modeInfo->conversion.mappingTable[powerIndex - 1U])) {
+        powerIndex--;
+      }
+      power = minPower + ((RAIL_TxPower_t)powerIndex * step);
+
+      powerSettingInfo->paPowerSetting = powerSetting;
+      powerSettingInfo->minPaPowerDdbm = minPower;
+      powerSettingInfo->maxPaPowerDdbm = maxPower;
+      powerSettingInfo->currentPaPowerDdbm = power;
+      return RAIL_STATUS_NO_ERROR;
+    }
+  }
+  return RAIL_STATUS_INVALID_CALL;
+#else
+  (void) mode;
+  (void) power;
+  (void) powerSettingInfo;
+  return RAIL_STATUS_INVALID_CALL;
+#endif //RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+}
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle,
+                                         RAIL_TxPowerMode_t mode,
+                                         RAIL_TxPower_t power)
+{
+  (void)railHandle;
+#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+  // Powersetting tables do not have raw powerlevels.
+  // Could use RAIL_ConvertDbmToPowerSettingEntry
+  (void)mode;
+  (void) power;
+#else
+
+  // When a channel dBm limitation greater than or equal to \ref RAIL_TX_POWER_MAX
+  // is converted to raw units, the max RAIL_TxPowerLevel_t will be
+  // returned. When compared to the current power level of the PA,
+  // it will always be greater, indicating that no power coercion
+  // is necessary to comply with channel limitations.
+  if (power >= RAIL_TX_POWER_MAX) {
+    return 255U;
+  }
+
+  if ((mode < sizeof(supportedPaIndices))
+      && (supportedPaIndices[mode] < RAIL_NUM_PA)) {
+    RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]];
+    uint32_t minPowerLevel = MAX(modeInfo->min, PA_CONVERSION_MINIMUM_PWRLVL);
+
+    // If we're in low power mode, just use the simple lookup table
+    if (modeInfo->algorithm == RAIL_PA_ALGORITHM_MAPPING_TABLE) {
+      // Binary search through the lookup table to find the closest power level
+      // without going over.
+      uint32_t lower = 0U;
+      // Track the high side of the estimate
+      uint32_t powerIndex = modeInfo->max - minPowerLevel;
+
+      while (lower < powerIndex) {
+        // Calculate the midpoint of the current range
+        uint32_t index = powerIndex - (powerIndex - lower) / 2U;
+        if (power < modeInfo->conversion.mappingTable[index]) {
+          powerIndex = index - 1U;
+        } else {
+          lower = index;
+        }
+      }
+      return (RAIL_TxPowerLevel_t)(powerIndex + minPowerLevel);
+    }
+
+    // Here we know we're using the piecewise linear conversion
+    RAIL_TxPowerCurveAlt_t const *paParams = modeInfo->conversion.powerCurve;
+    // Check for valid paParams before using them
+    if (paParams == NULL) {
+      return 0U;
+    }
+
+    // Cap the power based on the PA settings.
+    if (power > paParams->maxPower) {
+      // If we go above the maximum dbm the chip supports
+      // Then provide maximum powerLevel
+      power = paParams->maxPower;
+    } else if (power < paParams->minPower) {
+      // If we go below the minimum we want included in the curve fit, force it.
+      power = paParams->minPower;
+    } else {
+      // Do nothing, power is OK
+    }
+    // Map the power value to a 0 - 7 curveIndex value
+    //There are 8 segments of step size of RAIL_TX_POWER_CURVE_INCREMENT in deci dBm
+    //starting from maximum RAIL_TX_POWER_CURVE_MAX in deci dBm
+    // These are just starting points to give the code
+    // a rough idea of which segment to use, based on
+    // how they were fit. Adjustments are made later on
+    // if this turns out to be incorrect.
+    RAIL_TxPower_t txPowerMax = RAIL_TX_POWER_CURVE_DEFAULT_MAX;
+    RAIL_TxPower_t txPowerIncrement = RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT;
+    int16_t curveIndex = 0;
+    // if the first curve segment starts with RAIL_TX_POWER_LEVEL_INVALID
+    //It is an extra curve segment to depict the maxpower and increment
+    // (in deci-dBm) used while generating the curves.
+    // The extra segment is only present when curve segment is generated by
+    //using values different than the default - RAIL_TX_POWER_CURVE_DEFAULT_MAX
+    // and RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT.
+    if ((paParams->powerParams[0].maxPowerLevel) == RAIL_TX_POWER_LEVEL_INVALID) {
+      curveIndex += 1;
+      txPowerMax = (RAIL_TxPower_t) paParams->powerParams[0].slope;
+      txPowerIncrement = (RAIL_TxPower_t) paParams->powerParams[0].intercept;
+    }
+
+    curveIndex += (txPowerMax - power) / txPowerIncrement;
+    if ((curveIndex > ((int16_t)modeInfo->segments - 1))
+        || (curveIndex < 0)) {
+      curveIndex = ((int16_t)modeInfo->segments - 1);
+    }
+
+    uint32_t powerLevel;
+    do {
+      // Select the correct piecewise segment to use for conversion.
+      RAIL_TxPowerCurveSegment_t const *powerParams =
+        &paParams->powerParams[curveIndex];
+
+      // powerLevel can only go down to 0.
+      int32_t powerLevelInt = powerParams->intercept + ((int32_t)powerParams->slope * (int32_t)power);
+      if (powerLevelInt < 0) {
+        powerLevel = 0U;
+      } else {
+        powerLevel = (uint32_t) powerLevelInt;
+      }
+      // RAIL_LIB-8330: Modified from adding 500 to adding 92, this was tested on xg21 as being the highest
+      // number we can use without exceeding the requested power in dBm
+      powerLevel = ((powerLevel + 92U) / 1000U);
+
+      // In case it turns out the resultant power level was too low and we have
+      // to recalculate with the next curve...
+      curveIndex++;
+    } while ((curveIndex < (int16_t)modeInfo->segments)
+             && (powerLevel <= paParams->powerParams[curveIndex].maxPowerLevel));
+
+    // We already know that curveIndex is at most modeInfo->segments
+    if (powerLevel > paParams->powerParams[curveIndex - 1].maxPowerLevel) {
+      powerLevel = paParams->powerParams[curveIndex - 1].maxPowerLevel;
+    }
+
+    // If we go below the minimum we want included in the curve fit, force it.
+    if (powerLevel < minPowerLevel) {
+      powerLevel = minPowerLevel;
+    }
+
+    return (RAIL_TxPowerLevel_t)powerLevel;
+  }
+#endif // RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+  return 0U;
+}
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+RAIL_TxPower_t RAIL_ConvertRawToDbm(RAIL_Handle_t railHandle,
+                                    RAIL_TxPowerMode_t mode,
+                                    RAIL_TxPowerLevel_t powerLevel)
+{
+  (void)railHandle;
+
+  if ((mode < sizeof(supportedPaIndices))
+      && (supportedPaIndices[mode] < RAIL_NUM_PA)) {
+    RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]];
+    if (modeInfo->algorithm == RAIL_PA_ALGORITHM_MAPPING_TABLE) {
+      // Limit the max power level
+      if (powerLevel > modeInfo->max) {
+        powerLevel = modeInfo->max;
+      }
+
+      // We 1-index low power PA power levels, but of course arrays are 0 indexed
+      powerLevel -= MAX(modeInfo->min, PA_CONVERSION_MINIMUM_PWRLVL);
+
+      //If the index calculation above underflowed, then provide the lowest array index.
+      if (powerLevel > (modeInfo->max - modeInfo->min)) {
+        powerLevel = 0U;
+      }
+      return modeInfo->conversion.mappingTable[powerLevel];
+    } else {
+#if defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
+      // Although 0 is a legitimate power on non-2.4 LP PA's and can be set via
+      // "RAIL_SetTxPower(railHandle, 0)" it is MUCH lower than power
+      // level 1 (approximately -50 dBm). Including it in the piecewise
+      // linear fit would skew the curve substantially, so we exclude it
+      // from the conversion.
+      if (powerLevel == 0U) {
+        return -500;
+      }
+#endif
+
+      RAIL_TxPowerCurveAlt_t const *powerCurve = modeInfo->conversion.powerCurve;
+      // Check for a valid powerCurve pointer before using it
+      if (powerCurve == NULL) {
+        return RAIL_TX_POWER_MIN;
+      }
+
+      RAIL_TxPowerCurveSegment_t const *powerParams = powerCurve->powerParams;
+
+      // Hard code the extremes (i.e. don't use the curve fit) in order
+      // to make it clear that we are reaching the extent of the chip's
+      // capabilities
+      if (powerLevel <= modeInfo->min) {
+        return powerCurve->minPower;
+      } else if (powerLevel >= modeInfo->max) {
+        return powerCurve->maxPower;
+      } else {
+        // Power level is within bounds (MISRA required else)
+      }
+
+      // Figure out which parameter to use based on the power level
+      uint8_t x = 0;
+      uint8_t upperBound = modeInfo->segments - 1U;
+
+      // If the first curve segment starts with RAIL_TX_POWER_LEVEL_INVALID,
+      // then it is an additional curve segment that stores maxpower and increment
+      // (in deci-dBm) used to generate the curves.
+      // The extra info segment is present only if the curves were generated using
+      // values other than default - RAIL_TX_POWER_CURVE_DEFAULT_MAX and
+      // RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT.
+      if ((powerParams[0].maxPowerLevel) == RAIL_TX_POWER_LEVEL_INVALID) {
+        x = 1U; // skip over the first entry
+      }
+
+      for (; x < upperBound; x++) {
+        if (powerParams[x + 1U].maxPowerLevel < powerLevel) {
+          break;
+        }
+      }
+      int32_t power;
+      power = ((1000 * (int32_t)(powerLevel)) - powerParams[x].intercept);
+      power = ((power + ((int32_t)powerParams[x].slope / 2)) / (int32_t)powerParams[x].slope);
+
+      if (power > powerCurve->maxPower) {
+        return powerCurve->maxPower;
+      } else if (power < powerCurve->minPower) {
+        return powerCurve->minPower;
+      } else {
+        return (RAIL_TxPower_t)power;
+      }
+    }
+  }
+  return RAIL_TX_POWER_MIN;
+}
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+RAIL_Status_t RAIL_GetTxPowerCurveLimits(RAIL_Handle_t railHandle,
+                                         RAIL_TxPowerMode_t mode,
+                                         RAIL_TxPower_t *maxPower,
+                                         RAIL_TxPower_t *increment)
+{
+  (void)railHandle;
+  if ((mode < sizeof(supportedPaIndices))
+      && (supportedPaIndices[mode] < RAIL_NUM_PA)) {
+    RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]];
+#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+    if (modeInfo->algorithm == RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) {
+      *maxPower = modeInfo->maxPowerDbm;
+      *increment = modeInfo->step;
+      return RAIL_STATUS_NO_ERROR;
+    }
+#endif
+
+    //The power max info only for available Linear fit
+    if (modeInfo->algorithm == RAIL_PA_ALGORITHM_MAPPING_TABLE) {
+      return RAIL_STATUS_INVALID_CALL;
+    }
+    *maxPower = RAIL_TX_POWER_CURVE_DEFAULT_MAX;
+    *increment = RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT;
+    RAIL_TxPowerCurveAlt_t const *paParams = modeInfo->conversion.powerCurve;
+    if ((paParams->powerParams[0].maxPowerLevel) == RAIL_TX_POWER_LEVEL_INVALID) {
+      *maxPower = paParams->powerParams[0].slope;
+      *increment = (RAIL_TxPower_t)paParams->powerParams[0].intercept;
+    }
+    return RAIL_STATUS_NO_ERROR;
+  }
+  return RAIL_STATUS_INVALID_PARAMETER;
+}
+
+// This macro is defined when Silicon Labs builds curves into the library as WEAK
+// to ensure it can be overriden by customer versions of these functions. It
+// should *not* be defined in a customer build.
+#if !defined(RAIL_PA_CONVERSIONS_WEAK) && !defined(HAL_CONFIG)
+
+#include "sl_rail_util_pa_config.h"
+
+void sl_rail_util_pa_init(void)
+{
+#if SL_RAIL_UTIL_PA_VOLTAGE_MV > 1800
+  (void)RAIL_InitTxPowerCurvesAlt(&RAIL_TxPowerCurvesVbat);
+#else
+  (void)RAIL_InitTxPowerCurvesAlt(&RAIL_TxPowerCurvesDcdc);
+#endif
+#if SL_RAIL_UTIL_PA_CALIBRATION_ENABLE
+  RAIL_EnablePaCal(true);
+#else
+  RAIL_EnablePaCal(false);
+#endif
+}
+
+#if RAIL_SUPPORTS_2P4GHZ_BAND
+static RAIL_TxPowerConfig_t txPowerConfig2p4Ghz = {
+  .mode = SL_RAIL_UTIL_PA_SELECTION_2P4GHZ,
+  .voltage = SL_RAIL_UTIL_PA_VOLTAGE_MV,
+  .rampTime = SL_RAIL_UTIL_PA_RAMP_TIME_US,
+};
+#endif
+RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_2p4ghz(void)
+{
+#if RAIL_SUPPORTS_2P4GHZ_BAND
+  return &txPowerConfig2p4Ghz;
+#else
+  return NULL;
+#endif
+}
+
+#if RAIL_SUPPORTS_SUBGHZ_BAND
+static RAIL_TxPowerConfig_t txPowerConfigSubGhz = {
+  .mode = SL_RAIL_UTIL_PA_SELECTION_SUBGHZ,
+  .voltage = SL_RAIL_UTIL_PA_VOLTAGE_MV,
+  .rampTime = SL_RAIL_UTIL_PA_RAMP_TIME_US,
+};
+#endif
+RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_subghz(void)
+{
+#if RAIL_SUPPORTS_SUBGHZ_BAND
+  return &txPowerConfigSubGhz;
+#else
+  return NULL;
+#endif
+}
+
+#if RAIL_SUPPORTS_OFDM_PA
+#ifndef SL_RAIL_UTIL_PA_SELECTION_OFDM
+#define SL_RAIL_UTIL_PA_SELECTION_OFDM RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE
+#endif
+static RAIL_TxPowerConfig_t txPowerConfigOFDM = {
+  .mode = SL_RAIL_UTIL_PA_SELECTION_OFDM,
+  .voltage = SL_RAIL_UTIL_PA_VOLTAGE_MV,
+};
+#endif // RAIL_SUPPORTS_OFDM_PA
+RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_ofdm(void)
+{
+#if RAIL_SUPPORTS_OFDM_PA
+  return &txPowerConfigOFDM;
+#else
+  return NULL;
+#endif // RAIL_SUPPORTS_OFDM_PA
+}
+
+void sl_rail_util_pa_on_channel_config_change(RAIL_Handle_t rail_handle,
+                                              const RAIL_ChannelConfigEntry_t *entry)
+{
+  if (!RAIL_IsPaAutoModeEnabled(rail_handle)) {
+    RAIL_TxPowerConfig_t currentTxPowerConfig;
+    RAIL_TxPowerConfig_t *newTxPowerConfigPtr;
+    RAIL_Status_t status;
+
+    // Get current TX Power Config.
+    status = RAIL_GetTxPowerConfig(rail_handle, &currentTxPowerConfig);
+    if (status != RAIL_STATUS_NO_ERROR) {
+      while (true) {
+      } // Error: Can't get TX Power Config
+    }
+
+#if RAIL_SUPPORTS_DUAL_BAND
+    // Determine new TX Power Config.
+    if (entry->baseFrequency < 1000000000UL) {
+      newTxPowerConfigPtr = &txPowerConfigSubGhz;
+    } else {
+      newTxPowerConfigPtr = &txPowerConfig2p4Ghz;
+    }
+#else
+    (void) entry;
+#if RAIL_SUPPORTS_2P4GHZ_BAND
+    newTxPowerConfigPtr = &txPowerConfig2p4Ghz;
+#else
+    newTxPowerConfigPtr = &txPowerConfigSubGhz;
+#endif
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG
+    if (currentTxPowerConfig.mode == RAIL_TX_POWER_MODE_NONE) {
+#if RAIL_SUPPORTS_OFDM_PA
+      if (RAIL_SupportsTxPowerModeAlt(rail_handle,
+                                      &txPowerConfigOFDM.mode,
+                                      NULL, NULL)) {
+        // Apply OFDM Power Config.
+        status = RAIL_ConfigTxPower(rail_handle, &txPowerConfigOFDM);
+        if (status != RAIL_STATUS_NO_ERROR) {
+          while (true) {
+          } // Error: Can't set TX Power Config
+        }
+        // Set default TX power after RAIL_ConfigTxPower.
+        status = RAIL_SetTxPowerDbm(rail_handle, SL_RAIL_UTIL_PA_POWER_DECI_DBM);
+        if (status != RAIL_STATUS_NO_ERROR) {
+          while (true) {
+          } // Error: Can't set TX Power
+        }
+      }
+#endif // RAIL_SUPPORTS_OFDM_PA
+      // Apply FSK Power Config.
+      status = RAIL_ConfigTxPower(rail_handle, newTxPowerConfigPtr);
+      if (status != RAIL_STATUS_NO_ERROR) {
+        while (true) {
+        } // Error: Can't set TX Power Config
+      }
+      // Set default TX power after RAIL_ConfigTxPower.
+      status = RAIL_SetTxPowerDbm(rail_handle, SL_RAIL_UTIL_PA_POWER_DECI_DBM);
+      if (status != RAIL_STATUS_NO_ERROR) {
+        while (true) {
+        } // Error: Can't set TX Power
+      }
+    }
+#else
+    // Call RAIL_ConfigTxPower only if TX Power Config mode has changed.
+    if (currentTxPowerConfig.mode != newTxPowerConfigPtr->mode) {
+      // Save current TX power before RAIL_ConfigTxPower (because not preserved).
+      RAIL_TxPower_t txPowerDeciDbm;
+      if (currentTxPowerConfig.mode == RAIL_TX_POWER_MODE_NONE) {
+        txPowerDeciDbm = SL_RAIL_UTIL_PA_POWER_DECI_DBM;
+      } else {
+        txPowerDeciDbm = RAIL_GetTxPowerDbm(rail_handle);
+      }
+
+      // Apply new TX Power Config.
+      status = RAIL_ConfigTxPower(rail_handle, newTxPowerConfigPtr);
+      if (status != RAIL_STATUS_NO_ERROR) {
+        while (true) {
+        } // Error: Can't set TX Power Config
+      }
+      // Restore TX power after RAIL_ConfigTxPower.
+      status = RAIL_SetTxPowerDbm(rail_handle, txPowerDeciDbm);
+      if (status != RAIL_STATUS_NO_ERROR) {
+        while (true) {
+        } // Error: Can't set TX Power
+      }
+      // If requested a HIGHEST setting, update it with the real one selected
+      // to short-circuit the next time through here since HIGHEST never
+      // matches the real PA returned by RAIL_GetTxPowerConfig(), causing
+      // reconfiguration of the same PA on every callback.
+      if (false
+         #ifdef  RAIL_TX_POWER_MODE_2P4GIG_HIGHEST
+          || (newTxPowerConfigPtr->mode == RAIL_TX_POWER_MODE_2P4GIG_HIGHEST)
+         #endif
+         #ifdef  RAIL_TX_POWER_MODE_SUBGIG_HIGHEST
+          || (newTxPowerConfigPtr->mode == RAIL_TX_POWER_MODE_SUBGIG_HIGHEST)
+         #endif
+          ) {
+        (void) RAIL_GetTxPowerConfig(rail_handle, &currentTxPowerConfig);
+        newTxPowerConfigPtr->mode = currentTxPowerConfig.mode;
+      }
+    }
+#endif
+  } // !RAIL_IsPaAutoModeEnabled
+}
+#endif // !RAIL_PA_CONVERSIONS_WEAK

Libs/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.h

@@ -0,0 +1,188 @@
+/***************************************************************************//**
+ * @file
+ * @brief PA power conversion functions provided to the customer as source for
+ *   highest level of customization.
+ * @details This file contains the curves and logic that convert PA power
+ *   levels to dBm powers.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef PA_CONVERSIONS_EFR32_H
+#define PA_CONVERSIONS_EFR32_H
+
+#include "rail_types.h"
+
+// This macro is defined when Silicon Labs builds curves into the library as WEAK
+// to ensure it can be overriden by customer versions of these functions. It
+// should *not* be defined in a customer build.
+#ifndef  RAIL_PA_CONVERSIONS_WEAK
+#ifdef   SL_RAIL_UTIL_PA_CONFIG_HEADER
+#include SL_RAIL_UTIL_PA_CONFIG_HEADER
+#else
+#include "sl_rail_util_pa_conversions_efr32_config.h"
+#endif
+#endif
+
+#ifdef HAL_CONFIG
+#include "hal-config.h"
+#ifdef HAL_PA_CURVE_HEADER
+#ifdef SL_RAIL_UTIL_PA_CURVE_HEADER
+#undef SL_RAIL_UTIL_PA_CURVE_HEADER
+#endif
+#define SL_RAIL_UTIL_PA_CURVE_HEADER HAL_PA_CURVE_HEADER
+#endif
+#endif
+
+#ifdef   SL_RAIL_UTIL_PA_CURVE_TYPES
+#include SL_RAIL_UTIL_PA_CURVE_TYPES
+#else
+#include "pa_curve_types_efr32.h"
+#endif
+
+#ifdef   SL_RAIL_UTIL_PA_CURVE_HEADER
+#include SL_RAIL_UTIL_PA_CURVE_HEADER
+#else
+#include "pa_curves_efr32.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup PA_Curve_Conversions PA Curve Conversions
+ * @ingroup PA
+ * @{
+ */
+
+/// The curves to be used when battery voltage powers transmission
+extern const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat;
+
+/// The curves to be used when the DC-DC converter powers transmission
+extern const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc;
+
+/**
+ * Initialize Transmit power curves.
+ *
+ * @param[in] config A pointer to the custom TX power curves.
+ * @return Status code indicating success of the function call.
+ *
+ * @deprecated function is no longer supported.
+ *   Must use \ref RAIL_InitTxPowerCurvesAlt() instead.
+ */
+RAIL_Status_t RAIL_InitTxPowerCurves(const RAIL_TxPowerCurvesConfig_t *config);
+
+/**
+ * Initialize TxPower curves.
+ *
+ * @param[in] config A pointer to the custom TX power curves to use.
+ * @return Status code indicating success of the function call.
+ */
+RAIL_Status_t RAIL_InitTxPowerCurvesAlt(const RAIL_TxPowerCurvesConfigAlt_t *config);
+
+/**
+ * Gets the curve that should be used for conversion functions based on the
+ * current PA configuration.
+ *
+ * @param[in] mode PA mode whose curves are needed.
+ * @return A pointer to the \ref RAIL_TxPowerCurves_t that are used for conversion functions.
+ *
+ * @note: If the mode is not supported by the the chip,
+ *   then NULL will be returned.
+ */
+RAIL_TxPowerCurves_t const *RAIL_GetTxPowerCurve(RAIL_TxPowerMode_t mode);
+
+/**
+ * Gets the maximum power in deci-dBm that should be used for calculating
+ * the segments and to find right curve segment to convert Dbm to raw power
+ * level for a specific PA.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] mode PA mode whose curves are needed.
+ * @param[out] maxpower A non-NULL pointer to memory allocated to hold
+ *   the max power in deci-dBm used in calculation of curve segments.
+ * @param[out] increment A non-NULL pointer to memory allocated to hold
+ *   the increment in deci-dBm used in calculation of curve segments.
+ * @return Status code indicating success of the function call.
+ *
+ * For the PAs with \ref RAIL_PaConversionAlgorithm_t
+ * \ref RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, if the curves are generated with
+ * maxPower and increment other than \ref RAIL_TX_POWER_CURVE_DEFAULT_MAX and
+ * \ref RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT respectively, then the first
+ * \ref RAIL_TxPowerCurveSegment_t has its maxPowerLevel equal to
+ * \ref RAIL_TX_POWER_LEVEL_INVALID and its slope and intercept stores the
+ * maxPower and increment in deci-dBm respectively.
+ */
+RAIL_Status_t RAIL_GetTxPowerCurveLimits(RAIL_Handle_t railHandle,
+                                         RAIL_TxPowerMode_t mode,
+                                         RAIL_TxPower_t *maxpower,
+                                         RAIL_TxPower_t *increment);
+
+/**
+ * Initialize PA TX Curves.
+ */
+void sl_rail_util_pa_init(void);
+
+/**
+ * Get a pointer to the TX Power Config 2.4 GHz structure.
+ *
+ * @return A pointer to the TX Power Config stucture.
+ */
+RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_2p4ghz(void);
+
+/**
+ * Get a pointer to the TX Power Config Sub-GHz structure.
+ *
+ * @return A pointer to the TX Power Config stucture.
+ */
+RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_subghz(void);
+
+/**
+ * Get a pointer to the TX Power Config OFDM structure.
+ *
+ * @return A pointer to the TX Power Config stucture.
+ */
+RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_ofdm(void);
+
+/**
+ * Provide a channel config change callback capable of configuring the PA
+ * correctly.
+ *
+ * @param[in] rail_handle The RAIL handle being passed into this callback.
+ * @param[in] entry A pointer to the channel config entry being switched
+ *   to by hardware.
+ */
+void sl_rail_util_pa_on_channel_config_change(RAIL_Handle_t rail_handle,
+                                              const RAIL_ChannelConfigEntry_t *entry);
+
+/** @} */ // PA_Curve_Conversions
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // PA_CONVERSIONS_EFR32_H

Libs/platform/radio/rail_lib/plugin/pa-conversions/pa_curve_types_efr32.h

@@ -0,0 +1,290 @@
+/***************************************************************************//**
+ * @file
+ * @brief PA power conversion curve types used by Silicon Labs PA power
+ *   conversion functions.
+ * @details This file contains the curve types needed convert PA power levels
+ *   to dBm powers.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef PA_CURVE_TYPES_EFR32_H
+#define PA_CURVE_TYPES_EFR32_H
+
+#include "rail_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup PA_Curve_Conversions PA Curve Conversions
+ * @ingroup PA
+ * @{
+ */
+
+/**
+ * @struct RAIL_TxPowerCurveSegment_t
+ *
+ * @brief Structure containing data defining each segment of the
+ *   deci-dBm to raw power level mapping curve fits.
+ *
+ * Note, these used in an equation of the form:
+ *
+ *    powerLevel * 1000 = slope * power + intercept
+ *
+ * powerLevel is the 0-252/0-248/1-7 values used in the RAIL_Get/SetTxPower()
+ * functions, and power is the actual output power of the PA, specified
+ * in deci-dBm.
+ *
+ * @note If the curves are generated with
+ *   maxPower and increment other than \ref RAIL_TX_POWER_CURVE_DEFAULT_MAX and
+ *   \ref RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT respectively, then the first
+ *   \ref RAIL_TxPowerCurveSegment_t has its maxPowerLevel equal to
+ *   \ref RAIL_TX_POWER_LEVEL_INVALID and its slope and intercept stores the
+ *   maxPower and increment in deci-dBm respectively.
+ */
+typedef struct RAIL_TxPowerCurveSegment {
+  /** The highest power level that this segment will be used to convert */
+  uint16_t maxPowerLevel;
+  /** slope of the line */
+  int16_t slope;
+  /** y-intercept of the line */
+  int32_t intercept;
+} RAIL_TxPowerCurveSegment_t;
+
+/**
+ * @struct RAIL_TxPowerCurves_t
+ *
+ * @brief Structure containing the min and max values for a given
+ *   PA and voltage supply combination (in deci-dBm).
+ */
+typedef struct RAIL_TxPowerCurves {
+  /** max deci-dBm value */
+  int16_t maxPower;
+  /** min deci-dBm value */
+  int16_t minPower;
+  /**
+   * Pointer to an array of \ref RAIL_TxPowerCurvesConfig_t::piecewiseSegments
+   * elements of \ref RAIL_TxPowerCurveSegment_t for deci-dBm to raw
+   * power level conversion fits.
+   */
+  const RAIL_TxPowerCurveSegment_t *powerParams;
+} RAIL_TxPowerCurves_t;
+
+/**
+ * @struct RAIL_TxPowerCurvesConfig_t
+ *
+ * @brief Structure containing curve fit information and other metadata
+ *   required to properly use the WEAK versions of RAIL_ConvertRawToDb
+ *   and RAIL_ConvertDbmToRaw.
+ */
+typedef struct RAIL_TxPowerCurvesConfig {
+  /**
+   * Pointer a RAIL_TxPowerCurves_t representing the piecewise linear segments
+   * of curves that map power level to power in dBm for the 2.4 GHz high power
+   * PA.
+   *
+   * @note By the default conversion implementation, segments must be specified
+   *   in decreasing power order. That is, the 0th entry of this array should be
+   *   used to convert the highest power (levels). Segment at position n is valid
+   *   from maxPowerLevel+1 from the segment at n+1 (or 0 if n is array length - 1)
+   *   to maxPowerLevel of segment n, inclusive.
+   */
+  const RAIL_TxPowerCurves_t *txPower24HpCurves;
+
+  /**
+   * Pointer a RAIL_TxPowerCurves_t representing the piecewise linear segments
+   * of curves that map power level to power in dBm for the subgig PA.
+   *
+   * @note By the default conversion implementation, segments must be specified
+   *   in decreasing power order. That is, the 0th entry of this array should be
+   *   used to convert the highest power (levels). Segment at position n is valid
+   *   from maxPowerLevel+1 from the segment at n+1 (or 0 if n is array length - 1)
+   *   to maxPowerLevel of segment n, inclusive.
+   */
+  const RAIL_TxPowerCurves_t *txPowerSgCurves;
+
+  /**
+   * Look up table for each of the power levels of the 2.4GHz low power
+   * amplifier and their equivalent deci-dB value.
+   */
+  const int16_t *txPower24LpCurves;
+  /**
+   * The number of piecewise segments provided to the PA in each of the four
+   * conversion curve fits. The default is 8, but regardless of the number, it
+   * must be the same for all curves.
+   */
+  uint8_t piecewiseSegments;
+} RAIL_TxPowerCurvesConfig_t;
+
+/**
+ * @enum RAIL_PaConversionAlgorithm_t
+ * @brief PA conversion algorithms types for converting between dBm and power levels
+ */
+RAIL_ENUM(RAIL_PaConversionAlgorithm_t) {
+  /** Piecewise linear fit */
+  RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+  /** Mapping table between quantities */
+  RAIL_PA_ALGORITHM_MAPPING_TABLE,
+  /** Mapping table between pa power settings and dBm values */
+  RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE,
+};
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+#define RAIL_PA_ALGORITHM_PIECEWISE_LINEAR               ((RAIL_PaConversionAlgorithm_t) RAIL_PA_ALGORITHM_PIECEWISE_LINEAR)
+#define RAIL_PA_ALGORITHM_MAPPING_TABLE                  ((RAIL_PaConversionAlgorithm_t) RAIL_PA_ALGORITHM_MAPPING_TABLE)
+#define RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE ((RAIL_PaConversionAlgorithm_t) RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE)
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+/**
+ * @struct RAIL_TxPowerCurveAlt_t
+ *
+ * @brief Structure containing the min and max values for a given
+ *   PA and voltage supply combination (in deci-dBm).
+ */
+typedef struct RAIL_TxPowerCurveAlt {
+  /** max deci-dBm value */
+  int16_t maxPower;
+  /** min deci-dBm value */
+  int16_t minPower;
+  /**
+   * Array of \ref RAIL_PaDescriptor_t::segments \ref RAIL_TxPowerCurveSegment_t
+   * structures for the deci-dBm to raw power level conversion fits.
+   */
+//Array does not have a size since it can be various sizes.
+//No further fields allowed after this one.
+  RAIL_TxPowerCurveSegment_t powerParams[];
+} RAIL_TxPowerCurveAlt_t;
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+#if defined(SL_RAIL_UTIL_PA_POWERSETTING_TABLE_VERSION)
+#if RAIL_SUPPORTS_COMMON_PA_INTERFACE
+#if SL_RAIL_UTIL_PA_POWERSETTING_TABLE_VERSION == 1
+/// The entry in the powersetting table have the below bitfields
+/// |15-14 =sub-mode|13-8:unused|7-0:scalor(stripe+slice)|
+/// Mask for submode
+#define SLI_RAIL_UTIL_PA_TABLE_SUBMODE_MASK 0xC000UL
+/// Shift for submode
+#define SLI_RAIL_UTIL_PA_TABLE_SUBMODE_SHIFT 14U
+/// Mask for scalor
+#define SLI_RAIL_UTIL_PATABLE_SCALOR_MASK 0xFFU
+/// Shift for scalor
+#define SLI_RAIL_UTIL_PA_TABLE_SCALOR_SHIFT 0U
+#endif //SL_RAIL_UTIL_PA_POWERSETTING_TABLE_VERSION == 1
+#endif //RAIL_SUPPORTS_COMMON_PA_INTERFACE
+#endif //defined(SL_RAIL_UTIL_PA_POWERSETTING_TABLE_VERSION)
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+/**
+ * @struct RAIL_PowerConversion_t
+ *
+ * @brief Union containing a pointer to algorithm-specific conversion data.
+ */
+typedef union RAIL_PowerConversion {
+  /**
+   * Pointer to a powerCurve containing line segment data for the curves
+   * corresponding to a specific PA.
+   *
+   * @note By the default conversion implementation, segments must be specified
+   *   in decreasing power order. That is, the 0th entry of this array should be
+   *   used to convert the highest power (levels). Segment at position n is valid
+   *   from maxPowerLevel+1 from the segment at n+1 (or 0 if n is array length - 1)
+   *   to maxPowerLevel of segment n, inclusive.
+   */
+  const RAIL_TxPowerCurveAlt_t *powerCurve;
+  /**
+   * Lookup table for PA's which use the mapping table algorithm for converting
+   * between deci-dBm and power levels.
+   */
+#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+#if RAIL_SUPPORTS_COMMON_PA_INTERFACE
+  const int16_t *mappingTable;
+#else
+  const int32_t *mappingTable;
+#endif
+#else
+  const int16_t *mappingTable;
+#endif
+} RAIL_PowerConversion_t;
+
+/**
+ * @struct RAIL_PaDescriptor_t
+ *
+ * @brief Struct containing specifics of PA configuration.
+ *   PA descriptor as used in the PA conversion functions.
+ */
+typedef struct RAIL_PaDescriptor {
+  /** Algorithm used to map dBm to power levels for this PA. */
+  RAIL_PaConversionAlgorithm_t algorithm;
+  /**
+   * The number of piecewise segments provided to the PA in a piecewise linear
+   * curve fit. The default is 8. Should be set to 0 when not using the
+   * piecewise linear algorithm.
+   */
+  uint8_t segments;
+  /** Min power level for this PA. */
+  RAIL_TxPowerLevel_t min;
+  /** Max power level for this PA. */
+  RAIL_TxPowerLevel_t max;
+#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
+  /** step size in deci-dBm between entries in table. */
+  RAIL_TxPowerLevel_t step;
+  /** structure padding. */
+  uint8_t padding;
+  /** structure padding. */
+  uint16_t padding2;
+  /** Min power in deci-dBm for this PA. */
+  RAIL_TxPower_t minPowerDbm;
+  /** Max power in deci-dBm for this PA. */
+  RAIL_TxPower_t maxPowerDbm;
+#endif
+  /** Union containing a pointer to algorithm-specific conversion data. */
+  RAIL_PowerConversion_t conversion;
+} RAIL_PaDescriptor_t;
+
+/**
+ * @struct RAIL_TxPowerCurvesConfigAlt_t
+ *
+ * @brief More generic structure containing information about
+ *   piecewise linear curves and mapping tables, instead of specific PA's.
+ */
+typedef struct RAIL_TxPowerCurvesConfigAlt {
+  /** The curves for each PA. */
+  RAIL_PaDescriptor_t curves[RAIL_NUM_PA];
+  /** Signature used for validation of the curves configuruation. */
+  uint32_t signature;
+  /** PA VDD voltage, in millivolts. */
+  uint16_t paVoltage;
+} RAIL_TxPowerCurvesConfigAlt_t;
+
+/** @} */ // PA_Curve_Conversions
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // PA_CURVE_TYPES_EFR32_H

Libs/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c

@@ -0,0 +1,383 @@
+/***************************************************************************//**
+ * @file
+ * @brief Default PA power conversion structures with curves calibrated by the
+ *   RAIL team.
+ * @details This file contains the curves that convert PA power levels to dBm
+ *   powers.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+// This entire file should never be used on FCC pre-certified modules
+#ifndef _SILICON_LABS_MODULE
+
+#include "em_device.h"
+#include "pa_conversions_efr32.h"
+
+#if defined(_SILICON_LABS_32B_SERIES_1)
+
+static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = {
+  RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER,
+  RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER,
+  RAIL_PA_CURVES_2P4_HP_VBAT_CURVES
+};
+static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataSgVbat = {
+  RAIL_PA_CURVES_SG_VBAT_MAX_POWER,
+  RAIL_PA_CURVES_SG_VBAT_MIN_POWER,
+  RAIL_PA_CURVES_SG_VBAT_CURVES
+};
+static const int16_t RAIL_curves24LpVbat[RAIL_PA_CURVES_LP_VALUES] =
+  RAIL_PA_CURVES_2P4_LP;
+
+// This macro is defined when Silicon Labs builds this into the library as WEAK
+// to ensure it can be overriden by customer versions of these functions. It
+// should *not* be defined in a customer build.
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = {
+  .curves = {
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_2P4_HP_SG_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat },
+    },
+    {
+      .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE,
+      .segments = 0U,
+      .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX,
+      .conversion = { .mappingTable = &RAIL_curves24LpVbat[0] },
+    },
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_2P4_HP_SG_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_SUBGIG_MIN,
+      .max = RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataSgVbat },
+    },
+  },
+};
+
+static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpDcdc = {
+  RAIL_PA_CURVES_2P4_HP_DCDC_MAX_POWER,
+  RAIL_PA_CURVES_2P4_HP_DCDC_MIN_POWER,
+  RAIL_PA_CURVES_2P4_HP_DCDC_CURVES
+};
+static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataSgDcdc = {
+  RAIL_PA_CURVES_SG_DCDC_MAX_POWER,
+  RAIL_PA_CURVES_SG_DCDC_MIN_POWER,
+  RAIL_PA_CURVES_SG_DCDC_CURVES
+};
+static const int16_t RAIL_curves24LpDcdc[RAIL_PA_CURVES_LP_VALUES] =
+  RAIL_PA_CURVES_2P4_LP;
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = {
+  .curves = {
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_2P4_HP_SG_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataHpDcdc },
+    },
+    {
+      .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE,
+      .segments = 0U,
+      .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX,
+      .conversion = { .mappingTable = &RAIL_curves24LpDcdc[0] },
+    },
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_2P4_HP_SG_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_SUBGIG_MIN,
+      .max = RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataSgDcdc },
+    },
+  },
+};
+
+#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)   \
+  || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9))
+
+static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = {
+  RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER,
+  RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER,
+  RAIL_PA_CURVES_2P4_HP_VBAT_CURVES,
+};
+static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] =
+  RAIL_PA_CURVES_2P4_LP_VBAT_CURVES;
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = {
+  .curves = {
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat },
+    },
+    {
+      .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE,
+      .segments = 0U,
+      .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX,
+      .conversion = { .mappingTable = &RAIL_curves24Lp[0] },
+    },
+  }
+};
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = {
+  .curves = {
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat },
+    },
+    {
+      .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE,
+      .segments = 0U,
+      .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX,
+      .conversion = { .mappingTable = &RAIL_curves24Lp[0] },
+    },
+  }
+};
+
+#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
+
+RAIL_DECLARE_TX_POWER_VBAT_CURVES_ALT;
+
+// This chip has the same curve for Vbat and DCDC
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT;
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT;
+
+#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
+
+static const int32_t RAIL_curvesOFDM[RAIL_PA_CURVES_OFDM_CURVES_NUM_VALUES] =
+  RAIL_PA_CURVES_OFDM_CURVES;
+
+static const int32_t RAIL_curvesSubgig[RAIL_PA_CURVES_SUBGIG_CURVES_NUM_VALUES] =
+  RAIL_PA_CURVES_SUBGIG_CURVES;
+
+// This chip has the same curve for Vbat and DCDC
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT;
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT;
+
+#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
+
+static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = {
+  RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER,
+  RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER,
+  RAIL_PA_CURVES_2P4_HP_VBAT_CURVES,
+};
+static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataMpVbat = {
+  RAIL_PA_CURVES_2P4_MP_VBAT_MAX_POWER,
+  RAIL_PA_CURVES_2P4_MP_VBAT_MIN_POWER,
+  RAIL_PA_CURVES_2P4_MP_VBAT_CURVES,
+};
+static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataLpVbat = {
+  RAIL_PA_CURVES_2P4_LP_VBAT_MAX_POWER,
+  RAIL_PA_CURVES_2P4_LP_VBAT_MIN_POWER,
+  RAIL_PA_CURVES_2P4_LP,
+};
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = {
+  .curves = {
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat },
+    },
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_2P4_MP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_MP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataMpVbat },
+    },
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataLpVbat },
+    },
+  }
+};
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = {
+  .curves = {
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_HP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_HP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat },
+    },
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_MP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_MP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataMpVbat },
+    },
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_LP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_LP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataLpVbat },
+    },
+  }
+};
+#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
+static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = {
+  RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER,
+  RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER,
+  RAIL_PA_CURVES_2P4_HP_VBAT_CURVES,
+};
+
+#if defined(RAIL_DECLARE_TX_POWER_DCDC_CURVES_ALT)
+static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpDcdc = {
+  RAIL_PA_CURVES_2P4_HP_DCDC_MAX_POWER,
+  RAIL_PA_CURVES_2P4_HP_DCDC_MIN_POWER,
+  RAIL_PA_CURVES_2P4_HP_DCDC_CURVES,
+};
+#endif
+
+static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] =
+  RAIL_PA_CURVES_2P4_LP_VBAT_CURVES;
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = {
+  .curves = {
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX,
+      .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat },
+    },
+    {
+      .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE,
+      .segments = 0U,
+      .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX,
+      .conversion = { .mappingTable = &RAIL_curves24Lp[0] },
+    },
+  }
+};
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = {
+  .curves = {
+    {
+      .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR,
+      .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS,
+      .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX,
+#if defined(RAIL_DECLARE_TX_POWER_DCDC_CURVES_ALT)
+      .conversion = { .powerCurve = &RAIL_piecewiseDataHpDcdc },
+#else
+      .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat },
+#endif
+    },
+    {
+      .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE,
+      .segments = 0U,
+      .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN,
+      .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX,
+      .conversion = { .mappingTable = &RAIL_curves24Lp[0] },
+    },
+  }
+};
+
+#elif !defined(_SILICON_LABS_32B_SERIES_2)
+
+static const int16_t RAIL_curves10dbm[RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_NUM_VALUES] =
+  RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_CURVES;
+
+static const int16_t RAIL_curves0dbm[RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_NUM_VALUES] =
+  RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_CURVES;
+
+// This chip has the same curve for Vbat and DCDC
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT;
+
+#ifdef RAIL_PA_CONVERSIONS_WEAK
+__WEAK
+#endif
+const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT;
+
+#else
+#error "Unsupported platform!"
+#endif
+
+#endif //_SILICON_LABS_MODULE

Libs/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.h

@@ -0,0 +1,129 @@
+/***************************************************************************//**
+ * @file
+ * @brief PA power conversion curves used by Silicon Labs PA power conversion
+ *   functions.
+ * @details This file contains the curves needed convert PA power levels to
+ *   dBm powers.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef PA_CURVES_EFR32_H
+#define PA_CURVES_EFR32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "em_device.h"
+
+#ifdef _SILICON_LABS_32B_SERIES_1
+#include "efr32xg1x/sl_rail_util_pa_curves.h"
+#elif defined (_SILICON_LABS_32B_SERIES_2_CONFIG_1)
+#include "efr32xg21/sl_rail_util_pa_curves.h"
+#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2)
+#include "efr32xg22/sl_rail_util_pa_curves.h"
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
+#if defined(_SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT)
+  #if (_SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM == 20)
+  #include "efr32xg23/sl_rail_util_pa_curves_20dbm.h"
+  #elif (_SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM == 10)
+  #include "efr32xg23/sl_rail_util_pa_curves_10dbm_434M.h"
+  #else
+  #include "efr32xg23/sl_rail_util_pa_curves_14dbm.h"
+  #endif
+#else
+#error "No valid PA available for selected chip."
+#endif
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)
+#if defined(_SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT)
+  #if (_SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM == 20)
+    #if defined(HARDWARE_BOARD_SUPPORTS_RF_BAND_868)
+      #include "efr32xg28/sl_rail_util_pa_curves_20dbm_868M.h"
+    #else
+      #include "efr32xg28/sl_rail_util_pa_curves_20dbm_915M.h"
+    #endif
+  #else
+    #if defined(HARDWARE_BOARD_SUPPORTS_RF_BAND_868)
+      #include "efr32xg28/sl_rail_util_pa_curves_14dbm_868M.h"
+    #else
+      #include "efr32xg28/sl_rail_util_pa_curves_14dbm_915M.h"
+    #endif
+  #endif
+#else
+#error "No valid PA available for selected chip."
+#endif
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)
+  #if defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \
+  && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM > 10)
+  #include "efr32xg24/sl_rail_util_pa_curves_20dbm.h"
+  #else
+  #include "efr32xg24/sl_rail_util_pa_curves_10dbm.h"
+  #endif
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#include "efr32xg25/sl_rail_util_pa_dbm_powersetting_mapping_table.h"
+#include "efr32xg25/sl_rail_util_pa_curves.h"
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 6)
+  #if defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \
+  && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM > 10)
+  #include "efr32xg26/sl_rail_util_pa_curves_20dbm.h"
+  #else
+  #if defined(EFR32MG26B510F3200IL136)
+  #include "efr32xg26/sl_rail_util_pa_curves_BGA.h"
+  #else
+  #include "efr32xg26/sl_rail_util_pa_curves_10dbm.h"
+  #endif
+  #endif
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)
+// EFR32XG27 boards come in two different packaging -- CSP and QFN
+// These packages have different matching circuits which leads
+// to different PA curves.
+// CSP packages have _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM
+// = 4 whereas for QFN package it is 6 or 8dBm, so this parameter
+// is used to differentiate it.
+#if (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM < 6)
+#include "efr32xg27/sl_rail_util_pa_curves_CSP.h"
+#else
+#include "efr32xg27/sl_rail_util_pa_curves_QFN.h"
+#endif
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)
+#include "efr32xg29/sl_rail_util_pa_curves.h"
+#elif defined(_SILICON_LABS_32B_SERIES_3)
+#include "sixg301/sl_rail_util_pa_dbm_powersetting_mapping_table.h"
+#include "sixg301/sl_rail_util_pa_curves.h"
+#else
+#ifdef RAIL_INTERNAL_BUILD
+#include "pa_curves_efr32_internal.h"
+#else
+#error "Unsupported platform!"
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // PA_CURVES_EFR32_H

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ble_config_38M4Hz.h

@@ -0,0 +1,80 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config Header  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __SL_RAIL_BLE_CONFIG_38M4HZ_H__
+#define __SL_RAIL_BLE_CONFIG_38M4HZ_H__
+
+#include <stdint.h>
+#include "rail_types.h"
+
+extern const uint32_t sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_modemConfigBase[];
+
+extern const uint32_t sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_2Mbps_aox_38M4Hz_0_34_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_125kbps_38M4Hz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_500kbps_38M4Hz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_simulscan_38M4Hz_0_37_modemConfig[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_1MBPS_VITERBI_38M4HZ_PHY_BLUETOOTH_1M_AOX_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_1MBPS_VITERBI_38M4HZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_VITERBI_38M4HZ_PHY_BLUETOOTH_2M_38M4HZ_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_VITERBI_38M4HZ_PROFILE_BASE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_AOX_38M4HZ_PHY_BLUETOOTH_2M_38M4HZ_AOX_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_AOX_38M4HZ_PROFILE_BASE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_2Mbps_aox_38M4Hz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_aox_38M4Hz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_125KBPS_38M4HZ_PHY_BLUETOOTH_LR_125K_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_125KBPS_38M4HZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_125kbps_38M4Hz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_125kbps_38M4Hz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_500KBPS_38M4HZ_PHY_BLUETOOTH_LR_500K_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_500KBPS_38M4HZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_500kbps_38M4Hz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_500kbps_38M4Hz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_SIMULSCAN_38M4HZ_PHY_BLUETOOTH_1M_CONCURRENT_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_SIMULSCAN_38M4HZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_simulscan_38M4Hz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_simulscan_38M4Hz_channels[];
+
+#endif // __SL_RAIL_BLE_CONFIG_38M4HZ_H__

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ble_config_39MHz.h

@@ -0,0 +1,80 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config Header  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __SL_RAIL_BLE_CONFIG_39MHZ_H__
+#define __SL_RAIL_BLE_CONFIG_39MHZ_H__
+
+#include <stdint.h>
+#include "rail_types.h"
+
+extern const uint32_t sl_rail_ble_phy_1Mbps_viterbi_39MHz_modemConfigBase[];
+
+extern const uint32_t sl_rail_ble_phy_1Mbps_viterbi_39MHz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_2Mbps_aox_39MHz_0_34_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_125kbps_39MHz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_500kbps_39MHz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_simulscan_39MHz_0_37_modemConfig[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_1MBPS_VITERBI_39MHZ_PHY_BLUETOOTH_1M_AOX_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_1MBPS_VITERBI_39MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_1Mbps_viterbi_39MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_1Mbps_viterbi_39MHz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_VITERBI_39MHZ_PHY_BLUETOOTH_2M_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_VITERBI_39MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_AOX_39MHZ_PHY_BLUETOOTH_2M_AOX_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_AOX_39MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_2Mbps_aox_39MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_aox_39MHz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_125KBPS_39MHZ_PHY_BLUETOOTH_LR_125K_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_125KBPS_39MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_125kbps_39MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_125kbps_39MHz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_500KBPS_39MHZ_PHY_BLUETOOTH_LR_500K_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_500KBPS_39MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_500kbps_39MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_500kbps_39MHz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_SIMULSCAN_39MHZ_PHY_BLUETOOTH_1M_CONCURRENT_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_SIMULSCAN_39MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_simulscan_39MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_simulscan_39MHz_channels[];
+
+#endif // __SL_RAIL_BLE_CONFIG_39MHZ_H__

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ble_config_40MHz.h

@@ -0,0 +1,93 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config Header  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __SL_RAIL_BLE_CONFIG_40MHZ_H__
+#define __SL_RAIL_BLE_CONFIG_40MHZ_H__
+
+#include <stdint.h>
+#include "rail_types.h"
+
+extern const uint32_t sl_rail_ble_phy_1Mbps_viterbi_40MHz_modemConfigBase[];
+extern const uint32_t sl_rail_ble_phy_1Mbps_viterbi_cs_40MHz_modemConfigBase[];
+
+extern const uint32_t sl_rail_ble_phy_1Mbps_viterbi_40MHz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_2Mbps_viterbi_40MHz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_2Mbps_aox_40MHz_0_34_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_125kbps_40MHz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_500kbps_40MHz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_simulscan_40MHz_0_37_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_1Mbps_viterbi_cs_0_78_40MHz_modemConfig[];
+extern const uint32_t sl_rail_ble_phy_2Mbps_viterbi_cs_0_78_40MHz_modemConfig[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_1MBPS_VITERBI_40MHZ_PHY_BLUETOOTH_1M_AOX_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_1MBPS_VITERBI_40MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_1Mbps_viterbi_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_1Mbps_viterbi_40MHz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_VITERBI_40MHZ_PHY_BLUETOOTH_2M_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_VITERBI_40MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_2Mbps_viterbi_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_40MHz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_AOX_40MHZ_PHY_BLUETOOTH_2M_AOX_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_AOX_40MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_2Mbps_aox_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_aox_40MHz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_125KBPS_40MHZ_PHY_BLUETOOTH_LR_125K_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_125KBPS_40MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_125kbps_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_125kbps_40MHz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_500KBPS_40MHZ_PHY_BLUETOOTH_LR_500K_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_500KBPS_40MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_500kbps_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_500kbps_40MHz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_1MBPS_VITERBI_CS_40MHZ_PHY_BLUETOOTH_1M_HADM_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_1MBPS_VITERBI_CS_40MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_1Mbps_viterbi_cs_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_1Mbps_viterbi_cs_40MHz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_VITERBI_CS_40MHZ_PHY_BLUETOOTH_2M_HADM_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_2MBPS_VITERBI_CS_40MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_2Mbps_viterbi_cs_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_cs_40MHz_channels[];
+
+#define RAIL0_SL_RAIL_BLE_PHY_SIMULSCAN_40MHZ_PHY_BLUETOOTH_1M_CONCURRENT_PROD
+#define RAIL0_SL_RAIL_BLE_PHY_SIMULSCAN_40MHZ_PROFILE_BLE
+extern const RAIL_ChannelConfig_t sl_rail_ble_phy_simulscan_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_simulscan_40MHz_channels[];
+
+#endif // __SL_RAIL_BLE_CONFIG_40MHZ_H__

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ieee802154_config_38M4Hz.c

@@ -0,0 +1,880 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#include "em_device.h"
+#include "sl_rail_ieee802154_config_38M4Hz.h"
+
+static const uint8_t irCalConfig[] = {
+  25, 63, 1, 6, 4, 16, 1, 0, 0, 1, 1, 6, 0, 16, 39, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static const int32_t timingConfig_0[] = {
+  6125, 6125, 500, 0
+};
+
+static const int32_t timingConfig_1[] = {
+  6625, 6625, 500, 0
+};
+
+static const uint8_t hfxoRetimingConfigEntries[] = {
+  2, 0, 0, 0, 0x00, 0xf0, 0x49, 0x02, 6, 20, 0, 0, 0x00, 0xe0, 0x93, 0x04, 5, 56, 0, 0, 0xa0, 0x08, 0, 0, 0, 0, 0x58, 0x09, 1, 4, 7, 6, 0x10, 0x0a, 1, 4, 7, 7, 0xc8, 0x0a, 0, 4, 8, 7, 0x80, 0x0b, 0, 4, 8, 8, 0x38, 0x0c, 0, 4, 9, 8, 0x61, 0x08, 0, 0, 0, 0, 0x68, 0x08, 0, 0, 0, 0, 0xc7, 0x09, 1, 4, 4, 3, 0x2c, 0x0b, 1, 4, 4, 4, 0x92, 0x0c, 1, 4, 5, 4
+};
+
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+static const uint8_t stackInfo_0[2] = { 0x05, 0x03 };
+static const uint8_t stackInfo_1[2] = { 0x05, 0x00 };
+static const uint8_t stackInfo_2[2] = { 0x05, 0x04 };
+static const uint8_t stackInfo_3[2] = { 0x05, 0x06 };
+static const uint8_t stackInfo_4[2] = { 0x05, 0x05 };
+#endif // RADIO_CONFIG_ENABLE_STACK_INFO
+
+static RAIL_ChannelConfigEntryAttr_t channelConfigEntryAttr = {
+#if RAIL_SUPPORTS_OFDM_PA
+  {
+#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+    { 0xFFFFFFFFUL, 0xFFFFFFFFUL, },
+#else
+    { 0xFFFFFFFFUL },
+#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+    { 0xFFFFFFFFUL, 0xFFFFFFFFUL }
+  }
+#else // RAIL_SUPPORTS_OFDM_PA
+#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+  { 0xFFFFFFFFUL, 0xFFFFFFFFUL, },
+#else
+  { 0xFFFFFFFFUL },
+#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+#endif // RAIL_SUPPORTS_OFDM_PA
+};
+
+static const uint32_t phyInfo_0[] = {
+  18UL,
+  0x00444444UL, // 68.26666666666665
+  (uint32_t) NULL,
+  (uint32_t) irCalConfig,
+  (uint32_t) timingConfig_0,
+  0x00000000UL,
+  0UL,
+  60000000UL,
+  2000000UL,
+  0x00F62004UL,
+  0x02104911UL,
+  (uint32_t) NULL,
+  (uint32_t) hfxoRetimingConfigEntries,
+  (uint32_t) NULL,
+  0UL,
+  0UL,
+  2000035UL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+};
+
+static const uint32_t phyInfo_1[] = {
+  18UL,
+  0x00444444UL, // 68.26666666666665
+  (uint32_t) NULL,
+  (uint32_t) irCalConfig,
+  (uint32_t) timingConfig_1,
+  0x00000A00UL,
+  0UL,
+  60000000UL,
+  2000000UL,
+  0x00F82004UL,
+  0x02104911UL,
+  (uint32_t) NULL,
+  (uint32_t) hfxoRetimingConfigEntries,
+  (uint32_t) NULL,
+  0UL,
+  0UL,
+  2000035UL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+};
+
+static const uint32_t phyInfo_2[] = {
+  18UL,
+  0x00444444UL, // 68.26666666666665
+  (uint32_t) NULL,
+  (uint32_t) irCalConfig,
+  (uint32_t) timingConfig_1,
+  0x00000B00UL,
+  0UL,
+  60000000UL,
+  2000000UL,
+  0x00F82004UL,
+  0x02104911UL,
+  (uint32_t) NULL,
+  (uint32_t) hfxoRetimingConfigEntries,
+  (uint32_t) NULL,
+  0UL,
+  0UL,
+  2000035UL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_38M4Hz_modemConfigBase[] = {
+  0x0002400CUL, 0x00148001UL,
+  /*    4010 */ 0x0000407FUL,
+  0x00024020UL, 0x00000000UL,
+  /*    4024 */ 0x00000000UL,
+  0x00074030UL, 0x00000000UL,
+  /*    4034 */ 0x00000000UL,
+  /*    4038 */ 0x00000000UL,
+  /*    403C */ 0x00000000UL,
+  /*    4040 */ 0x00000000UL,
+  /*    4044 */ 0x00004000UL,
+  /*    4048 */ 0x030007A0UL,
+  0x00014050UL, 0x00000000UL,
+  0x0002405CUL, 0x00000000UL,
+  /*    4060 */ 0x00000000UL,
+  0x000140A8UL, 0x00000007UL,
+  0x000440BCUL, 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  0x00044108UL, 0x00004000UL,
+  /*    410C */ 0x00004CFFUL,
+  /*    4110 */ 0x00004100UL,
+  /*    4114 */ 0x00004DFFUL,
+  0x0007C028UL, 0x03B380ECUL,
+  /*    C02C */ 0x51407543UL,
+  /*    C030 */ 0xF8000FA0UL,
+  /*    C034 */ 0x00004000UL,
+  /*    C038 */ 0x0007AAA8UL,
+  /*    C03C */ 0x00000000UL,
+  /*    C040 */ 0x00000000UL,
+  0x0005C054UL, 0x00303151UL,
+  /*    C058 */ 0xE60D000EUL,
+  /*    C05C */ 0x0000002AUL,
+  /*    C060 */ 0x0D0C0B08UL,
+  /*    C064 */ 0x0000000DUL,
+  0x0009C070UL, 0x000010BAUL,
+  /*    C074 */ 0x00200400UL,
+  /*    C078 */ 0x00801804UL,
+  /*    C07C */ 0x01203C0BUL,
+  /*    C080 */ 0x02107C18UL,
+  /*    C084 */ 0x06E0FC2FUL,
+  /*    C088 */ 0x0000007FUL,
+  /*    C08C */ 0x00000000UL,
+  /*    C090 */ 0x00000000UL,
+  0x0005C0A8UL, 0x15724BBDUL,
+  /*    C0AC */ 0x0518A311UL,
+  /*    C0B0 */ 0x76543210UL,
+  /*    C0B4 */ 0x00000A98UL,
+  /*    C0B8 */ 0x00000000UL,
+  0x0001C0CCUL, 0x00000001UL,
+  0x0002C0D4UL, 0x000A0001UL,
+  /*    C0D8 */ 0x00280001UL,
+  0x01010008UL, 0x00000704UL,
+  0x01010018UL, 0x00000000UL,
+  0x01010020UL, 0x00008408UL,
+  0x01034040UL, 0x00000000UL,
+  /*    4044 */ 0x00000000UL,
+  /*    4048 */ 0x00000010UL,
+  0x01024058UL, 0x00000000UL,
+  /*    405C */ 0x03000000UL,
+  0x01064068UL, 0x00FF0264UL,
+  /*    406C */ 0x00000841UL,
+  /*    4070 */ 0x00000008UL,
+  /*    4074 */ 0x000807B0UL,
+  /*    4078 */ 0x000000A7UL,
+  /*    407C */ 0x00000000UL,
+  0x01024084UL, 0x744AC39BUL,
+  /*    4088 */ 0x000F03F0UL,
+  0x01104094UL, 0x30100101UL,
+  /*    4098 */ 0x7F7F7050UL,
+  /*    409C */ 0x00000000UL,
+  /*    40A0 */ 0x00000000UL,
+  /*    40A4 */ 0x00000000UL,
+  /*    40A8 */ 0x00000000UL,
+  /*    40AC */ 0x00000000UL,
+  /*    40B0 */ 0x00000000UL,
+  /*    40B4 */ 0x00000000UL,
+  /*    40B8 */ 0x00000000UL,
+  /*    40BC */ 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  /*    40CC */ 0x00000000UL,
+  /*    40D0 */ 0x00000000UL,
+  0x010140E0UL, 0x00000200UL,
+  0x01024110UL, 0x00051E33UL,
+  /*    4114 */ 0x00000000UL,
+  0x0101411CUL, 0x8A81B000UL,
+  0x01054124UL, 0x078304FFUL,
+  /*    4128 */ 0x3AC81388UL,
+  /*    412C */ 0x0C6606FFUL,
+  /*    4130 */ 0x078304FFUL,
+  /*    4134 */ 0x03FF1388UL,
+  0x0106413CUL, 0x0051BFBBUL,
+  /*    4140 */ 0x00000000UL,
+  /*    4144 */ 0x123556B7UL,
+  /*    4148 */ 0x50000000UL,
+  /*    414C */ 0x00003B80UL,
+  /*    4150 */ 0x00000000UL,
+  0x01014158UL, 0x00000000UL,
+  0x01024164UL, 0x0000010CUL,
+  /*    4168 */ 0x00FA53E8UL,
+  0x010141A4UL, 0x00000000UL,
+  0x010241B0UL, 0x00000000UL,
+  /*    41B4 */ 0x00200000UL,
+  0x010341BCUL, 0x00000000UL,
+  /*    41C0 */ 0x003C0000UL,
+  /*    41C4 */ 0x0006AAAAUL,
+  0x010341D0UL, 0x00000000UL,
+  /*    41D4 */ 0x000000D0UL,
+  /*    41D8 */ 0x00020000UL,
+  0x011641E0UL, 0x00000000UL,
+  /*    41E4 */ 0x0BFFE7E6UL,
+  /*    41E8 */ 0x000AA1CDUL,
+  /*    41EC */ 0x006A06BDUL,
+  /*    41F0 */ 0x004DB05EUL,
+  /*    41F4 */ 0x0E42027DUL,
+  /*    41F8 */ 0x0222B6A5UL,
+  /*    41FC */ 0x34B225FFUL,
+  /*    4200 */ 0x0BFFE7E6UL,
+  /*    4204 */ 0x000AA1CDUL,
+  /*    4208 */ 0x006A06BDUL,
+  /*    420C */ 0x004DB05EUL,
+  /*    4210 */ 0x0E42027DUL,
+  /*    4214 */ 0x0222B6A5UL,
+  /*    4218 */ 0x34B225FFUL,
+  /*    421C */ 0x00000000UL,
+  /*    4220 */ 0x00000000UL,
+  /*    4224 */ 0x0000002CUL,
+  /*    4228 */ 0x3675EE07UL,
+  /*    422C */ 0x40001860UL,
+  /*    4230 */ 0x00000000UL,
+  /*    4234 */ 0x00000000UL,
+  0x01034244UL, 0x00000014UL,
+  /*    4248 */ 0x00000000UL,
+  /*    424C */ 0x04000008UL,
+  0x01014268UL, 0x00000000UL,
+  0x01024298UL, 0x0200003FUL,
+  /*    429C */ 0x0000FFFFUL,
+  0x0104433CUL, 0x1F1F1F1FUL,
+  /*    4340 */ 0x1B1F1F1FUL,
+  /*    4344 */ 0x11131518UL,
+  /*    4348 */ 0x0C0D0E10UL,
+  0x01024350UL, 0x00000000UL,
+  /*    4354 */ 0x00000000UL,
+  0x01018010UL, 0x00000003UL,
+  0x01028038UL, 0x00104911UL,
+  /*    803C */ 0x00000001UL,
+  0x0103809CUL, 0x000240EBUL,
+  /*    80A0 */ 0x00037870UL,
+  /*    80A4 */ 0x0000C0D5UL,
+  0x110180A8UL, 0x000001F0UL,
+  0x310180A8UL, 0x01CB4205UL,
+  0x110180ACUL, 0x000001F0UL,
+  0x310180ACUL, 0x008D2205UL,
+  0x010280B0UL, 0x02000300UL,
+  /*    80B4 */ 0x01000037UL,
+  0x0201009CUL, 0x04000C00UL,
+  0x020300D8UL, 0xAA400005UL,
+  /*    00DC */ 0x00000188UL,
+  /*    00E0 */ 0x000000C0UL,
+  0x120100ECUL, 0x00000FE0UL,
+  0x320100ECUL, 0x1151200CUL,
+  0x020100F0UL, 0x0000012BUL,
+  0x12010110UL, 0x000FFF00UL,
+  0x32010110UL, 0x31000002UL,
+  0x12010150UL, 0x0001C000UL,
+  0x32010150UL, 0x00A200C1UL,
+  0x02010174UL, 0x0C1B8169UL,
+  0x12010178UL, 0x001C0000UL,
+  0x32010178UL, 0xCFE00410UL,
+  0x12010180UL, 0x00000779UL,
+  0x32010180UL, 0x00000002UL,
+  0x02020184UL, 0x00000000UL,
+  /*    0188 */ 0x00000050UL,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_38M4Hz_modemConfigBase[] = {
+  0x0002400CUL, 0x00148001UL,
+  /*    4010 */ 0x0000407FUL,
+  0x00024020UL, 0x00000000UL,
+  /*    4024 */ 0x00000000UL,
+  0x00074030UL, 0x00000000UL,
+  /*    4034 */ 0x00000000UL,
+  /*    4038 */ 0x00000000UL,
+  /*    403C */ 0x00000000UL,
+  /*    4040 */ 0x00000000UL,
+  /*    4044 */ 0x00004000UL,
+  /*    4048 */ 0x030007A0UL,
+  0x00014050UL, 0x00000000UL,
+  0x0002405CUL, 0x00000000UL,
+  /*    4060 */ 0x00000000UL,
+  0x000140A8UL, 0x00000007UL,
+  0x000440BCUL, 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  0x00044108UL, 0x00004000UL,
+  /*    410C */ 0x00004CFFUL,
+  /*    4110 */ 0x00004100UL,
+  /*    4114 */ 0x00004DFFUL,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x012801FEUL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00001400UL,
+  0x0008C028UL, 0x03B380ECUL,
+  /*    C02C */ 0x51407543UL,
+  /*    C030 */ 0xF8000FA0UL,
+  /*    C034 */ 0x00004000UL,
+  /*    C038 */ 0x0007AAA8UL,
+  /*    C03C */ 0x00000000UL,
+  /*    C040 */ 0x00000000UL,
+  /*    C044 */ 0x00000000UL,
+  0x0010C054UL, 0x00303151UL,
+  /*    C058 */ 0xE6070007UL,
+  /*    C05C */ 0x00000015UL,
+  /*    C060 */ 0x07060604UL,
+  /*    C064 */ 0x00000007UL,
+  /*    C068 */ 0x0002C688UL,
+  /*    C06C */ 0x00000500UL,
+  /*    C070 */ 0x000010BAUL,
+  /*    C074 */ 0x00200400UL,
+  /*    C078 */ 0x00801804UL,
+  /*    C07C */ 0x01203C0BUL,
+  /*    C080 */ 0x02107C18UL,
+  /*    C084 */ 0x06E0FC2FUL,
+  /*    C088 */ 0x0000007FUL,
+  /*    C08C */ 0x00000000UL,
+  /*    C090 */ 0x00000000UL,
+  0x0005C0A8UL, 0x15724BBDUL,
+  /*    C0AC */ 0x0518A311UL,
+  /*    C0B0 */ 0x76543210UL,
+  /*    C0B4 */ 0x00000A98UL,
+  /*    C0B8 */ 0x00000000UL,
+  0x0004C0CCUL, 0x00000001UL,
+  /*    C0D0 */ 0x000000A1UL,
+  /*    C0D4 */ 0x000A0001UL,
+  /*    C0D8 */ 0x00280001UL,
+  0x01010008UL, 0x00000704UL,
+  0x01010018UL, 0x00000000UL,
+  0x01010020UL, 0x00008408UL,
+  0x01254040UL, 0x00000000UL,
+  /*    4044 */ 0x00000000UL,
+  /*    4048 */ 0x00000010UL,
+  /*    404C */ 0x0413FB20UL,
+  /*    4050 */ 0x0042C007UL,
+  /*    4054 */ 0x00000000UL,
+  /*    4058 */ 0x00000000UL,
+  /*    405C */ 0x03000000UL,
+  /*    4060 */ 0x20000000UL,
+  /*    4064 */ 0x0002B820UL,
+  /*    4068 */ 0x00FF0264UL,
+  /*    406C */ 0x00000841UL,
+  /*    4070 */ 0x00000008UL,
+  /*    4074 */ 0x000807B0UL,
+  /*    4078 */ 0x000000A7UL,
+  /*    407C */ 0x00000000UL,
+  /*    4080 */ 0x08A0025AUL,
+  /*    4084 */ 0x744AC39BUL,
+  /*    4088 */ 0x000F03F0UL,
+  /*    408C */ 0x60000000UL,
+  /*    4090 */ 0x00000000UL,
+  /*    4094 */ 0x30100101UL,
+  /*    4098 */ 0x7F7F7050UL,
+  /*    409C */ 0x00000000UL,
+  /*    40A0 */ 0x00000000UL,
+  /*    40A4 */ 0x00000000UL,
+  /*    40A8 */ 0x00000000UL,
+  /*    40AC */ 0x00000000UL,
+  /*    40B0 */ 0x00000000UL,
+  /*    40B4 */ 0x00000000UL,
+  /*    40B8 */ 0x00000000UL,
+  /*    40BC */ 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  /*    40CC */ 0x00000000UL,
+  /*    40D0 */ 0x00000000UL,
+  0x010140E0UL, 0x00000200UL,
+  0x01024110UL, 0x00051E73UL,
+  /*    4114 */ 0x00000000UL,
+  0x010E411CUL, 0x8A81B000UL,
+  /*    4120 */ 0x00000111UL,
+  /*    4124 */ 0x078304FFUL,
+  /*    4128 */ 0x3AC81388UL,
+  /*    412C */ 0x0C6606FFUL,
+  /*    4130 */ 0x078304FFUL,
+  /*    4134 */ 0x03FF1388UL,
+  /*    4138 */ 0xF00A20BCUL,
+  /*    413C */ 0x0051BFBBUL,
+  /*    4140 */ 0x00000000UL,
+  /*    4144 */ 0x123556B7UL,
+  /*    4148 */ 0x50000000UL,
+  /*    414C */ 0x00003B80UL,
+  /*    4150 */ 0x00000000UL,
+  0x01024158UL, 0x00000000UL,
+  /*    415C */ 0x00001003UL,
+  0x010D4164UL, 0x0000010CUL,
+  /*    4168 */ 0x00FA53E8UL,
+  /*    416C */ 0x40000000UL,
+  /*    4170 */ 0x00000000UL,
+  /*    4174 */ 0x00000000UL,
+  /*    4178 */ 0x00000000UL,
+  /*    417C */ 0x00000000UL,
+  /*    4180 */ 0x00000000UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x00000000UL,
+  /*    418C */ 0x00000000UL,
+  /*    4190 */ 0x00000000UL,
+  /*    4194 */ 0x00000000UL,
+  0x010241A4UL, 0x00000000UL,
+  /*    41A8 */ 0x00000000UL,
+  0x010241B0UL, 0x00000000UL,
+  /*    41B4 */ 0x00200000UL,
+  0x010341BCUL, 0x00000000UL,
+  /*    41C0 */ 0x003C0000UL,
+  /*    41C4 */ 0x0006AAAAUL,
+  0x010341D0UL, 0x00000000UL,
+  /*    41D4 */ 0x000000D0UL,
+  /*    41D8 */ 0x00020000UL,
+  0x011641E0UL, 0x00000000UL,
+  /*    41E4 */ 0x0BFFE7E6UL,
+  /*    41E8 */ 0x000AA1CDUL,
+  /*    41EC */ 0x006A06BDUL,
+  /*    41F0 */ 0x004DB05EUL,
+  /*    41F4 */ 0x0E42027DUL,
+  /*    41F8 */ 0x0222B6A5UL,
+  /*    41FC */ 0x34B225FFUL,
+  /*    4200 */ 0x0BFFE7E6UL,
+  /*    4204 */ 0x000AA1CDUL,
+  /*    4208 */ 0x006A06BDUL,
+  /*    420C */ 0x004DB05EUL,
+  /*    4210 */ 0x0E42027DUL,
+  /*    4214 */ 0x0222B6A5UL,
+  /*    4218 */ 0x34B225FFUL,
+  /*    421C */ 0x00000000UL,
+  /*    4220 */ 0x00000000UL,
+  /*    4224 */ 0x0000002CUL,
+  /*    4228 */ 0x3675EE07UL,
+  /*    422C */ 0x00001860UL,
+  /*    4230 */ 0x00000000UL,
+  /*    4234 */ 0x00000000UL,
+  0x0101423CUL, 0x00000112UL,
+  0x01034244UL, 0x00000014UL,
+  /*    4248 */ 0x00000000UL,
+  /*    424C */ 0x04000008UL,
+  0x01014268UL, 0x00000000UL,
+  0x01024280UL, 0x40090001UL,
+  /*    4284 */ 0x00100801UL,
+  0x01054298UL, 0x0200003FUL,
+  /*    429C */ 0x0000FFFFUL,
+  /*    42A0 */ 0x03E80000UL,
+  /*    42A4 */ 0x00000200UL,
+  /*    42A8 */ 0x00100000UL,
+  0x010142B4UL, 0x00C00000UL,
+  0x010A4330UL, 0x02400040UL,
+  /*    4334 */ 0x04AC0140UL,
+  /*    4338 */ 0x0100B050UL,
+  /*    433C */ 0x1F1F1F1FUL,
+  /*    4340 */ 0x1B1F1F1FUL,
+  /*    4344 */ 0x11131518UL,
+  /*    4348 */ 0x0C0D0E10UL,
+  /*    434C */ 0x2D0F285DUL,
+  /*    4350 */ 0x00000000UL,
+  /*    4354 */ 0x00000000UL,
+  0x01018010UL, 0x00000003UL,
+  0x01028038UL, 0x00104911UL,
+  /*    803C */ 0x00000001UL,
+  0x0103809CUL, 0x000240EBUL,
+  /*    80A0 */ 0x0000C0D5UL,
+  /*    80A4 */ 0x0000C0D5UL,
+  0x110180A8UL, 0x000001F0UL,
+  0x310180A8UL, 0x008D2205UL,
+  0x110180ACUL, 0x000001F0UL,
+  0x310180ACUL, 0x008D2205UL,
+  0x010280B0UL, 0x0100003FUL,
+  /*    80B4 */ 0x01000037UL,
+  0x0201009CUL, 0x04000C00UL,
+  0x020300D8UL, 0xAA400005UL,
+  /*    00DC */ 0x00000188UL,
+  /*    00E0 */ 0x000000C0UL,
+  0x120100ECUL, 0x00000FE0UL,
+  0x320100ECUL, 0x1151200CUL,
+  0x020100F0UL, 0x0000012BUL,
+  0x12010110UL, 0x000FFF00UL,
+  0x32010110UL, 0x31000002UL,
+  0x12010150UL, 0x0001C000UL,
+  0x32010150UL, 0x00A200C1UL,
+  0x02010174UL, 0x0C1FF169UL,
+  0x12010178UL, 0x001C0000UL,
+  0x32010178UL, 0x1FE00410UL,
+  0x12010180UL, 0x00000779UL,
+  0x02020184UL, 0x00000000UL,
+  /*    0188 */ 0x00000048UL,
+  0x03014FFCUL, (uint32_t) &phyInfo_1,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_38M4Hz_modemConfig[] = {
+  0x03014FFCUL, (uint32_t) &phyInfo_0,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x01280214UL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00004300UL,
+  0x0001C044UL, 0x0000022EUL,
+  0x0002C068UL, 0x0002B6D1UL,
+  /*    C06C */ 0x00000740UL,
+  0x0001C0D0UL, 0x00000000UL,
+  0x0103404CUL, 0x0413F920UL,
+  /*    4050 */ 0x00620007UL,
+  /*    4054 */ 0x00007038UL,
+  0x01024060UL, 0x0F016800UL,
+  /*    4064 */ 0x4024B840UL,
+  0x01014080UL, 0x00006323UL,
+  0x0102408CUL, 0x60008000UL,
+  /*    4090 */ 0x00000ABEUL,
+  0x01014120UL, 0x00000B59UL,
+  0x01014138UL, 0xF00A2090UL,
+  0x0101415CUL, 0x00001E00UL,
+  0x010B416CUL, 0xC00C1400UL,
+  /*    4170 */ 0x28211A14UL,
+  /*    4174 */ 0x423B342EUL,
+  /*    4178 */ 0x55435049UL,
+  /*    417C */ 0x0CBA9876UL,
+  /*    4180 */ 0x00007323UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x64282117UL,
+  /*    418C */ 0x001A1714UL,
+  /*    4190 */ 0x7DC80420UL,
+  /*    4194 */ 0x093A20A1UL,
+  0x010141A8UL, 0x00000029UL,
+  0x0101423CUL, 0x00000000UL,
+  0x01024280UL, 0x00000000UL,
+  /*    4284 */ 0x00000081UL,
+  0x010342A0UL, 0x0000FFFFUL,
+  /*    42A4 */ 0x000003FFUL,
+  /*    42A8 */ 0x0000FFFFUL,
+  0x010142B4UL, 0x00000000UL,
+  0x01034330UL, 0x01200040UL,
+  /*    4334 */ 0x000000A0UL,
+  /*    4338 */ 0x01005008UL,
+  0x0101434CUL, 0x2F87C145UL,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_antdiv_38M4Hz_modemConfig[] = {
+  0x03014FFCUL, (uint32_t) &phyInfo_2,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x012801FEUL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00001400UL,
+  0x0001C044UL, 0x00000000UL,
+  0x0002C068UL, 0x0002C688UL,
+  /*    C06C */ 0x00000500UL,
+  0x0001C0D0UL, 0x000000A1UL,
+  0x0103404CUL, 0x0413FB20UL,
+  /*    4050 */ 0x0042C007UL,
+  /*    4054 */ 0x00000000UL,
+  0x01024060UL, 0x28000000UL,
+  /*    4064 */ 0x00028000UL,
+  0x01014080UL, 0x08A0015AUL,
+  0x0102408CUL, 0x60000000UL,
+  /*    4090 */ 0x00000000UL,
+  0x01014120UL, 0x00000000UL,
+  0x01014138UL, 0xF00A20BCUL,
+  0x0101415CUL, 0x00001003UL,
+  0x010B416CUL, 0x40000000UL,
+  /*    4170 */ 0x00000000UL,
+  /*    4174 */ 0x00000000UL,
+  /*    4178 */ 0x00000000UL,
+  /*    417C */ 0x00000000UL,
+  /*    4180 */ 0x00000000UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x00000000UL,
+  /*    418C */ 0x00000000UL,
+  /*    4190 */ 0x00000000UL,
+  /*    4194 */ 0x00000000UL,
+  0x010141A8UL, 0x00000000UL,
+  0x0101423CUL, 0x00000112UL,
+  0x01024280UL, 0x40090001UL,
+  /*    4284 */ 0x00100801UL,
+  0x010342A0UL, 0x03E80000UL,
+  /*    42A4 */ 0x00000200UL,
+  /*    42A8 */ 0x00100000UL,
+  0x010142B4UL, 0x00C00000UL,
+  0x01034330UL, 0x02400041UL,
+  /*    4334 */ 0x04AC0140UL,
+  /*    4338 */ 0x0100B050UL,
+  0x0101434CUL, 0x2D0F285DUL,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_38M4Hz_modemConfig[] = {
+  0x03014FFCUL, (uint32_t) &phyInfo_2,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x012801FEUL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00001400UL,
+  0x0001C044UL, 0x00000000UL,
+  0x0002C068UL, 0x0002C688UL,
+  /*    C06C */ 0x00000500UL,
+  0x0001C0D0UL, 0x000000A1UL,
+  0x0103404CUL, 0x0413FB20UL,
+  /*    4050 */ 0x0042C007UL,
+  /*    4054 */ 0x00000000UL,
+  0x01024060UL, 0x28000000UL,
+  /*    4064 */ 0x00028000UL,
+  0x01014080UL, 0x08A0015AUL,
+  0x0102408CUL, 0x60000000UL,
+  /*    4090 */ 0x00000000UL,
+  0x01014120UL, 0x00000000UL,
+  0x01014138UL, 0xF00A20BCUL,
+  0x0101415CUL, 0x00001003UL,
+  0x010B416CUL, 0x40000000UL,
+  /*    4170 */ 0x00000000UL,
+  /*    4174 */ 0x00000000UL,
+  /*    4178 */ 0x00000000UL,
+  /*    417C */ 0x00000000UL,
+  /*    4180 */ 0x00000000UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x00000000UL,
+  /*    418C */ 0x00000000UL,
+  /*    4190 */ 0x00000000UL,
+  /*    4194 */ 0x00000000UL,
+  0x010141A8UL, 0x00000000UL,
+  0x0101423CUL, 0x00000112UL,
+  0x01024280UL, 0x40090001UL,
+  /*    4284 */ 0x00100801UL,
+  0x010342A0UL, 0x03E80000UL,
+  /*    42A4 */ 0x00000200UL,
+  /*    42A8 */ 0x00100000UL,
+  0x010142B4UL, 0x00C00000UL,
+  0x01034330UL, 0x02400041UL,
+  /*    4334 */ 0x05B40140UL,
+  /*    4338 */ 0x0100B050UL,
+  0x0101434CUL, 0x2D0F285DUL,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_fem_38M4Hz_modemConfig[] = {
+  0x03014FFCUL, (uint32_t) &phyInfo_0,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x01280214UL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00004300UL,
+  0x0001C044UL, 0x0000022EUL,
+  0x0002C068UL, 0x0002B6D1UL,
+  /*    C06C */ 0x00000740UL,
+  0x0001C0D0UL, 0x00000000UL,
+  0x0103404CUL, 0x0413F920UL,
+  /*    4050 */ 0x00620007UL,
+  /*    4054 */ 0x00007038UL,
+  0x01024060UL, 0x0F016800UL,
+  /*    4064 */ 0x4024B840UL,
+  0x01014080UL, 0x00006323UL,
+  0x0102408CUL, 0x60008000UL,
+  /*    4090 */ 0x00000ABEUL,
+  0x01014120UL, 0x00000B59UL,
+  0x01014138UL, 0xF00A2090UL,
+  0x0101415CUL, 0x00001E00UL,
+  0x010B416CUL, 0xC00C1400UL,
+  /*    4170 */ 0x2E27201AUL,
+  /*    4174 */ 0x48413A34UL,
+  /*    4178 */ 0x6654564FUL,
+  /*    417C */ 0x0DCBA987UL,
+  /*    4180 */ 0x00007323UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x6A2E2717UL,
+  /*    418C */ 0x001A1714UL,
+  /*    4190 */ 0x7DC80420UL,
+  /*    4194 */ 0x093A20A1UL,
+  0x010141A8UL, 0x00000029UL,
+  0x0101423CUL, 0x00000000UL,
+  0x01024280UL, 0x00000000UL,
+  /*    4284 */ 0x00000081UL,
+  0x010342A0UL, 0x0000FFFFUL,
+  /*    42A4 */ 0x000003FFUL,
+  /*    42A8 */ 0x0000FFFFUL,
+  0x010142B4UL, 0x00000000UL,
+  0x01034330UL, 0x01200040UL,
+  /*    4334 */ 0x000000A0UL,
+  /*    4338 */ 0x01005008UL,
+  0x0101434CUL, 0x2F87C145UL,
+  0xFFFFFFFFUL,
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_38M4Hz_channels[] = {
+  {
+    .phyConfigDeltaAdd = sl_rail_ieee802154_phy_2G4Hz_38M4Hz_modemConfig,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_0,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_38M4Hz_channels[] = {
+  {
+    .phyConfigDeltaAdd = NULL,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_1,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_antdiv_38M4Hz_channels[] = {
+  {
+    .phyConfigDeltaAdd = sl_rail_ieee802154_phy_2G4Hz_antdiv_38M4Hz_modemConfig,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_2,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_38M4Hz_channels[] = {
+  {
+    .phyConfigDeltaAdd = sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_38M4Hz_modemConfig,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_3,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_fem_38M4Hz_channels[] = {
+  {
+    .phyConfigDeltaAdd = sl_rail_ieee802154_phy_2G4Hz_fem_38M4Hz_modemConfig,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_4,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_38M4Hz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_38M4Hz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_38M4Hz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 38400000UL,
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_38M4Hz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_fast_switch_38M4Hz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_fast_switch_38M4Hz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 38400000UL,
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_antdiv_38M4Hz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_38M4Hz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_antdiv_38M4Hz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 38400000UL,
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_38M4Hz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_38M4Hz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_38M4Hz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 38400000UL,
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_fem_38M4Hz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_38M4Hz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_fem_38M4Hz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 38400000UL,
+};

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ieee802154_config_38M4Hz.h

@@ -0,0 +1,74 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config Header  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __SL_RAIL_IEEE802154_CONFIG_38M4HZ_H__
+#define __SL_RAIL_IEEE802154_CONFIG_38M4HZ_H__
+
+#include <stdint.h>
+#include "rail_types.h"
+
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_38M4Hz_modemConfigBase[];
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_38M4Hz_modemConfigBase[];
+
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_38M4Hz_modemConfig[];
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_antdiv_38M4Hz_modemConfig[];
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_38M4Hz_modemConfig[];
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_fem_38M4Hz_modemConfig[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_38M4HZ_PHY_IEEE802154_2P4GHZ_PROD
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_38M4HZ_PROFILE_IEEE802154OQPSK
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_38M4Hz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_38M4Hz_channels[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_FAST_SWITCH_38M4HZ_PHY_IEEE802154_2P4GHZ_ANTDIV_FASTSWITCH
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_FAST_SWITCH_38M4HZ_PROFILE_BASE
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_38M4Hz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_38M4Hz_channels[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_ANTDIV_38M4HZ_PHY_IEEE802154_2P4GHZ_DIVERSITY_PROD
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_ANTDIV_38M4HZ_PROFILE_IEEE802154OQPSK
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_antdiv_38M4Hz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_antdiv_38M4Hz_channels[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_ANTDIV_FEM_38M4HZ_PHY_IEEE802154_2P4GHZ_DIVERSITY_FEM_PROD
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_ANTDIV_FEM_38M4HZ_PROFILE_IEEE802154OQPSK
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_38M4Hz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_38M4Hz_channels[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_FEM_38M4HZ_PHY_IEEE802154_2P4GHZ_FEM_PROD
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_FEM_38M4HZ_PROFILE_IEEE802154OQPSK
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_fem_38M4Hz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_fem_38M4Hz_channels[];
+
+#endif // __SL_RAIL_IEEE802154_CONFIG_38M4HZ_H__

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ieee802154_config_39MHz.c

@@ -0,0 +1,880 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#include "em_device.h"
+#include "sl_rail_ieee802154_config_39MHz.h"
+
+static const uint8_t irCalConfig[] = {
+  25, 63, 1, 6, 4, 16, 1, 0, 0, 1, 1, 6, 0, 16, 39, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static const int32_t timingConfig_0[] = {
+  6125, 6125, 500, 0
+};
+
+static const int32_t timingConfig_1[] = {
+  6625, 6625, 500, 0
+};
+
+static const uint8_t hfxoRetimingConfigEntries[] = {
+  2, 0, 0, 0, 0xc0, 0x17, 0x53, 0x02, 6, 20, 0, 0, 0x80, 0x2f, 0xa6, 0x04, 5, 56, 0, 0, 0xa0, 0x08, 0, 0, 0, 0, 0x58, 0x09, 1, 4, 7, 6, 0x10, 0x0a, 1, 4, 7, 7, 0xc8, 0x0a, 0, 4, 8, 7, 0x80, 0x0b, 0, 4, 8, 8, 0x38, 0x0c, 0, 4, 9, 8, 0x61, 0x08, 0, 0, 0, 0, 0x8a, 0x08, 0, 0, 0, 0, 0xc7, 0x09, 1, 4, 4, 3, 0x2c, 0x0b, 1, 4, 4, 4, 0x92, 0x0c, 1, 4, 5, 4
+};
+
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+static const uint8_t stackInfo_0[2] = { 0x05, 0x03 };
+static const uint8_t stackInfo_1[2] = { 0x05, 0x00 };
+static const uint8_t stackInfo_2[2] = { 0x05, 0x04 };
+static const uint8_t stackInfo_3[2] = { 0x05, 0x06 };
+static const uint8_t stackInfo_4[2] = { 0x05, 0x05 };
+#endif // RADIO_CONFIG_ENABLE_STACK_INFO
+
+static RAIL_ChannelConfigEntryAttr_t channelConfigEntryAttr = {
+#if RAIL_SUPPORTS_OFDM_PA
+  {
+#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+    { 0xFFFFFFFFUL, 0xFFFFFFFFUL, },
+#else
+    { 0xFFFFFFFFUL },
+#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+    { 0xFFFFFFFFUL, 0xFFFFFFFFUL }
+  }
+#else // RAIL_SUPPORTS_OFDM_PA
+#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+  { 0xFFFFFFFFUL, 0xFFFFFFFFUL, },
+#else
+  { 0xFFFFFFFFUL },
+#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+#endif // RAIL_SUPPORTS_OFDM_PA
+};
+
+static const uint32_t phyInfo_0[] = {
+  18UL,
+  0x00666666UL, // 102.39999999999999
+  (uint32_t) NULL,
+  (uint32_t) irCalConfig,
+  (uint32_t) timingConfig_0,
+  0x00000000UL,
+  0UL,
+  40000000UL,
+  2000000UL,
+  0x00F62004UL,
+  0x025047F1UL,
+  (uint32_t) NULL,
+  (uint32_t) hfxoRetimingConfigEntries,
+  (uint32_t) NULL,
+  0UL,
+  0UL,
+  1999970UL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+};
+
+static const uint32_t phyInfo_1[] = {
+  18UL,
+  0x00666666UL, // 102.39999999999999
+  (uint32_t) NULL,
+  (uint32_t) irCalConfig,
+  (uint32_t) timingConfig_1,
+  0x00000A00UL,
+  0UL,
+  40000000UL,
+  2000000UL,
+  0x00F82004UL,
+  0x025047F1UL,
+  (uint32_t) NULL,
+  (uint32_t) hfxoRetimingConfigEntries,
+  (uint32_t) NULL,
+  0UL,
+  0UL,
+  1999970UL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+};
+
+static const uint32_t phyInfo_2[] = {
+  18UL,
+  0x00666666UL, // 102.39999999999999
+  (uint32_t) NULL,
+  (uint32_t) irCalConfig,
+  (uint32_t) timingConfig_1,
+  0x00000B00UL,
+  0UL,
+  40000000UL,
+  2000000UL,
+  0x00F82004UL,
+  0x025047F1UL,
+  (uint32_t) NULL,
+  (uint32_t) hfxoRetimingConfigEntries,
+  (uint32_t) NULL,
+  0UL,
+  0UL,
+  1999970UL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_39MHz_modemConfigBase[] = {
+  0x0002400CUL, 0x00148001UL,
+  /*    4010 */ 0x0000407FUL,
+  0x00024020UL, 0x00000000UL,
+  /*    4024 */ 0x00000000UL,
+  0x00074030UL, 0x00000000UL,
+  /*    4034 */ 0x00000000UL,
+  /*    4038 */ 0x00000000UL,
+  /*    403C */ 0x00000000UL,
+  /*    4040 */ 0x00000000UL,
+  /*    4044 */ 0x00004000UL,
+  /*    4048 */ 0x030007A0UL,
+  0x00014050UL, 0x00000000UL,
+  0x0002405CUL, 0x00000000UL,
+  /*    4060 */ 0x00000000UL,
+  0x000140A8UL, 0x00000007UL,
+  0x000440BCUL, 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  0x00044108UL, 0x00004000UL,
+  /*    410C */ 0x00004CFFUL,
+  /*    4110 */ 0x00004100UL,
+  /*    4114 */ 0x00004DFFUL,
+  0x0007C028UL, 0x03B380ECUL,
+  /*    C02C */ 0x51407543UL,
+  /*    C030 */ 0xF8000FA0UL,
+  /*    C034 */ 0x00004000UL,
+  /*    C038 */ 0x0007AAA8UL,
+  /*    C03C */ 0x00000000UL,
+  /*    C040 */ 0x00000000UL,
+  0x0005C054UL, 0x00303151UL,
+  /*    C058 */ 0xE60D000EUL,
+  /*    C05C */ 0x0000002AUL,
+  /*    C060 */ 0x0D0C0B08UL,
+  /*    C064 */ 0x0000000DUL,
+  0x0009C070UL, 0x000010BAUL,
+  /*    C074 */ 0x00200400UL,
+  /*    C078 */ 0x00801804UL,
+  /*    C07C */ 0x01203C0BUL,
+  /*    C080 */ 0x02107C18UL,
+  /*    C084 */ 0x06E0FC2FUL,
+  /*    C088 */ 0x0000007FUL,
+  /*    C08C */ 0x00000000UL,
+  /*    C090 */ 0x00000000UL,
+  0x0005C0A8UL, 0x15724BBDUL,
+  /*    C0AC */ 0x0518A311UL,
+  /*    C0B0 */ 0x76543210UL,
+  /*    C0B4 */ 0x00000A98UL,
+  /*    C0B8 */ 0x00000000UL,
+  0x0001C0CCUL, 0x00000001UL,
+  0x0002C0D4UL, 0x000A0001UL,
+  /*    C0D8 */ 0x00280001UL,
+  0x01010008UL, 0x00000704UL,
+  0x01010018UL, 0x00000000UL,
+  0x01010020UL, 0x00008408UL,
+  0x01034040UL, 0x00000000UL,
+  /*    4044 */ 0x00000000UL,
+  /*    4048 */ 0x00000010UL,
+  0x01024058UL, 0x00000000UL,
+  /*    405C */ 0x03000000UL,
+  0x01064068UL, 0x00F00249UL,
+  /*    406C */ 0x00000841UL,
+  /*    4070 */ 0x00000002UL,
+  /*    4074 */ 0x000807B0UL,
+  /*    4078 */ 0x000000A7UL,
+  /*    407C */ 0x00000000UL,
+  0x01024084UL, 0x744AC39BUL,
+  /*    4088 */ 0x000F03F0UL,
+  0x01104094UL, 0x30100101UL,
+  /*    4098 */ 0x7F7F7050UL,
+  /*    409C */ 0x00000000UL,
+  /*    40A0 */ 0x00000000UL,
+  /*    40A4 */ 0x00000000UL,
+  /*    40A8 */ 0x00000000UL,
+  /*    40AC */ 0x00000000UL,
+  /*    40B0 */ 0x00000000UL,
+  /*    40B4 */ 0x00000000UL,
+  /*    40B8 */ 0x00000000UL,
+  /*    40BC */ 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  /*    40CC */ 0x00000000UL,
+  /*    40D0 */ 0x00000000UL,
+  0x010140E0UL, 0x00000200UL,
+  0x01024110UL, 0x00051E33UL,
+  /*    4114 */ 0x00000000UL,
+  0x0101411CUL, 0x8BC29000UL,
+  0x01054124UL, 0x078304FFUL,
+  /*    4128 */ 0x3AC81388UL,
+  /*    412C */ 0x0C6606FFUL,
+  /*    4130 */ 0x078304FFUL,
+  /*    4134 */ 0x03FF1388UL,
+  0x0106413CUL, 0x005254F8UL,
+  /*    4140 */ 0x00000000UL,
+  /*    4144 */ 0x123556B7UL,
+  /*    4148 */ 0x50000000UL,
+  /*    414C */ 0x00003B80UL,
+  /*    4150 */ 0x00000000UL,
+  0x01014158UL, 0x00000000UL,
+  0x01024164UL, 0x0000010CUL,
+  /*    4168 */ 0x00FA53E8UL,
+  0x010141A4UL, 0x00000000UL,
+  0x010241B0UL, 0x00000000UL,
+  /*    41B4 */ 0x00200000UL,
+  0x010341BCUL, 0x00000000UL,
+  /*    41C0 */ 0x003C0000UL,
+  /*    41C4 */ 0x00069069UL,
+  0x010341D0UL, 0x00000000UL,
+  /*    41D4 */ 0x000000D0UL,
+  /*    41D8 */ 0x00020000UL,
+  0x011641E0UL, 0x00000000UL,
+  /*    41E4 */ 0x365E63DEUL,
+  /*    41E8 */ 0x00076FBFUL,
+  /*    41EC */ 0x0016EA6FUL,
+  /*    41F0 */ 0x00CE30E5UL,
+  /*    41F4 */ 0x0ED9B9B2UL,
+  /*    41F8 */ 0x0494844BUL,
+  /*    41FC */ 0x24A91F5AUL,
+  /*    4200 */ 0x365E63DEUL,
+  /*    4204 */ 0x00076FBFUL,
+  /*    4208 */ 0x0016EA6FUL,
+  /*    420C */ 0x00CE30E5UL,
+  /*    4210 */ 0x0ED9B9B2UL,
+  /*    4214 */ 0x0494844BUL,
+  /*    4218 */ 0x24A91F5AUL,
+  /*    421C */ 0x00000000UL,
+  /*    4220 */ 0x00000000UL,
+  /*    4224 */ 0x0000002CUL,
+  /*    4228 */ 0x3675EE07UL,
+  /*    422C */ 0x40001860UL,
+  /*    4230 */ 0x00000000UL,
+  /*    4234 */ 0x00000000UL,
+  0x01034244UL, 0x00000014UL,
+  /*    4248 */ 0x00000000UL,
+  /*    424C */ 0x04000008UL,
+  0x01014268UL, 0x00000000UL,
+  0x01024298UL, 0x0200003FUL,
+  /*    429C */ 0x0000FFFFUL,
+  0x0104433CUL, 0x1F1F1F1FUL,
+  /*    4340 */ 0x1B1F1F1FUL,
+  /*    4344 */ 0x11131518UL,
+  /*    4348 */ 0x0C0D0E10UL,
+  0x01024350UL, 0x00000000UL,
+  /*    4354 */ 0x00000000UL,
+  0x01018010UL, 0x00000003UL,
+  0x01028038UL, 0x001047F1UL,
+  /*    803C */ 0x00000001UL,
+  0x0103809CUL, 0x000240EBUL,
+  /*    80A0 */ 0x00037870UL,
+  /*    80A4 */ 0x0000C0D5UL,
+  0x110180A8UL, 0x000001F0UL,
+  0x310180A8UL, 0x01CB4205UL,
+  0x110180ACUL, 0x000001F0UL,
+  0x310180ACUL, 0x008D2205UL,
+  0x010280B0UL, 0x02000300UL,
+  /*    80B4 */ 0x01000037UL,
+  0x0201009CUL, 0x04000C00UL,
+  0x020300D8UL, 0xAA400005UL,
+  /*    00DC */ 0x00000188UL,
+  /*    00E0 */ 0x000000C0UL,
+  0x120100ECUL, 0x00000FE0UL,
+  0x320100ECUL, 0x1151200CUL,
+  0x020100F0UL, 0x0000012BUL,
+  0x12010110UL, 0x000FFF00UL,
+  0x32010110UL, 0x31000002UL,
+  0x12010150UL, 0x0001C000UL,
+  0x32010150UL, 0x00A200C1UL,
+  0x02010174UL, 0x0C1B8169UL,
+  0x12010178UL, 0x001C0000UL,
+  0x32010178UL, 0xCFE00410UL,
+  0x12010180UL, 0x00000779UL,
+  0x32010180UL, 0x00000002UL,
+  0x02020184UL, 0x00000000UL,
+  /*    0188 */ 0x00000050UL,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_39MHz_modemConfigBase[] = {
+  0x0002400CUL, 0x00148001UL,
+  /*    4010 */ 0x0000407FUL,
+  0x00024020UL, 0x00000000UL,
+  /*    4024 */ 0x00000000UL,
+  0x00074030UL, 0x00000000UL,
+  /*    4034 */ 0x00000000UL,
+  /*    4038 */ 0x00000000UL,
+  /*    403C */ 0x00000000UL,
+  /*    4040 */ 0x00000000UL,
+  /*    4044 */ 0x00004000UL,
+  /*    4048 */ 0x030007A0UL,
+  0x00014050UL, 0x00000000UL,
+  0x0002405CUL, 0x00000000UL,
+  /*    4060 */ 0x00000000UL,
+  0x000140A8UL, 0x00000007UL,
+  0x000440BCUL, 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  0x00044108UL, 0x00004000UL,
+  /*    410C */ 0x00004CFFUL,
+  /*    4110 */ 0x00004100UL,
+  /*    4114 */ 0x00004DFFUL,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x012801FEUL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00001400UL,
+  0x0008C028UL, 0x03B380ECUL,
+  /*    C02C */ 0x51407543UL,
+  /*    C030 */ 0xF8000FA0UL,
+  /*    C034 */ 0x00004000UL,
+  /*    C038 */ 0x0007AAA8UL,
+  /*    C03C */ 0x00000000UL,
+  /*    C040 */ 0x00000000UL,
+  /*    C044 */ 0x00000000UL,
+  0x0010C054UL, 0x00303151UL,
+  /*    C058 */ 0xE6070007UL,
+  /*    C05C */ 0x00000015UL,
+  /*    C060 */ 0x07060604UL,
+  /*    C064 */ 0x00000007UL,
+  /*    C068 */ 0x0002C688UL,
+  /*    C06C */ 0x00000500UL,
+  /*    C070 */ 0x000010BAUL,
+  /*    C074 */ 0x00200400UL,
+  /*    C078 */ 0x00801804UL,
+  /*    C07C */ 0x01203C0BUL,
+  /*    C080 */ 0x02107C18UL,
+  /*    C084 */ 0x06E0FC2FUL,
+  /*    C088 */ 0x0000007FUL,
+  /*    C08C */ 0x00000000UL,
+  /*    C090 */ 0x00000000UL,
+  0x0005C0A8UL, 0x15724BBDUL,
+  /*    C0AC */ 0x0518A311UL,
+  /*    C0B0 */ 0x76543210UL,
+  /*    C0B4 */ 0x00000A98UL,
+  /*    C0B8 */ 0x00000000UL,
+  0x0004C0CCUL, 0x00000001UL,
+  /*    C0D0 */ 0x000000A1UL,
+  /*    C0D4 */ 0x000A0001UL,
+  /*    C0D8 */ 0x00280001UL,
+  0x01010008UL, 0x00000704UL,
+  0x01010018UL, 0x00000000UL,
+  0x01010020UL, 0x00008408UL,
+  0x01254040UL, 0x00000000UL,
+  /*    4044 */ 0x00000000UL,
+  /*    4048 */ 0x00000010UL,
+  /*    404C */ 0x0413FB20UL,
+  /*    4050 */ 0x0042C007UL,
+  /*    4054 */ 0x00000000UL,
+  /*    4058 */ 0x00000000UL,
+  /*    405C */ 0x03000000UL,
+  /*    4060 */ 0x20000000UL,
+  /*    4064 */ 0x0002B820UL,
+  /*    4068 */ 0x00F00249UL,
+  /*    406C */ 0x00000841UL,
+  /*    4070 */ 0x00000002UL,
+  /*    4074 */ 0x000807B0UL,
+  /*    4078 */ 0x000000A7UL,
+  /*    407C */ 0x00000000UL,
+  /*    4080 */ 0x08A0025AUL,
+  /*    4084 */ 0x744AC39BUL,
+  /*    4088 */ 0x000F03F0UL,
+  /*    408C */ 0x60000000UL,
+  /*    4090 */ 0x00000000UL,
+  /*    4094 */ 0x30100101UL,
+  /*    4098 */ 0x7F7F7050UL,
+  /*    409C */ 0x00000000UL,
+  /*    40A0 */ 0x00000000UL,
+  /*    40A4 */ 0x00000000UL,
+  /*    40A8 */ 0x00000000UL,
+  /*    40AC */ 0x00000000UL,
+  /*    40B0 */ 0x00000000UL,
+  /*    40B4 */ 0x00000000UL,
+  /*    40B8 */ 0x00000000UL,
+  /*    40BC */ 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  /*    40CC */ 0x00000000UL,
+  /*    40D0 */ 0x00000000UL,
+  0x010140E0UL, 0x00000200UL,
+  0x01024110UL, 0x00051E73UL,
+  /*    4114 */ 0x00000000UL,
+  0x010E411CUL, 0x8BC29000UL,
+  /*    4120 */ 0x00000111UL,
+  /*    4124 */ 0x078304FFUL,
+  /*    4128 */ 0x3AC81388UL,
+  /*    412C */ 0x0C6606FFUL,
+  /*    4130 */ 0x078304FFUL,
+  /*    4134 */ 0x03FF1388UL,
+  /*    4138 */ 0xF00A20BCUL,
+  /*    413C */ 0x005254F8UL,
+  /*    4140 */ 0x00000000UL,
+  /*    4144 */ 0x123556B7UL,
+  /*    4148 */ 0x50000000UL,
+  /*    414C */ 0x00003B80UL,
+  /*    4150 */ 0x00000000UL,
+  0x01024158UL, 0x00000000UL,
+  /*    415C */ 0x00001003UL,
+  0x010D4164UL, 0x0000010CUL,
+  /*    4168 */ 0x00FA53E8UL,
+  /*    416C */ 0x40000000UL,
+  /*    4170 */ 0x00000000UL,
+  /*    4174 */ 0x00000000UL,
+  /*    4178 */ 0x00000000UL,
+  /*    417C */ 0x00000000UL,
+  /*    4180 */ 0x00000000UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x00000000UL,
+  /*    418C */ 0x00000000UL,
+  /*    4190 */ 0x00000000UL,
+  /*    4194 */ 0x00000000UL,
+  0x010241A4UL, 0x00000000UL,
+  /*    41A8 */ 0x00000000UL,
+  0x010241B0UL, 0x00000000UL,
+  /*    41B4 */ 0x00200000UL,
+  0x010341BCUL, 0x00000000UL,
+  /*    41C0 */ 0x003C0000UL,
+  /*    41C4 */ 0x00069069UL,
+  0x010341D0UL, 0x00000000UL,
+  /*    41D4 */ 0x000000D0UL,
+  /*    41D8 */ 0x00020000UL,
+  0x011641E0UL, 0x00000000UL,
+  /*    41E4 */ 0x365E63DEUL,
+  /*    41E8 */ 0x00076FBFUL,
+  /*    41EC */ 0x0016EA6FUL,
+  /*    41F0 */ 0x00CE30E5UL,
+  /*    41F4 */ 0x0ED9B9B2UL,
+  /*    41F8 */ 0x0494844BUL,
+  /*    41FC */ 0x24A91F5AUL,
+  /*    4200 */ 0x365E63DEUL,
+  /*    4204 */ 0x00076FBFUL,
+  /*    4208 */ 0x0016EA6FUL,
+  /*    420C */ 0x00CE30E5UL,
+  /*    4210 */ 0x0ED9B9B2UL,
+  /*    4214 */ 0x0494844BUL,
+  /*    4218 */ 0x24A91F5AUL,
+  /*    421C */ 0x00000000UL,
+  /*    4220 */ 0x00000000UL,
+  /*    4224 */ 0x0000002CUL,
+  /*    4228 */ 0x3675EE07UL,
+  /*    422C */ 0x00001860UL,
+  /*    4230 */ 0x00000000UL,
+  /*    4234 */ 0x00000000UL,
+  0x0101423CUL, 0x00000112UL,
+  0x01034244UL, 0x00000014UL,
+  /*    4248 */ 0x00000000UL,
+  /*    424C */ 0x04000008UL,
+  0x01014268UL, 0x00000000UL,
+  0x01024280UL, 0x40090001UL,
+  /*    4284 */ 0x00100801UL,
+  0x01054298UL, 0x0200003FUL,
+  /*    429C */ 0x0000FFFFUL,
+  /*    42A0 */ 0x03E80000UL,
+  /*    42A4 */ 0x00000200UL,
+  /*    42A8 */ 0x00100000UL,
+  0x010142B4UL, 0x00C00000UL,
+  0x010A4330UL, 0x02400040UL,
+  /*    4334 */ 0x04AC0140UL,
+  /*    4338 */ 0x0100B050UL,
+  /*    433C */ 0x1F1F1F1FUL,
+  /*    4340 */ 0x1B1F1F1FUL,
+  /*    4344 */ 0x11131518UL,
+  /*    4348 */ 0x0C0D0E10UL,
+  /*    434C */ 0x2D0F285DUL,
+  /*    4350 */ 0x00000000UL,
+  /*    4354 */ 0x00000000UL,
+  0x01018010UL, 0x00000003UL,
+  0x01028038UL, 0x001047F1UL,
+  /*    803C */ 0x00000001UL,
+  0x0103809CUL, 0x000240EBUL,
+  /*    80A0 */ 0x0000C0D5UL,
+  /*    80A4 */ 0x0000C0D5UL,
+  0x110180A8UL, 0x000001F0UL,
+  0x310180A8UL, 0x008D2205UL,
+  0x110180ACUL, 0x000001F0UL,
+  0x310180ACUL, 0x008D2205UL,
+  0x010280B0UL, 0x0100003FUL,
+  /*    80B4 */ 0x01000037UL,
+  0x0201009CUL, 0x04000C00UL,
+  0x020300D8UL, 0xAA400005UL,
+  /*    00DC */ 0x00000188UL,
+  /*    00E0 */ 0x000000C0UL,
+  0x120100ECUL, 0x00000FE0UL,
+  0x320100ECUL, 0x1151200CUL,
+  0x020100F0UL, 0x0000012BUL,
+  0x12010110UL, 0x000FFF00UL,
+  0x32010110UL, 0x31000002UL,
+  0x12010150UL, 0x0001C000UL,
+  0x32010150UL, 0x00A200C1UL,
+  0x02010174UL, 0x0C1FF169UL,
+  0x12010178UL, 0x001C0000UL,
+  0x32010178UL, 0x1FE00410UL,
+  0x12010180UL, 0x00000779UL,
+  0x02020184UL, 0x00000000UL,
+  /*    0188 */ 0x00000048UL,
+  0x03014FFCUL, (uint32_t) &phyInfo_1,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_39MHz_modemConfig[] = {
+  0x03014FFCUL, (uint32_t) &phyInfo_0,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x01280214UL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00004300UL,
+  0x0001C044UL, 0x0000022EUL,
+  0x0002C068UL, 0x0002B6D1UL,
+  /*    C06C */ 0x000006C0UL,
+  0x0001C0D0UL, 0x00000000UL,
+  0x0103404CUL, 0x0413F920UL,
+  /*    4050 */ 0x00620007UL,
+  /*    4054 */ 0x00007038UL,
+  0x01024060UL, 0x0F016800UL,
+  /*    4064 */ 0x4024B840UL,
+  0x01014080UL, 0x00006323UL,
+  0x0102408CUL, 0x60008000UL,
+  /*    4090 */ 0x00000ABEUL,
+  0x01014120UL, 0x00000B59UL,
+  0x01014138UL, 0xF00A2090UL,
+  0x0101415CUL, 0x00001E00UL,
+  0x010B416CUL, 0xC00C1400UL,
+  /*    4170 */ 0x28211A14UL,
+  /*    4174 */ 0x423B342EUL,
+  /*    4178 */ 0x55435049UL,
+  /*    417C */ 0x0CBA9876UL,
+  /*    4180 */ 0x00007323UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x64282117UL,
+  /*    418C */ 0x001A1714UL,
+  /*    4190 */ 0x7DC80420UL,
+  /*    4194 */ 0x093A20A1UL,
+  0x010141A8UL, 0x00000029UL,
+  0x0101423CUL, 0x00000000UL,
+  0x01024280UL, 0x00000000UL,
+  /*    4284 */ 0x00000081UL,
+  0x010342A0UL, 0x0000FFFFUL,
+  /*    42A4 */ 0x000003FFUL,
+  /*    42A8 */ 0x0000FFFFUL,
+  0x010142B4UL, 0x00000000UL,
+  0x01034330UL, 0x01200040UL,
+  /*    4334 */ 0x000000A0UL,
+  /*    4338 */ 0x01005008UL,
+  0x0101434CUL, 0x2F87C145UL,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_antdiv_39MHz_modemConfig[] = {
+  0x03014FFCUL, (uint32_t) &phyInfo_2,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x012801FEUL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00001400UL,
+  0x0001C044UL, 0x00000000UL,
+  0x0002C068UL, 0x0002C688UL,
+  /*    C06C */ 0x00000500UL,
+  0x0001C0D0UL, 0x000000A1UL,
+  0x0103404CUL, 0x0413FB20UL,
+  /*    4050 */ 0x0042C007UL,
+  /*    4054 */ 0x00000000UL,
+  0x01024060UL, 0x28000000UL,
+  /*    4064 */ 0x00028000UL,
+  0x01014080UL, 0x08A0015AUL,
+  0x0102408CUL, 0x60000000UL,
+  /*    4090 */ 0x00000000UL,
+  0x01014120UL, 0x00000000UL,
+  0x01014138UL, 0xF00A20BCUL,
+  0x0101415CUL, 0x00001003UL,
+  0x010B416CUL, 0x40000000UL,
+  /*    4170 */ 0x00000000UL,
+  /*    4174 */ 0x00000000UL,
+  /*    4178 */ 0x00000000UL,
+  /*    417C */ 0x00000000UL,
+  /*    4180 */ 0x00000000UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x00000000UL,
+  /*    418C */ 0x00000000UL,
+  /*    4190 */ 0x00000000UL,
+  /*    4194 */ 0x00000000UL,
+  0x010141A8UL, 0x00000000UL,
+  0x0101423CUL, 0x00000112UL,
+  0x01024280UL, 0x40090001UL,
+  /*    4284 */ 0x00100801UL,
+  0x010342A0UL, 0x03E80000UL,
+  /*    42A4 */ 0x00000200UL,
+  /*    42A8 */ 0x00100000UL,
+  0x010142B4UL, 0x00C00000UL,
+  0x01034330UL, 0x02400041UL,
+  /*    4334 */ 0x04AC0140UL,
+  /*    4338 */ 0x0100B050UL,
+  0x0101434CUL, 0x2D0F285DUL,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_39MHz_modemConfig[] = {
+  0x03014FFCUL, (uint32_t) &phyInfo_2,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x012801FEUL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00001400UL,
+  0x0001C044UL, 0x00000000UL,
+  0x0002C068UL, 0x0002C688UL,
+  /*    C06C */ 0x00000500UL,
+  0x0001C0D0UL, 0x000000A1UL,
+  0x0103404CUL, 0x0413FB20UL,
+  /*    4050 */ 0x0042C007UL,
+  /*    4054 */ 0x00000000UL,
+  0x01024060UL, 0x28000000UL,
+  /*    4064 */ 0x00028000UL,
+  0x01014080UL, 0x08A0015AUL,
+  0x0102408CUL, 0x60000000UL,
+  /*    4090 */ 0x00000000UL,
+  0x01014120UL, 0x00000000UL,
+  0x01014138UL, 0xF00A20BCUL,
+  0x0101415CUL, 0x00001003UL,
+  0x010B416CUL, 0x40000000UL,
+  /*    4170 */ 0x00000000UL,
+  /*    4174 */ 0x00000000UL,
+  /*    4178 */ 0x00000000UL,
+  /*    417C */ 0x00000000UL,
+  /*    4180 */ 0x00000000UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x00000000UL,
+  /*    418C */ 0x00000000UL,
+  /*    4190 */ 0x00000000UL,
+  /*    4194 */ 0x00000000UL,
+  0x010141A8UL, 0x00000000UL,
+  0x0101423CUL, 0x00000112UL,
+  0x01024280UL, 0x40090001UL,
+  /*    4284 */ 0x00100801UL,
+  0x010342A0UL, 0x03E80000UL,
+  /*    42A4 */ 0x00000200UL,
+  /*    42A8 */ 0x00100000UL,
+  0x010142B4UL, 0x00C00000UL,
+  0x01034330UL, 0x02400041UL,
+  /*    4334 */ 0x05B40140UL,
+  /*    4338 */ 0x0100B050UL,
+  0x0101434CUL, 0x2D0F285DUL,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_fem_39MHz_modemConfig[] = {
+  0x03014FFCUL, (uint32_t) &phyInfo_0,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x01280214UL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00004300UL,
+  0x0001C044UL, 0x0000022EUL,
+  0x0002C068UL, 0x0002B6D1UL,
+  /*    C06C */ 0x000006C0UL,
+  0x0001C0D0UL, 0x00000000UL,
+  0x0103404CUL, 0x0413F920UL,
+  /*    4050 */ 0x00620007UL,
+  /*    4054 */ 0x00007038UL,
+  0x01024060UL, 0x0F016800UL,
+  /*    4064 */ 0x4024B840UL,
+  0x01014080UL, 0x00006323UL,
+  0x0102408CUL, 0x60008000UL,
+  /*    4090 */ 0x00000ABEUL,
+  0x01014120UL, 0x00000B59UL,
+  0x01014138UL, 0xF00A2090UL,
+  0x0101415CUL, 0x00001E00UL,
+  0x010B416CUL, 0xC00C1400UL,
+  /*    4170 */ 0x2E27201AUL,
+  /*    4174 */ 0x48413A34UL,
+  /*    4178 */ 0x6654564FUL,
+  /*    417C */ 0x0DCBA987UL,
+  /*    4180 */ 0x00007323UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x6A2E2717UL,
+  /*    418C */ 0x001A1714UL,
+  /*    4190 */ 0x7DC80420UL,
+  /*    4194 */ 0x093A20A1UL,
+  0x010141A8UL, 0x00000029UL,
+  0x0101423CUL, 0x00000000UL,
+  0x01024280UL, 0x00000000UL,
+  /*    4284 */ 0x00000081UL,
+  0x010342A0UL, 0x0000FFFFUL,
+  /*    42A4 */ 0x000003FFUL,
+  /*    42A8 */ 0x0000FFFFUL,
+  0x010142B4UL, 0x00000000UL,
+  0x01034330UL, 0x01200040UL,
+  /*    4334 */ 0x000000A0UL,
+  /*    4338 */ 0x01005008UL,
+  0x0101434CUL, 0x2F87C145UL,
+  0xFFFFFFFFUL,
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_39MHz_channels[] = {
+  {
+    .phyConfigDeltaAdd = sl_rail_ieee802154_phy_2G4Hz_39MHz_modemConfig,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_0,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_39MHz_channels[] = {
+  {
+    .phyConfigDeltaAdd = NULL,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_1,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_antdiv_39MHz_channels[] = {
+  {
+    .phyConfigDeltaAdd = sl_rail_ieee802154_phy_2G4Hz_antdiv_39MHz_modemConfig,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_2,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_39MHz_channels[] = {
+  {
+    .phyConfigDeltaAdd = sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_39MHz_modemConfig,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_3,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_fem_39MHz_channels[] = {
+  {
+    .phyConfigDeltaAdd = sl_rail_ieee802154_phy_2G4Hz_fem_39MHz_modemConfig,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_4,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_39MHz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_39MHz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_39MHz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 39000000UL,
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_39MHz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_fast_switch_39MHz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_fast_switch_39MHz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 39000000UL,
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_antdiv_39MHz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_39MHz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_antdiv_39MHz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 39000000UL,
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_39MHz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_39MHz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_39MHz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 39000000UL,
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_fem_39MHz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_39MHz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_fem_39MHz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 39000000UL,
+};

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ieee802154_config_39MHz.h

@@ -0,0 +1,74 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config Header  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __SL_RAIL_IEEE802154_CONFIG_39MHZ_H__
+#define __SL_RAIL_IEEE802154_CONFIG_39MHZ_H__
+
+#include <stdint.h>
+#include "rail_types.h"
+
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_39MHz_modemConfigBase[];
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_39MHz_modemConfigBase[];
+
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_39MHz_modemConfig[];
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_antdiv_39MHz_modemConfig[];
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_39MHz_modemConfig[];
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_fem_39MHz_modemConfig[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_39MHZ_PHY_IEEE802154_2P4GHZ_PROD
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_39MHZ_PROFILE_IEEE802154OQPSK
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_39MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_39MHz_channels[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_FAST_SWITCH_39MHZ_PHY_IEEE802154_2P4GHZ_ANTDIV_FASTSWITCH
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_FAST_SWITCH_39MHZ_PROFILE_BASE
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_39MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_39MHz_channels[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_ANTDIV_39MHZ_PHY_IEEE802154_2P4GHZ_DIVERSITY_PROD
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_ANTDIV_39MHZ_PROFILE_IEEE802154OQPSK
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_antdiv_39MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_antdiv_39MHz_channels[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_ANTDIV_FEM_39MHZ_PHY_IEEE802154_2P4GHZ_DIVERSITY_FEM_PROD
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_ANTDIV_FEM_39MHZ_PROFILE_IEEE802154OQPSK
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_39MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_39MHz_channels[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_FEM_39MHZ_PHY_IEEE802154_2P4GHZ_FEM_PROD
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_FEM_39MHZ_PROFILE_IEEE802154OQPSK
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_fem_39MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_fem_39MHz_channels[];
+
+#endif // __SL_RAIL_IEEE802154_CONFIG_39MHZ_H__

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ieee802154_config_40MHz.c

@@ -0,0 +1,880 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#include "em_device.h"
+#include "sl_rail_ieee802154_config_40MHz.h"
+
+static const uint8_t irCalConfig[] = {
+  25, 63, 1, 6, 4, 16, 1, 0, 0, 1, 1, 6, 0, 16, 39, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static const int32_t timingConfig_0[] = {
+  6125, 6125, 500, 0
+};
+
+static const int32_t timingConfig_1[] = {
+  6625, 6625, 500, 0
+};
+
+static const uint8_t hfxoRetimingConfigEntries[] = {
+  2, 0, 0, 0, 0x00, 0x5a, 0x62, 0x02, 6, 20, 0, 0, 0x00, 0xb4, 0xc4, 0x04, 7, 56, 0, 0, 0xa0, 0x08, 0, 0, 0, 0, 0x58, 0x09, 1, 4, 7, 6, 0x10, 0x0a, 1, 4, 7, 7, 0xc8, 0x0a, 0, 4, 8, 7, 0x80, 0x0b, 0, 4, 8, 8, 0x38, 0x0c, 0, 4, 9, 8, 0x61, 0x08, 0, 0, 0, 0, 0xc2, 0x08, 0, 0, 0, 0, 0xc7, 0x09, 1, 4, 4, 3, 0xc4, 0x09, 0, 0, 0, 0, 0x2c, 0x0b, 1, 4, 4, 4, 0xc4, 0x09, 0, 0, 0, 0, 0x92, 0x0c, 1, 4, 5, 4
+};
+
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+static const uint8_t stackInfo_0[2] = { 0x05, 0x03 };
+static const uint8_t stackInfo_1[2] = { 0x05, 0x00 };
+static const uint8_t stackInfo_2[2] = { 0x05, 0x04 };
+static const uint8_t stackInfo_3[2] = { 0x05, 0x06 };
+static const uint8_t stackInfo_4[2] = { 0x05, 0x05 };
+#endif // RADIO_CONFIG_ENABLE_STACK_INFO
+
+static RAIL_ChannelConfigEntryAttr_t channelConfigEntryAttr = {
+#if RAIL_SUPPORTS_OFDM_PA
+  {
+#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+    { 0xFFFFFFFFUL, 0xFFFFFFFFUL, },
+#else
+    { 0xFFFFFFFFUL },
+#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+    { 0xFFFFFFFFUL, 0xFFFFFFFFUL }
+  }
+#else // RAIL_SUPPORTS_OFDM_PA
+#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+  { 0xFFFFFFFFUL, 0xFFFFFFFFUL, },
+#else
+  { 0xFFFFFFFFUL },
+#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+#endif // RAIL_SUPPORTS_OFDM_PA
+};
+
+static const uint32_t phyInfo_0[] = {
+  18UL,
+  0x00666666UL, // 102.39999999999999
+  (uint32_t) NULL,
+  (uint32_t) irCalConfig,
+  (uint32_t) timingConfig_0,
+  0x00000000UL,
+  0UL,
+  40000000UL,
+  2000000UL,
+  0x00F62004UL,
+  0x02504624UL,
+  (uint32_t) NULL,
+  (uint32_t) hfxoRetimingConfigEntries,
+  (uint32_t) NULL,
+  0UL,
+  0UL,
+  1999970UL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+};
+
+static const uint32_t phyInfo_1[] = {
+  18UL,
+  0x00666666UL, // 102.39999999999999
+  (uint32_t) NULL,
+  (uint32_t) irCalConfig,
+  (uint32_t) timingConfig_1,
+  0x00000A00UL,
+  0UL,
+  40000000UL,
+  2000000UL,
+  0x00F82004UL,
+  0x02504624UL,
+  (uint32_t) NULL,
+  (uint32_t) hfxoRetimingConfigEntries,
+  (uint32_t) NULL,
+  0UL,
+  0UL,
+  1999970UL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+};
+
+static const uint32_t phyInfo_2[] = {
+  18UL,
+  0x00666666UL, // 102.39999999999999
+  (uint32_t) NULL,
+  (uint32_t) irCalConfig,
+  (uint32_t) timingConfig_1,
+  0x00000B00UL,
+  0UL,
+  40000000UL,
+  2000000UL,
+  0x00F82004UL,
+  0x02504624UL,
+  (uint32_t) NULL,
+  (uint32_t) hfxoRetimingConfigEntries,
+  (uint32_t) NULL,
+  0UL,
+  0UL,
+  1999970UL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_40MHz_modemConfigBase[] = {
+  0x0002400CUL, 0x00148001UL,
+  /*    4010 */ 0x0000407FUL,
+  0x00024020UL, 0x00000000UL,
+  /*    4024 */ 0x00000000UL,
+  0x00074030UL, 0x00000000UL,
+  /*    4034 */ 0x00000000UL,
+  /*    4038 */ 0x00000000UL,
+  /*    403C */ 0x00000000UL,
+  /*    4040 */ 0x00000000UL,
+  /*    4044 */ 0x00004000UL,
+  /*    4048 */ 0x030007A0UL,
+  0x00014050UL, 0x00000000UL,
+  0x0002405CUL, 0x00000000UL,
+  /*    4060 */ 0x00000000UL,
+  0x000140A8UL, 0x00000007UL,
+  0x000440BCUL, 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  0x00044108UL, 0x00004000UL,
+  /*    410C */ 0x00004CFFUL,
+  /*    4110 */ 0x00004100UL,
+  /*    4114 */ 0x00004DFFUL,
+  0x0007C028UL, 0x03B380ECUL,
+  /*    C02C */ 0x51407543UL,
+  /*    C030 */ 0xF8000FA0UL,
+  /*    C034 */ 0x00004000UL,
+  /*    C038 */ 0x0007AAA8UL,
+  /*    C03C */ 0x00000000UL,
+  /*    C040 */ 0x00000000UL,
+  0x0005C054UL, 0x00303151UL,
+  /*    C058 */ 0xE60E000FUL,
+  /*    C05C */ 0x0000002DUL,
+  /*    C060 */ 0x0E0D0B08UL,
+  /*    C064 */ 0x0000000EUL,
+  0x0009C070UL, 0x000010BAUL,
+  /*    C074 */ 0x00200400UL,
+  /*    C078 */ 0x00801804UL,
+  /*    C07C */ 0x01203C0BUL,
+  /*    C080 */ 0x02107C18UL,
+  /*    C084 */ 0x06E0FC2FUL,
+  /*    C088 */ 0x0000007FUL,
+  /*    C08C */ 0x00000000UL,
+  /*    C090 */ 0x00000000UL,
+  0x0005C0A8UL, 0x15724BBDUL,
+  /*    C0AC */ 0x0518A311UL,
+  /*    C0B0 */ 0x76543210UL,
+  /*    C0B4 */ 0x00000A98UL,
+  /*    C0B8 */ 0x00000000UL,
+  0x0001C0CCUL, 0x00000001UL,
+  0x0002C0D4UL, 0x000A0001UL,
+  /*    C0D8 */ 0x00280001UL,
+  0x01010008UL, 0x00000704UL,
+  0x01010018UL, 0x00000000UL,
+  0x01010020UL, 0x00008408UL,
+  0x01034040UL, 0x00000000UL,
+  /*    4044 */ 0x00000000UL,
+  /*    4048 */ 0x00000010UL,
+  0x01024058UL, 0x00000000UL,
+  /*    405C */ 0x03000000UL,
+  0x01064068UL, 0x00FE027BUL,
+  /*    406C */ 0x00000841UL,
+  /*    4070 */ 0x00000002UL,
+  /*    4074 */ 0x000807B0UL,
+  /*    4078 */ 0x000000A7UL,
+  /*    407C */ 0x00000000UL,
+  0x01024084UL, 0x744AC39BUL,
+  /*    4088 */ 0x000F03F0UL,
+  0x01104094UL, 0x30100101UL,
+  /*    4098 */ 0x7F7F7050UL,
+  /*    409C */ 0x00000000UL,
+  /*    40A0 */ 0x00000000UL,
+  /*    40A4 */ 0x00000000UL,
+  /*    40A8 */ 0x00000000UL,
+  /*    40AC */ 0x00000000UL,
+  /*    40B0 */ 0x00000000UL,
+  /*    40B4 */ 0x00000000UL,
+  /*    40B8 */ 0x00000000UL,
+  /*    40BC */ 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  /*    40CC */ 0x00000000UL,
+  /*    40D0 */ 0x00000000UL,
+  0x010140E0UL, 0x00000200UL,
+  0x01024110UL, 0x00051E33UL,
+  /*    4114 */ 0x00000000UL,
+  0x0101411CUL, 0x8BC29000UL,
+  0x01054124UL, 0x078304FFUL,
+  /*    4128 */ 0x3AC81388UL,
+  /*    412C */ 0x0C6606FFUL,
+  /*    4130 */ 0x078304FFUL,
+  /*    4134 */ 0x03FF1388UL,
+  0x0106413CUL, 0x005254F3UL,
+  /*    4140 */ 0x00000000UL,
+  /*    4144 */ 0x123556B7UL,
+  /*    4148 */ 0x50000000UL,
+  /*    414C */ 0x00003B80UL,
+  /*    4150 */ 0x00000000UL,
+  0x01014158UL, 0x00000000UL,
+  0x01024164UL, 0x0000010CUL,
+  /*    4168 */ 0x00FA53E8UL,
+  0x010141A4UL, 0x00000000UL,
+  0x010241B0UL, 0x00000000UL,
+  /*    41B4 */ 0x00200000UL,
+  0x010341BCUL, 0x00000000UL,
+  /*    41C0 */ 0x003C0000UL,
+  /*    41C4 */ 0x00066666UL,
+  0x010341D0UL, 0x00000000UL,
+  /*    41D4 */ 0x000000D0UL,
+  /*    41D8 */ 0x00020000UL,
+  0x011641E0UL, 0x00000000UL,
+  /*    41E4 */ 0x365E63DEUL,
+  /*    41E8 */ 0x00076FBFUL,
+  /*    41EC */ 0x0016EA6FUL,
+  /*    41F0 */ 0x00CE30E5UL,
+  /*    41F4 */ 0x0ED9B9B2UL,
+  /*    41F8 */ 0x0494844BUL,
+  /*    41FC */ 0x24A91F5AUL,
+  /*    4200 */ 0x365E63DEUL,
+  /*    4204 */ 0x00076FBFUL,
+  /*    4208 */ 0x0016EA6FUL,
+  /*    420C */ 0x00CE30E5UL,
+  /*    4210 */ 0x0ED9B9B2UL,
+  /*    4214 */ 0x0494844BUL,
+  /*    4218 */ 0x24A91F5AUL,
+  /*    421C */ 0x00000000UL,
+  /*    4220 */ 0x00000000UL,
+  /*    4224 */ 0x0000002CUL,
+  /*    4228 */ 0x3675EE07UL,
+  /*    422C */ 0x40001860UL,
+  /*    4230 */ 0x00000000UL,
+  /*    4234 */ 0x00000000UL,
+  0x01034244UL, 0x00000014UL,
+  /*    4248 */ 0x00000000UL,
+  /*    424C */ 0x04000008UL,
+  0x01014268UL, 0x00000000UL,
+  0x01024298UL, 0x0200003FUL,
+  /*    429C */ 0x0000FFFFUL,
+  0x0104433CUL, 0x1F1F1F1FUL,
+  /*    4340 */ 0x1B1F1F1FUL,
+  /*    4344 */ 0x11131518UL,
+  /*    4348 */ 0x0C0D0E10UL,
+  0x01024350UL, 0x00000000UL,
+  /*    4354 */ 0x00000000UL,
+  0x01018010UL, 0x00000003UL,
+  0x01028038UL, 0x00104624UL,
+  /*    803C */ 0x00000001UL,
+  0x0103809CUL, 0x000240EBUL,
+  /*    80A0 */ 0x00037870UL,
+  /*    80A4 */ 0x0000C0D5UL,
+  0x110180A8UL, 0x000001F0UL,
+  0x310180A8UL, 0x01CB4205UL,
+  0x110180ACUL, 0x000001F0UL,
+  0x310180ACUL, 0x008D2205UL,
+  0x010280B0UL, 0x02000300UL,
+  /*    80B4 */ 0x01000037UL,
+  0x0201009CUL, 0x04000C00UL,
+  0x020300D8UL, 0xAA400005UL,
+  /*    00DC */ 0x00000188UL,
+  /*    00E0 */ 0x000000C0UL,
+  0x120100ECUL, 0x00000FE0UL,
+  0x320100ECUL, 0x1151200CUL,
+  0x020100F0UL, 0x0000012BUL,
+  0x12010110UL, 0x000FFF00UL,
+  0x32010110UL, 0x31000002UL,
+  0x12010150UL, 0x0001C000UL,
+  0x32010150UL, 0x00A200C1UL,
+  0x02010174UL, 0x0C1B8169UL,
+  0x12010178UL, 0x001C0000UL,
+  0x32010178UL, 0xCFE00410UL,
+  0x12010180UL, 0x00000779UL,
+  0x32010180UL, 0x00000002UL,
+  0x02020184UL, 0x00000000UL,
+  /*    0188 */ 0x00000050UL,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_40MHz_modemConfigBase[] = {
+  0x0002400CUL, 0x00148001UL,
+  /*    4010 */ 0x0000407FUL,
+  0x00024020UL, 0x00000000UL,
+  /*    4024 */ 0x00000000UL,
+  0x00074030UL, 0x00000000UL,
+  /*    4034 */ 0x00000000UL,
+  /*    4038 */ 0x00000000UL,
+  /*    403C */ 0x00000000UL,
+  /*    4040 */ 0x00000000UL,
+  /*    4044 */ 0x00004000UL,
+  /*    4048 */ 0x030007A0UL,
+  0x00014050UL, 0x00000000UL,
+  0x0002405CUL, 0x00000000UL,
+  /*    4060 */ 0x00000000UL,
+  0x000140A8UL, 0x00000007UL,
+  0x000440BCUL, 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  0x00044108UL, 0x00004000UL,
+  /*    410C */ 0x00004CFFUL,
+  /*    4110 */ 0x00004100UL,
+  /*    4114 */ 0x00004DFFUL,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x012801FEUL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00001400UL,
+  0x0008C028UL, 0x03B380ECUL,
+  /*    C02C */ 0x51407543UL,
+  /*    C030 */ 0xF8000FA0UL,
+  /*    C034 */ 0x00004000UL,
+  /*    C038 */ 0x0007AAA8UL,
+  /*    C03C */ 0x00000000UL,
+  /*    C040 */ 0x00000000UL,
+  /*    C044 */ 0x00000000UL,
+  0x0010C054UL, 0x00303151UL,
+  /*    C058 */ 0xE6070007UL,
+  /*    C05C */ 0x00000015UL,
+  /*    C060 */ 0x07060604UL,
+  /*    C064 */ 0x00000007UL,
+  /*    C068 */ 0x0002C688UL,
+  /*    C06C */ 0x00000500UL,
+  /*    C070 */ 0x000010BAUL,
+  /*    C074 */ 0x00200400UL,
+  /*    C078 */ 0x00801804UL,
+  /*    C07C */ 0x01203C0BUL,
+  /*    C080 */ 0x02107C18UL,
+  /*    C084 */ 0x06E0FC2FUL,
+  /*    C088 */ 0x0000007FUL,
+  /*    C08C */ 0x00000000UL,
+  /*    C090 */ 0x00000000UL,
+  0x0005C0A8UL, 0x15724BBDUL,
+  /*    C0AC */ 0x0518A311UL,
+  /*    C0B0 */ 0x76543210UL,
+  /*    C0B4 */ 0x00000A98UL,
+  /*    C0B8 */ 0x00000000UL,
+  0x0004C0CCUL, 0x00000001UL,
+  /*    C0D0 */ 0x000000A1UL,
+  /*    C0D4 */ 0x000A0001UL,
+  /*    C0D8 */ 0x00280001UL,
+  0x01010008UL, 0x00000704UL,
+  0x01010018UL, 0x00000000UL,
+  0x01010020UL, 0x00008408UL,
+  0x01254040UL, 0x00000000UL,
+  /*    4044 */ 0x00000000UL,
+  /*    4048 */ 0x00000010UL,
+  /*    404C */ 0x0413FB20UL,
+  /*    4050 */ 0x0042C007UL,
+  /*    4054 */ 0x00000000UL,
+  /*    4058 */ 0x00000000UL,
+  /*    405C */ 0x03000000UL,
+  /*    4060 */ 0x20000000UL,
+  /*    4064 */ 0x0002B820UL,
+  /*    4068 */ 0x00FE027BUL,
+  /*    406C */ 0x00000841UL,
+  /*    4070 */ 0x00000002UL,
+  /*    4074 */ 0x000807B0UL,
+  /*    4078 */ 0x000000A7UL,
+  /*    407C */ 0x00000000UL,
+  /*    4080 */ 0x08A0025AUL,
+  /*    4084 */ 0x744AC39BUL,
+  /*    4088 */ 0x000F03F0UL,
+  /*    408C */ 0x60000000UL,
+  /*    4090 */ 0x00000000UL,
+  /*    4094 */ 0x30100101UL,
+  /*    4098 */ 0x7F7F7050UL,
+  /*    409C */ 0x00000000UL,
+  /*    40A0 */ 0x00000000UL,
+  /*    40A4 */ 0x00000000UL,
+  /*    40A8 */ 0x00000000UL,
+  /*    40AC */ 0x00000000UL,
+  /*    40B0 */ 0x00000000UL,
+  /*    40B4 */ 0x00000000UL,
+  /*    40B8 */ 0x00000000UL,
+  /*    40BC */ 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  /*    40CC */ 0x00000000UL,
+  /*    40D0 */ 0x00000000UL,
+  0x010140E0UL, 0x00000200UL,
+  0x01024110UL, 0x00051E73UL,
+  /*    4114 */ 0x00000000UL,
+  0x010E411CUL, 0x8BC29000UL,
+  /*    4120 */ 0x00000111UL,
+  /*    4124 */ 0x078304FFUL,
+  /*    4128 */ 0x3AC81388UL,
+  /*    412C */ 0x0C6606FFUL,
+  /*    4130 */ 0x078304FFUL,
+  /*    4134 */ 0x03FF1388UL,
+  /*    4138 */ 0xF00A20BCUL,
+  /*    413C */ 0x005254F3UL,
+  /*    4140 */ 0x00000000UL,
+  /*    4144 */ 0x123556B7UL,
+  /*    4148 */ 0x50000000UL,
+  /*    414C */ 0x00003B80UL,
+  /*    4150 */ 0x00000000UL,
+  0x01024158UL, 0x00000000UL,
+  /*    415C */ 0x00001003UL,
+  0x010D4164UL, 0x0000010CUL,
+  /*    4168 */ 0x00FA53E8UL,
+  /*    416C */ 0x40000000UL,
+  /*    4170 */ 0x00000000UL,
+  /*    4174 */ 0x00000000UL,
+  /*    4178 */ 0x00000000UL,
+  /*    417C */ 0x00000000UL,
+  /*    4180 */ 0x00000000UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x00000000UL,
+  /*    418C */ 0x00000000UL,
+  /*    4190 */ 0x00000000UL,
+  /*    4194 */ 0x00000000UL,
+  0x010241A4UL, 0x00000000UL,
+  /*    41A8 */ 0x00000000UL,
+  0x010241B0UL, 0x00000000UL,
+  /*    41B4 */ 0x00200000UL,
+  0x010341BCUL, 0x00000000UL,
+  /*    41C0 */ 0x003C0000UL,
+  /*    41C4 */ 0x00066666UL,
+  0x010341D0UL, 0x00000000UL,
+  /*    41D4 */ 0x000000D0UL,
+  /*    41D8 */ 0x00020000UL,
+  0x011641E0UL, 0x00000000UL,
+  /*    41E4 */ 0x365E63DEUL,
+  /*    41E8 */ 0x00076FBFUL,
+  /*    41EC */ 0x0016EA6FUL,
+  /*    41F0 */ 0x00CE30E5UL,
+  /*    41F4 */ 0x0ED9B9B2UL,
+  /*    41F8 */ 0x0494844BUL,
+  /*    41FC */ 0x24A91F5AUL,
+  /*    4200 */ 0x365E63DEUL,
+  /*    4204 */ 0x00076FBFUL,
+  /*    4208 */ 0x0016EA6FUL,
+  /*    420C */ 0x00CE30E5UL,
+  /*    4210 */ 0x0ED9B9B2UL,
+  /*    4214 */ 0x0494844BUL,
+  /*    4218 */ 0x24A91F5AUL,
+  /*    421C */ 0x00000000UL,
+  /*    4220 */ 0x00000000UL,
+  /*    4224 */ 0x0000002CUL,
+  /*    4228 */ 0x3675EE07UL,
+  /*    422C */ 0x00001860UL,
+  /*    4230 */ 0x00000000UL,
+  /*    4234 */ 0x00000000UL,
+  0x0101423CUL, 0x00000112UL,
+  0x01034244UL, 0x00000014UL,
+  /*    4248 */ 0x00000000UL,
+  /*    424C */ 0x04000008UL,
+  0x01014268UL, 0x00000000UL,
+  0x01024280UL, 0x40090001UL,
+  /*    4284 */ 0x00100801UL,
+  0x01054298UL, 0x0200003FUL,
+  /*    429C */ 0x0000FFFFUL,
+  /*    42A0 */ 0x03E80000UL,
+  /*    42A4 */ 0x00000200UL,
+  /*    42A8 */ 0x00100000UL,
+  0x010142B4UL, 0x00C00000UL,
+  0x010A4330UL, 0x02400040UL,
+  /*    4334 */ 0x04AC0140UL,
+  /*    4338 */ 0x0100B050UL,
+  /*    433C */ 0x1F1F1F1FUL,
+  /*    4340 */ 0x1B1F1F1FUL,
+  /*    4344 */ 0x11131518UL,
+  /*    4348 */ 0x0C0D0E10UL,
+  /*    434C */ 0x2D0F285DUL,
+  /*    4350 */ 0x00000000UL,
+  /*    4354 */ 0x00000000UL,
+  0x01018010UL, 0x00000003UL,
+  0x01028038UL, 0x00104624UL,
+  /*    803C */ 0x00000001UL,
+  0x0103809CUL, 0x000240EBUL,
+  /*    80A0 */ 0x0000C0D5UL,
+  /*    80A4 */ 0x0000C0D5UL,
+  0x110180A8UL, 0x000001F0UL,
+  0x310180A8UL, 0x008D2205UL,
+  0x110180ACUL, 0x000001F0UL,
+  0x310180ACUL, 0x008D2205UL,
+  0x010280B0UL, 0x0100003FUL,
+  /*    80B4 */ 0x01000037UL,
+  0x0201009CUL, 0x04000C00UL,
+  0x020300D8UL, 0xAA400005UL,
+  /*    00DC */ 0x00000188UL,
+  /*    00E0 */ 0x000000C0UL,
+  0x120100ECUL, 0x00000FE0UL,
+  0x320100ECUL, 0x1151200CUL,
+  0x020100F0UL, 0x0000012BUL,
+  0x12010110UL, 0x000FFF00UL,
+  0x32010110UL, 0x31000002UL,
+  0x12010150UL, 0x0001C000UL,
+  0x32010150UL, 0x00A200C1UL,
+  0x02010174UL, 0x0C1FF169UL,
+  0x12010178UL, 0x001C0000UL,
+  0x32010178UL, 0x1FE00410UL,
+  0x12010180UL, 0x00000779UL,
+  0x02020184UL, 0x00000000UL,
+  /*    0188 */ 0x00000048UL,
+  0x03014FFCUL, (uint32_t) &phyInfo_1,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_40MHz_modemConfig[] = {
+  0x03014FFCUL, (uint32_t) &phyInfo_0,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x01280214UL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00004300UL,
+  0x0001C044UL, 0x0000022EUL,
+  0x0002C068UL, 0x0002B6D1UL,
+  /*    C06C */ 0x000006C0UL,
+  0x0001C0D0UL, 0x00000000UL,
+  0x0103404CUL, 0x0413F920UL,
+  /*    4050 */ 0x00620007UL,
+  /*    4054 */ 0x00007038UL,
+  0x01024060UL, 0x0F016800UL,
+  /*    4064 */ 0x4024B840UL,
+  0x01014080UL, 0x00006323UL,
+  0x0102408CUL, 0x60008000UL,
+  /*    4090 */ 0x00000ABEUL,
+  0x01014120UL, 0x00000B59UL,
+  0x01014138UL, 0xF00A2090UL,
+  0x0101415CUL, 0x00001E00UL,
+  0x010B416CUL, 0xC00C1400UL,
+  /*    4170 */ 0x28211A14UL,
+  /*    4174 */ 0x423B342EUL,
+  /*    4178 */ 0x55435049UL,
+  /*    417C */ 0x0CBA9876UL,
+  /*    4180 */ 0x00007323UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x64282117UL,
+  /*    418C */ 0x001A1714UL,
+  /*    4190 */ 0x7DC80420UL,
+  /*    4194 */ 0x093A20A1UL,
+  0x010141A8UL, 0x00000029UL,
+  0x0101423CUL, 0x00000000UL,
+  0x01024280UL, 0x00000000UL,
+  /*    4284 */ 0x00000081UL,
+  0x010342A0UL, 0x0000FFFFUL,
+  /*    42A4 */ 0x000003FFUL,
+  /*    42A8 */ 0x0000FFFFUL,
+  0x010142B4UL, 0x00000000UL,
+  0x01034330UL, 0x01200040UL,
+  /*    4334 */ 0x000000A0UL,
+  /*    4338 */ 0x01005008UL,
+  0x0101434CUL, 0x2F87C145UL,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_antdiv_40MHz_modemConfig[] = {
+  0x03014FFCUL, (uint32_t) &phyInfo_2,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x012801FEUL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00001400UL,
+  0x0001C044UL, 0x00000000UL,
+  0x0002C068UL, 0x0002C688UL,
+  /*    C06C */ 0x00000500UL,
+  0x0001C0D0UL, 0x000000A1UL,
+  0x0103404CUL, 0x0413FB20UL,
+  /*    4050 */ 0x0042C007UL,
+  /*    4054 */ 0x00000000UL,
+  0x01024060UL, 0x28000000UL,
+  /*    4064 */ 0x00028000UL,
+  0x01014080UL, 0x08A0015AUL,
+  0x0102408CUL, 0x60000000UL,
+  /*    4090 */ 0x00000000UL,
+  0x01014120UL, 0x00000000UL,
+  0x01014138UL, 0xF00A20BCUL,
+  0x0101415CUL, 0x00001003UL,
+  0x010B416CUL, 0x40000000UL,
+  /*    4170 */ 0x00000000UL,
+  /*    4174 */ 0x00000000UL,
+  /*    4178 */ 0x00000000UL,
+  /*    417C */ 0x00000000UL,
+  /*    4180 */ 0x00000000UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x00000000UL,
+  /*    418C */ 0x00000000UL,
+  /*    4190 */ 0x00000000UL,
+  /*    4194 */ 0x00000000UL,
+  0x010141A8UL, 0x00000000UL,
+  0x0101423CUL, 0x00000112UL,
+  0x01024280UL, 0x40090001UL,
+  /*    4284 */ 0x00100801UL,
+  0x010342A0UL, 0x03E80000UL,
+  /*    42A4 */ 0x00000200UL,
+  /*    42A8 */ 0x00100000UL,
+  0x010142B4UL, 0x00C00000UL,
+  0x01034330UL, 0x02400041UL,
+  /*    4334 */ 0x04AC0140UL,
+  /*    4338 */ 0x0100B050UL,
+  0x0101434CUL, 0x2D0F285DUL,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_40MHz_modemConfig[] = {
+  0x03014FFCUL, (uint32_t) &phyInfo_2,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x012801FEUL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00001400UL,
+  0x0001C044UL, 0x00000000UL,
+  0x0002C068UL, 0x0002C688UL,
+  /*    C06C */ 0x00000500UL,
+  0x0001C0D0UL, 0x000000A1UL,
+  0x0103404CUL, 0x0413FB20UL,
+  /*    4050 */ 0x0042C007UL,
+  /*    4054 */ 0x00000000UL,
+  0x01024060UL, 0x28000000UL,
+  /*    4064 */ 0x00028000UL,
+  0x01014080UL, 0x08A0015AUL,
+  0x0102408CUL, 0x60000000UL,
+  /*    4090 */ 0x00000000UL,
+  0x01014120UL, 0x00000000UL,
+  0x01014138UL, 0xF00A20BCUL,
+  0x0101415CUL, 0x00001003UL,
+  0x010B416CUL, 0x40000000UL,
+  /*    4170 */ 0x00000000UL,
+  /*    4174 */ 0x00000000UL,
+  /*    4178 */ 0x00000000UL,
+  /*    417C */ 0x00000000UL,
+  /*    4180 */ 0x00000000UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x00000000UL,
+  /*    418C */ 0x00000000UL,
+  /*    4190 */ 0x00000000UL,
+  /*    4194 */ 0x00000000UL,
+  0x010141A8UL, 0x00000000UL,
+  0x0101423CUL, 0x00000112UL,
+  0x01024280UL, 0x40090001UL,
+  /*    4284 */ 0x00100801UL,
+  0x010342A0UL, 0x03E80000UL,
+  /*    42A4 */ 0x00000200UL,
+  /*    42A8 */ 0x00100000UL,
+  0x010142B4UL, 0x00C00000UL,
+  0x01034330UL, 0x02400041UL,
+  /*    4334 */ 0x05B40140UL,
+  /*    4338 */ 0x0100B050UL,
+  0x0101434CUL, 0x2D0F285DUL,
+  0xFFFFFFFFUL,
+};
+
+const uint32_t sl_rail_ieee802154_phy_2G4Hz_fem_40MHz_modemConfig[] = {
+  0x03014FFCUL, (uint32_t) &phyInfo_0,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x01280214UL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00004300UL,
+  0x0001C044UL, 0x0000022EUL,
+  0x0002C068UL, 0x0002B6D1UL,
+  /*    C06C */ 0x000006C0UL,
+  0x0001C0D0UL, 0x00000000UL,
+  0x0103404CUL, 0x0413F920UL,
+  /*    4050 */ 0x00620007UL,
+  /*    4054 */ 0x00007038UL,
+  0x01024060UL, 0x0F016800UL,
+  /*    4064 */ 0x4024B840UL,
+  0x01014080UL, 0x00006323UL,
+  0x0102408CUL, 0x60008000UL,
+  /*    4090 */ 0x00000ABEUL,
+  0x01014120UL, 0x00000B59UL,
+  0x01014138UL, 0xF00A2090UL,
+  0x0101415CUL, 0x00001E00UL,
+  0x010B416CUL, 0xC00C1400UL,
+  /*    4170 */ 0x2E27201AUL,
+  /*    4174 */ 0x48413A34UL,
+  /*    4178 */ 0x6654564FUL,
+  /*    417C */ 0x0DCBA987UL,
+  /*    4180 */ 0x00007323UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x6A2E2717UL,
+  /*    418C */ 0x001A1714UL,
+  /*    4190 */ 0x7DC80420UL,
+  /*    4194 */ 0x093A20A1UL,
+  0x010141A8UL, 0x00000029UL,
+  0x0101423CUL, 0x00000000UL,
+  0x01024280UL, 0x00000000UL,
+  /*    4284 */ 0x00000081UL,
+  0x010342A0UL, 0x0000FFFFUL,
+  /*    42A4 */ 0x000003FFUL,
+  /*    42A8 */ 0x0000FFFFUL,
+  0x010142B4UL, 0x00000000UL,
+  0x01034330UL, 0x01200040UL,
+  /*    4334 */ 0x000000A0UL,
+  /*    4338 */ 0x01005008UL,
+  0x0101434CUL, 0x2F87C145UL,
+  0xFFFFFFFFUL,
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_40MHz_channels[] = {
+  {
+    .phyConfigDeltaAdd = sl_rail_ieee802154_phy_2G4Hz_40MHz_modemConfig,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_0,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_40MHz_channels[] = {
+  {
+    .phyConfigDeltaAdd = NULL,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_1,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_antdiv_40MHz_channels[] = {
+  {
+    .phyConfigDeltaAdd = sl_rail_ieee802154_phy_2G4Hz_antdiv_40MHz_modemConfig,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_2,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_40MHz_channels[] = {
+  {
+    .phyConfigDeltaAdd = sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_40MHz_modemConfig,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_3,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_fem_40MHz_channels[] = {
+  {
+    .phyConfigDeltaAdd = sl_rail_ieee802154_phy_2G4Hz_fem_40MHz_modemConfig,
+    .baseFrequency = 2405000000,
+    .channelSpacing = 5000000,
+    .physicalChannelOffset = 11,
+    .channelNumberStart = 11,
+    .channelNumberEnd = 26,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_4,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_40MHz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_40MHz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_40MHz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 40000000UL,
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_40MHz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_fast_switch_40MHz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_fast_switch_40MHz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 40000000UL,
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_antdiv_40MHz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_40MHz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_antdiv_40MHz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 40000000UL,
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_40MHz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_40MHz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_40MHz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 40000000UL,
+};
+
+const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_fem_40MHz_channelConfig = {
+  .phyConfigBase = sl_rail_ieee802154_phy_2G4Hz_40MHz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rail_ieee802154_phy_2G4Hz_fem_40MHz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 40000000UL,
+};

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ieee802154_config_40MHz.h

@@ -0,0 +1,74 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config Header  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __SL_RAIL_IEEE802154_CONFIG_40MHZ_H__
+#define __SL_RAIL_IEEE802154_CONFIG_40MHZ_H__
+
+#include <stdint.h>
+#include "rail_types.h"
+
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_40MHz_modemConfigBase[];
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_40MHz_modemConfigBase[];
+
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_40MHz_modemConfig[];
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_antdiv_40MHz_modemConfig[];
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_40MHz_modemConfig[];
+extern const uint32_t sl_rail_ieee802154_phy_2G4Hz_fem_40MHz_modemConfig[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_40MHZ_PHY_IEEE802154_2P4GHZ_PROD
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_40MHZ_PROFILE_IEEE802154OQPSK
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_40MHz_channels[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_FAST_SWITCH_40MHZ_PHY_IEEE802154_2P4GHZ_ANTDIV_FASTSWITCH
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_FAST_SWITCH_40MHZ_PROFILE_BASE
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_fast_switch_40MHz_channels[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_ANTDIV_40MHZ_PHY_IEEE802154_2P4GHZ_DIVERSITY_PROD
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_ANTDIV_40MHZ_PROFILE_IEEE802154OQPSK
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_antdiv_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_antdiv_40MHz_channels[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_ANTDIV_FEM_40MHZ_PHY_IEEE802154_2P4GHZ_DIVERSITY_FEM_PROD
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_ANTDIV_FEM_40MHZ_PROFILE_IEEE802154OQPSK
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_40MHz_channels[];
+
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_FEM_40MHZ_PHY_IEEE802154_2P4GHZ_FEM_PROD
+#define RAIL0_SL_RAIL_IEEE802154_PHY_2G4HZ_FEM_40MHZ_PROFILE_IEEE802154OQPSK
+extern const RAIL_ChannelConfig_t sl_rail_ieee802154_phy_2G4Hz_fem_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rail_ieee802154_phy_2G4Hz_fem_40MHz_channels[];
+
+#endif // __SL_RAIL_IEEE802154_CONFIG_40MHZ_H__

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_rfsense_ook_config_38M4Hz.c

@@ -0,0 +1,344 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#include "em_device.h"
+#include "sl_rail_rfsense_ook_config_38M4Hz.h"
+
+static const uint8_t irCalConfig[] = {
+  25, 63, 1, 6, 4, 16, 1, 0, 0, 1, 0, 2, 2, 0, 0, 0, 0, 5, 0, 1, 1, 0, 0, 0, 0, 0
+};
+
+static const int32_t timingConfig[] = {
+  1103579, 1103579, 500000, 0
+};
+
+static const uint8_t hfxoRetimingConfigEntries[] = {
+  2, 0, 0, 0, 0x00, 0xf0, 0x49, 0x02, 6, 20, 0, 0, 0x00, 0xe0, 0x93, 0x04, 5, 56, 0, 0, 0xa0, 0x08, 0, 0, 0, 0, 0x58, 0x09, 1, 4, 7, 6, 0x10, 0x0a, 1, 4, 7, 7, 0xc8, 0x0a, 0, 4, 8, 7, 0x80, 0x0b, 0, 4, 8, 8, 0x38, 0x0c, 0, 4, 9, 8, 0x61, 0x08, 0, 0, 0, 0, 0x68, 0x08, 0, 0, 0, 0, 0xc7, 0x09, 1, 4, 4, 3, 0x2c, 0x0b, 1, 4, 4, 4, 0x92, 0x0c, 1, 4, 5, 4
+};
+
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+static const uint8_t stackInfo_0[2] = { 0x00, 0x00 };
+#endif // RADIO_CONFIG_ENABLE_STACK_INFO
+
+static RAIL_ChannelConfigEntryAttr_t channelConfigEntryAttr = {
+#if RAIL_SUPPORTS_OFDM_PA
+  {
+#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+    { 0xFFFFFFFFUL, 0xFFFFFFFFUL, },
+#else
+    { 0xFFFFFFFFUL },
+#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+    { 0xFFFFFFFFUL, 0xFFFFFFFFUL }
+  }
+#else // RAIL_SUPPORTS_OFDM_PA
+#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+  { 0xFFFFFFFFUL, 0xFFFFFFFFUL, },
+#else
+  { 0xFFFFFFFFUL },
+#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+#endif // RAIL_SUPPORTS_OFDM_PA
+};
+
+static const uint32_t phyInfo[] = {
+  18UL,
+  0x00000000UL, // 0.0
+  (uint32_t) NULL,
+  (uint32_t) irCalConfig,
+  (uint32_t) timingConfig,
+  0x00000000UL,
+  0UL,
+  22950000UL,
+  1000UL,
+  0x00F20201UL,
+  0x03100444UL,
+  (uint32_t) NULL,
+  (uint32_t) hfxoRetimingConfigEntries,
+  (uint32_t) NULL,
+  0UL,
+  0UL,
+  2000UL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+};
+
+const uint32_t sl_rfsense_ook_1kbps_38M4Hz_modemConfigBase[] = {
+  0x0002400CUL, 0x00000000UL,
+  /*    4010 */ 0x00004000UL,
+  0x00024020UL, 0x0000000FUL,
+  /*    4024 */ 0x00000000UL,
+  0x00074030UL, 0x00000000UL,
+  /*    4034 */ 0x00000000UL,
+  /*    4038 */ 0x00000000UL,
+  /*    403C */ 0x00000000UL,
+  /*    4040 */ 0x00000000UL,
+  /*    4044 */ 0x00004000UL,
+  /*    4048 */ 0x03000700UL,
+  0x00014050UL, 0x00000000UL,
+  0x0002405CUL, 0x00000000UL,
+  /*    4060 */ 0x00000000UL,
+  0x000140A8UL, 0x00000007UL,
+  0x000440BCUL, 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  0x00044108UL, 0x000040FFUL,
+  /*    410C */ 0x00000000UL,
+  /*    4110 */ 0x000041FFUL,
+  /*    4114 */ 0x00000000UL,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x01280100UL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00001300UL,
+  0x0008C028UL, 0x03B380ECUL,
+  /*    C02C */ 0x51407543UL,
+  /*    C030 */ 0xF8000FA0UL,
+  /*    C034 */ 0x00004000UL,
+  /*    C038 */ 0x0007AAA8UL,
+  /*    C03C */ 0x00000000UL,
+  /*    C040 */ 0x00000000UL,
+  /*    C044 */ 0x00000000UL,
+  0x0010C054UL, 0x00302151UL,
+  /*    C058 */ 0xE6DF00F0UL,
+  /*    C05C */ 0x00005355UL,
+  /*    C060 */ 0xD8CCB484UL,
+  /*    C064 */ 0x000000DFUL,
+  /*    C068 */ 0x0002C688UL,
+  /*    C06C */ 0x00000740UL,
+  /*    C070 */ 0x000010BAUL,
+  /*    C074 */ 0x00200400UL,
+  /*    C078 */ 0x00801804UL,
+  /*    C07C */ 0x01203C0BUL,
+  /*    C080 */ 0x02107C18UL,
+  /*    C084 */ 0x06E0FC2FUL,
+  /*    C088 */ 0x0000007FUL,
+  /*    C08C */ 0x00000000UL,
+  /*    C090 */ 0x00000000UL,
+  0x0005C0A8UL, 0x15724BBDUL,
+  /*    C0AC */ 0x0518A311UL,
+  /*    C0B0 */ 0x76543210UL,
+  /*    C0B4 */ 0x00000A98UL,
+  /*    C0B8 */ 0x00000000UL,
+  0x0004C0CCUL, 0x00000001UL,
+  /*    C0D0 */ 0x00000000UL,
+  /*    C0D4 */ 0x000A0001UL,
+  /*    C0D8 */ 0x00280001UL,
+  0x01010008UL, 0x00000744UL,
+  0x01010018UL, 0x00000000UL,
+  0x01010020UL, 0x0000A001UL,
+  0x01254040UL, 0x00000000UL,
+  /*    4044 */ 0x00000000UL,
+  /*    4048 */ 0x00000010UL,
+  /*    404C */ 0x00000191UL,
+  /*    4050 */ 0x0602C001UL,
+  /*    4054 */ 0x00003000UL,
+  /*    4058 */ 0x00000000UL,
+  /*    405C */ 0x03000000UL,
+  /*    4060 */ 0x20000000UL,
+  /*    4064 */ 0x00000000UL,
+  /*    4068 */ 0x00067080UL,
+  /*    406C */ 0x00000841UL,
+  /*    4070 */ 0x000407F0UL,
+  /*    4074 */ 0x00000010UL,
+  /*    4078 */ 0x00000000UL,
+  /*    407C */ 0x00000000UL,
+  /*    4080 */ 0x08AC0000UL,
+  /*    4084 */ 0x00000000UL,
+  /*    4088 */ 0x000F031DUL,
+  /*    408C */ 0x60000000UL,
+  /*    4090 */ 0x00000000UL,
+  /*    4094 */ 0x00000000UL,
+  /*    4098 */ 0x00000000UL,
+  /*    409C */ 0x00000000UL,
+  /*    40A0 */ 0x00000000UL,
+  /*    40A4 */ 0x00000000UL,
+  /*    40A8 */ 0x00000000UL,
+  /*    40AC */ 0x00000000UL,
+  /*    40B0 */ 0x00000000UL,
+  /*    40B4 */ 0x00000000UL,
+  /*    40B8 */ 0x00000000UL,
+  /*    40BC */ 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  /*    40CC */ 0x00000000UL,
+  /*    40D0 */ 0x00000000UL,
+  0x010140E0UL, 0x00000200UL,
+  0x01024110UL, 0x00051E33UL,
+  /*    4114 */ 0x00000000UL,
+  0x010E411CUL, 0x8B561000UL,
+  /*    4120 */ 0x00000000UL,
+  /*    4124 */ 0x078304FFUL,
+  /*    4128 */ 0x3AC81388UL,
+  /*    412C */ 0x0C6606FFUL,
+  /*    4130 */ 0x078304FFUL,
+  /*    4134 */ 0x03FF1388UL,
+  /*    4138 */ 0xF00A20BCUL,
+  /*    413C */ 0x00503358UL,
+  /*    4140 */ 0x00000000UL,
+  /*    4144 */ 0x123556B7UL,
+  /*    4148 */ 0x50000000UL,
+  /*    414C */ 0x00003B80UL,
+  /*    4150 */ 0x00000000UL,
+  0x01024158UL, 0x00000000UL,
+  /*    415C */ 0x00000000UL,
+  0x010D4164UL, 0x0000010CUL,
+  /*    4168 */ 0x00FA53E8UL,
+  /*    416C */ 0x40000000UL,
+  /*    4170 */ 0x00000000UL,
+  /*    4174 */ 0x00000000UL,
+  /*    4178 */ 0x00000000UL,
+  /*    417C */ 0x00000000UL,
+  /*    4180 */ 0x00000000UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x00000000UL,
+  /*    418C */ 0x00000000UL,
+  /*    4190 */ 0x00000000UL,
+  /*    4194 */ 0x00000000UL,
+  0x010241A4UL, 0x00000000UL,
+  /*    41A8 */ 0x00000000UL,
+  0x010241B0UL, 0x00000000UL,
+  /*    41B4 */ 0x00200000UL,
+  0x010341BCUL, 0x00000000UL,
+  /*    41C0 */ 0x003C0000UL,
+  /*    41C4 */ 0x0006AAAAUL,
+  0x010341D0UL, 0x00000000UL,
+  /*    41D4 */ 0x00000010UL,
+  /*    41D8 */ 0x00020000UL,
+  0x011641E0UL, 0x00000000UL,
+  /*    41E4 */ 0x0BFFE7E6UL,
+  /*    41E8 */ 0x000AA1CDUL,
+  /*    41EC */ 0x006A06BDUL,
+  /*    41F0 */ 0x004DB05EUL,
+  /*    41F4 */ 0x0E42027DUL,
+  /*    41F8 */ 0x0222B6A5UL,
+  /*    41FC */ 0x34B225FFUL,
+  /*    4200 */ 0x0BFFE7E6UL,
+  /*    4204 */ 0x000AA1CDUL,
+  /*    4208 */ 0x006A06BDUL,
+  /*    420C */ 0x004DB05EUL,
+  /*    4210 */ 0x0E42027DUL,
+  /*    4214 */ 0x0222B6A5UL,
+  /*    4218 */ 0x34B225FFUL,
+  /*    421C */ 0x00000000UL,
+  /*    4220 */ 0x00000000UL,
+  /*    4224 */ 0x00000005UL,
+  /*    4228 */ 0x00000000UL,
+  /*    422C */ 0x40001860UL,
+  /*    4230 */ 0x00000000UL,
+  /*    4234 */ 0x00000000UL,
+  0x0101423CUL, 0x00000000UL,
+  0x01034244UL, 0x00000014UL,
+  /*    4248 */ 0x00000000UL,
+  /*    424C */ 0x04000008UL,
+  0x01014268UL, 0x00000000UL,
+  0x01024280UL, 0x00000000UL,
+  /*    4284 */ 0x00000081UL,
+  0x01054298UL, 0x0200003FUL,
+  /*    429C */ 0x0000FFFFUL,
+  /*    42A0 */ 0x0000FFFFUL,
+  /*    42A4 */ 0x000003FFUL,
+  /*    42A8 */ 0x0000FFFFUL,
+  0x010142B4UL, 0x00000000UL,
+  0x010A4330UL, 0x01200040UL,
+  /*    4334 */ 0x000000A0UL,
+  /*    4338 */ 0x01005008UL,
+  /*    433C */ 0x1F1F1F1FUL,
+  /*    4340 */ 0x1B1F1F1FUL,
+  /*    4344 */ 0x11131518UL,
+  /*    4348 */ 0x0C0D0E10UL,
+  /*    434C */ 0x2F87C145UL,
+  /*    4350 */ 0x00000000UL,
+  /*    4354 */ 0x00000000UL,
+  0x01018010UL, 0x00000003UL,
+  0x01028038UL, 0x00100444UL,
+  /*    803C */ 0x00000001UL,
+  0x0103809CUL, 0x00000000UL,
+  /*    80A0 */ 0x00037870UL,
+  /*    80A4 */ 0x000000D0UL,
+  0x110180A8UL, 0x000001F0UL,
+  0x310180A8UL, 0x01CB4205UL,
+  0x110180ACUL, 0x000001F0UL,
+  0x310180ACUL, 0x00FD3E05UL,
+  0x010280B0UL, 0x02000300UL,
+  /*    80B4 */ 0x01000037UL,
+  0x0201009CUL, 0x04000C00UL,
+  0x020300D8UL, 0xAA400005UL,
+  /*    00DC */ 0x00000188UL,
+  /*    00E0 */ 0x000000C0UL,
+  0x120100ECUL, 0x00000FE0UL,
+  0x320100ECUL, 0x5151200CUL,
+  0x020100F0UL, 0x0000012BUL,
+  0x12010110UL, 0x000FFF00UL,
+  0x32010110UL, 0x31000002UL,
+  0x12010150UL, 0x0001C000UL,
+  0x32010150UL, 0x00A200C1UL,
+  0x02010174UL, 0x0C1B8169UL,
+  0x12010178UL, 0x001C0000UL,
+  0x32010178UL, 0xCFE00410UL,
+  0x12010180UL, 0x00000779UL,
+  0x32010180UL, 0x00000002UL,
+  0x02020184UL, 0x00001000UL,
+  /*    0188 */ 0x00000050UL,
+  0x03014FFCUL, (uint32_t) &phyInfo,
+  0xFFFFFFFFUL,
+};
+
+const RAIL_ChannelConfigEntry_t sl_rfsense_ook_1kbps_38M4Hz_channels[] = {
+  {
+    .phyConfigDeltaAdd = NULL,
+    .baseFrequency = 2450000000,
+    .channelSpacing = 1000000,
+    .physicalChannelOffset = 0,
+    .channelNumberStart = 0,
+    .channelNumberEnd = 0,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_0,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfig_t sl_rfsense_ook_1kbps_38M4Hz_channelConfig = {
+  .phyConfigBase = sl_rfsense_ook_1kbps_38M4Hz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rfsense_ook_1kbps_38M4Hz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 38400000UL,
+};

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_rfsense_ook_config_38M4Hz.h

@@ -0,0 +1,48 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config Header  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __SL_RAIL_RFSENSE_OOK_CONFIG_38M4HZ_H__
+#define __SL_RAIL_RFSENSE_OOK_CONFIG_38M4HZ_H__
+
+#include <stdint.h>
+#include "rail_types.h"
+
+extern const uint32_t sl_rfsense_ook_1kbps_38M4Hz_modemConfigBase[];
+
+#define RAIL0_SL_RFSENSE_OOK_1KBPS_38M4HZ_PHY_RFSENSE_2450M_OOK_1KBPS
+#define RAIL0_SL_RFSENSE_OOK_1KBPS_38M4HZ_PROFILE_BASE
+extern const RAIL_ChannelConfig_t sl_rfsense_ook_1kbps_38M4Hz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rfsense_ook_1kbps_38M4Hz_channels[];
+
+#endif // __SL_RAIL_RFSENSE_OOK_CONFIG_38M4HZ_H__

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_rfsense_ook_config_39MHz.c

@@ -0,0 +1,344 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#include "em_device.h"
+#include "sl_rail_rfsense_ook_config_39MHz.h"
+
+static const uint8_t irCalConfig[] = {
+  25, 63, 1, 6, 4, 16, 1, 0, 0, 1, 0, 2, 2, 0, 0, 0, 0, 5, 0, 1, 1, 0, 0, 0, 0, 0
+};
+
+static const int32_t timingConfig[] = {
+  1103579, 1103579, 500000, 0
+};
+
+static const uint8_t hfxoRetimingConfigEntries[] = {
+  2, 0, 0, 0, 0xc0, 0x17, 0x53, 0x02, 6, 20, 0, 0, 0x80, 0x2f, 0xa6, 0x04, 5, 56, 0, 0, 0xa0, 0x08, 0, 0, 0, 0, 0x58, 0x09, 1, 4, 7, 6, 0x10, 0x0a, 1, 4, 7, 7, 0xc8, 0x0a, 0, 4, 8, 7, 0x80, 0x0b, 0, 4, 8, 8, 0x38, 0x0c, 0, 4, 9, 8, 0x61, 0x08, 0, 0, 0, 0, 0x8a, 0x08, 0, 0, 0, 0, 0xc7, 0x09, 1, 4, 4, 3, 0x2c, 0x0b, 1, 4, 4, 4, 0x92, 0x0c, 1, 4, 5, 4
+};
+
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+static const uint8_t stackInfo_0[2] = { 0x00, 0x00 };
+#endif // RADIO_CONFIG_ENABLE_STACK_INFO
+
+static RAIL_ChannelConfigEntryAttr_t channelConfigEntryAttr = {
+#if RAIL_SUPPORTS_OFDM_PA
+  {
+#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+    { 0xFFFFFFFFUL, 0xFFFFFFFFUL, },
+#else
+    { 0xFFFFFFFFUL },
+#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+    { 0xFFFFFFFFUL, 0xFFFFFFFFUL }
+  }
+#else // RAIL_SUPPORTS_OFDM_PA
+#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+  { 0xFFFFFFFFUL, 0xFFFFFFFFUL, },
+#else
+  { 0xFFFFFFFFUL },
+#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+#endif // RAIL_SUPPORTS_OFDM_PA
+};
+
+static const uint32_t phyInfo[] = {
+  18UL,
+  0x00000000UL, // 0.0
+  (uint32_t) NULL,
+  (uint32_t) irCalConfig,
+  (uint32_t) timingConfig,
+  0x00000000UL,
+  0UL,
+  22950000UL,
+  1000UL,
+  0x00F20201UL,
+  0x03100433UL,
+  (uint32_t) NULL,
+  (uint32_t) hfxoRetimingConfigEntries,
+  (uint32_t) NULL,
+  0UL,
+  0UL,
+  2000UL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+};
+
+const uint32_t sl_rfsense_ook_1kbps_39MHz_modemConfigBase[] = {
+  0x0002400CUL, 0x00000000UL,
+  /*    4010 */ 0x00004000UL,
+  0x00024020UL, 0x0000000FUL,
+  /*    4024 */ 0x00000000UL,
+  0x00074030UL, 0x00000000UL,
+  /*    4034 */ 0x00000000UL,
+  /*    4038 */ 0x00000000UL,
+  /*    403C */ 0x00000000UL,
+  /*    4040 */ 0x00000000UL,
+  /*    4044 */ 0x00004000UL,
+  /*    4048 */ 0x03000700UL,
+  0x00014050UL, 0x00000000UL,
+  0x0002405CUL, 0x00000000UL,
+  /*    4060 */ 0x00000000UL,
+  0x000140A8UL, 0x00000007UL,
+  0x000440BCUL, 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  0x00044108UL, 0x000040FFUL,
+  /*    410C */ 0x00000000UL,
+  /*    4110 */ 0x000041FFUL,
+  /*    4114 */ 0x00000000UL,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x01280100UL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00001300UL,
+  0x0008C028UL, 0x03B380ECUL,
+  /*    C02C */ 0x51407543UL,
+  /*    C030 */ 0xF8000FA0UL,
+  /*    C034 */ 0x00004000UL,
+  /*    C038 */ 0x0007AAA8UL,
+  /*    C03C */ 0x00000000UL,
+  /*    C040 */ 0x00000000UL,
+  /*    C044 */ 0x00000000UL,
+  0x0010C054UL, 0x00302151UL,
+  /*    C058 */ 0xE6E300F4UL,
+  /*    C05C */ 0x000054A3UL,
+  /*    C060 */ 0xDCCFB786UL,
+  /*    C064 */ 0x000000E3UL,
+  /*    C068 */ 0x0002C688UL,
+  /*    C06C */ 0x00000740UL,
+  /*    C070 */ 0x000010BAUL,
+  /*    C074 */ 0x00200400UL,
+  /*    C078 */ 0x00801804UL,
+  /*    C07C */ 0x01203C0BUL,
+  /*    C080 */ 0x02107C18UL,
+  /*    C084 */ 0x06E0FC2FUL,
+  /*    C088 */ 0x0000007FUL,
+  /*    C08C */ 0x00000000UL,
+  /*    C090 */ 0x00000000UL,
+  0x0005C0A8UL, 0x15724BBDUL,
+  /*    C0AC */ 0x0518A311UL,
+  /*    C0B0 */ 0x76543210UL,
+  /*    C0B4 */ 0x00000A98UL,
+  /*    C0B8 */ 0x00000000UL,
+  0x0004C0CCUL, 0x00000001UL,
+  /*    C0D0 */ 0x00000000UL,
+  /*    C0D4 */ 0x000A0001UL,
+  /*    C0D8 */ 0x00280001UL,
+  0x01010008UL, 0x00000744UL,
+  0x01010018UL, 0x00000000UL,
+  0x01010020UL, 0x0000A001UL,
+  0x01254040UL, 0x00000000UL,
+  /*    4044 */ 0x00000000UL,
+  /*    4048 */ 0x00000010UL,
+  /*    404C */ 0x00000191UL,
+  /*    4050 */ 0x0602C001UL,
+  /*    4054 */ 0x00003000UL,
+  /*    4058 */ 0x00000000UL,
+  /*    405C */ 0x03000000UL,
+  /*    4060 */ 0x20000000UL,
+  /*    4064 */ 0x00000000UL,
+  /*    4068 */ 0x00067242UL,
+  /*    406C */ 0x00000841UL,
+  /*    4070 */ 0x000407F0UL,
+  /*    4074 */ 0x00000010UL,
+  /*    4078 */ 0x00000000UL,
+  /*    407C */ 0x00000000UL,
+  /*    4080 */ 0x08AC0000UL,
+  /*    4084 */ 0x00000000UL,
+  /*    4088 */ 0x000F031CUL,
+  /*    408C */ 0x60000000UL,
+  /*    4090 */ 0x00000000UL,
+  /*    4094 */ 0x00000000UL,
+  /*    4098 */ 0x00000000UL,
+  /*    409C */ 0x00000000UL,
+  /*    40A0 */ 0x00000000UL,
+  /*    40A4 */ 0x00000000UL,
+  /*    40A8 */ 0x00000000UL,
+  /*    40AC */ 0x00000000UL,
+  /*    40B0 */ 0x00000000UL,
+  /*    40B4 */ 0x00000000UL,
+  /*    40B8 */ 0x00000000UL,
+  /*    40BC */ 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  /*    40CC */ 0x00000000UL,
+  /*    40D0 */ 0x00000000UL,
+  0x010140E0UL, 0x00000200UL,
+  0x01024110UL, 0x00051E33UL,
+  /*    4114 */ 0x00000000UL,
+  0x010E411CUL, 0x8B561000UL,
+  /*    4120 */ 0x00000000UL,
+  /*    4124 */ 0x078304FFUL,
+  /*    4128 */ 0x3AC81388UL,
+  /*    412C */ 0x0C6606FFUL,
+  /*    4130 */ 0x078304FFUL,
+  /*    4134 */ 0x03FF1388UL,
+  /*    4138 */ 0xF00A20BCUL,
+  /*    413C */ 0x00503356UL,
+  /*    4140 */ 0x00000000UL,
+  /*    4144 */ 0x123556B7UL,
+  /*    4148 */ 0x50000000UL,
+  /*    414C */ 0x00003B80UL,
+  /*    4150 */ 0x00000000UL,
+  0x01024158UL, 0x00000000UL,
+  /*    415C */ 0x00000000UL,
+  0x010D4164UL, 0x0000010CUL,
+  /*    4168 */ 0x00FA53E8UL,
+  /*    416C */ 0x40000000UL,
+  /*    4170 */ 0x00000000UL,
+  /*    4174 */ 0x00000000UL,
+  /*    4178 */ 0x00000000UL,
+  /*    417C */ 0x00000000UL,
+  /*    4180 */ 0x00000000UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x00000000UL,
+  /*    418C */ 0x00000000UL,
+  /*    4190 */ 0x00000000UL,
+  /*    4194 */ 0x00000000UL,
+  0x010241A4UL, 0x00000000UL,
+  /*    41A8 */ 0x00000000UL,
+  0x010241B0UL, 0x00000000UL,
+  /*    41B4 */ 0x00200000UL,
+  0x010341BCUL, 0x00000000UL,
+  /*    41C0 */ 0x003C0000UL,
+  /*    41C4 */ 0x00069069UL,
+  0x010341D0UL, 0x00000000UL,
+  /*    41D4 */ 0x00000010UL,
+  /*    41D8 */ 0x00020000UL,
+  0x011641E0UL, 0x00000000UL,
+  /*    41E4 */ 0x0BFFE7E6UL,
+  /*    41E8 */ 0x000AA1CDUL,
+  /*    41EC */ 0x006A06BDUL,
+  /*    41F0 */ 0x004DB05EUL,
+  /*    41F4 */ 0x0E42027DUL,
+  /*    41F8 */ 0x0222B6A5UL,
+  /*    41FC */ 0x34B225FFUL,
+  /*    4200 */ 0x0BFFE7E6UL,
+  /*    4204 */ 0x000AA1CDUL,
+  /*    4208 */ 0x006A06BDUL,
+  /*    420C */ 0x004DB05EUL,
+  /*    4210 */ 0x0E42027DUL,
+  /*    4214 */ 0x0222B6A5UL,
+  /*    4218 */ 0x34B225FFUL,
+  /*    421C */ 0x00000000UL,
+  /*    4220 */ 0x00000000UL,
+  /*    4224 */ 0x00000005UL,
+  /*    4228 */ 0x00000000UL,
+  /*    422C */ 0x40001860UL,
+  /*    4230 */ 0x00000000UL,
+  /*    4234 */ 0x00000000UL,
+  0x0101423CUL, 0x00000000UL,
+  0x01034244UL, 0x00000014UL,
+  /*    4248 */ 0x00000000UL,
+  /*    424C */ 0x04000008UL,
+  0x01014268UL, 0x00000000UL,
+  0x01024280UL, 0x00000000UL,
+  /*    4284 */ 0x00000081UL,
+  0x01054298UL, 0x0200003FUL,
+  /*    429C */ 0x0000FFFFUL,
+  /*    42A0 */ 0x0000FFFFUL,
+  /*    42A4 */ 0x000003FFUL,
+  /*    42A8 */ 0x0000FFFFUL,
+  0x010142B4UL, 0x00000000UL,
+  0x010A4330UL, 0x01200040UL,
+  /*    4334 */ 0x000000A0UL,
+  /*    4338 */ 0x01005008UL,
+  /*    433C */ 0x1F1F1F1FUL,
+  /*    4340 */ 0x1B1F1F1FUL,
+  /*    4344 */ 0x11131518UL,
+  /*    4348 */ 0x0C0D0E10UL,
+  /*    434C */ 0x2F87C145UL,
+  /*    4350 */ 0x00000000UL,
+  /*    4354 */ 0x00000000UL,
+  0x01018010UL, 0x00000003UL,
+  0x01028038UL, 0x00100433UL,
+  /*    803C */ 0x00000001UL,
+  0x0103809CUL, 0x00000000UL,
+  /*    80A0 */ 0x00037870UL,
+  /*    80A4 */ 0x000000D0UL,
+  0x110180A8UL, 0x000001F0UL,
+  0x310180A8UL, 0x01CB4205UL,
+  0x110180ACUL, 0x000001F0UL,
+  0x310180ACUL, 0x00FD3E05UL,
+  0x010280B0UL, 0x02000300UL,
+  /*    80B4 */ 0x01000037UL,
+  0x0201009CUL, 0x04000C00UL,
+  0x020300D8UL, 0xAA400005UL,
+  /*    00DC */ 0x00000188UL,
+  /*    00E0 */ 0x000000C0UL,
+  0x120100ECUL, 0x00000FE0UL,
+  0x320100ECUL, 0x5151200CUL,
+  0x020100F0UL, 0x0000012BUL,
+  0x12010110UL, 0x000FFF00UL,
+  0x32010110UL, 0x31000002UL,
+  0x12010150UL, 0x0001C000UL,
+  0x32010150UL, 0x00A200C1UL,
+  0x02010174UL, 0x0C1B8169UL,
+  0x12010178UL, 0x001C0000UL,
+  0x32010178UL, 0xCFE00410UL,
+  0x12010180UL, 0x00000779UL,
+  0x32010180UL, 0x00000002UL,
+  0x02020184UL, 0x00001000UL,
+  /*    0188 */ 0x00000050UL,
+  0x03014FFCUL, (uint32_t) &phyInfo,
+  0xFFFFFFFFUL,
+};
+
+const RAIL_ChannelConfigEntry_t sl_rfsense_ook_1kbps_39MHz_channels[] = {
+  {
+    .phyConfigDeltaAdd = NULL,
+    .baseFrequency = 2450000000,
+    .channelSpacing = 1000000,
+    .physicalChannelOffset = 0,
+    .channelNumberStart = 0,
+    .channelNumberEnd = 0,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_0,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfig_t sl_rfsense_ook_1kbps_39MHz_channelConfig = {
+  .phyConfigBase = sl_rfsense_ook_1kbps_39MHz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rfsense_ook_1kbps_39MHz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 39000000UL,
+};

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_rfsense_ook_config_39MHz.h

@@ -0,0 +1,48 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config Header  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __SL_RAIL_RFSENSE_OOK_CONFIG_39MHZ_H__
+#define __SL_RAIL_RFSENSE_OOK_CONFIG_39MHZ_H__
+
+#include <stdint.h>
+#include "rail_types.h"
+
+extern const uint32_t sl_rfsense_ook_1kbps_39MHz_modemConfigBase[];
+
+#define RAIL0_SL_RFSENSE_OOK_1KBPS_39MHZ_PHY_RFSENSE_2450M_OOK_1KBPS
+#define RAIL0_SL_RFSENSE_OOK_1KBPS_39MHZ_PROFILE_BASE
+extern const RAIL_ChannelConfig_t sl_rfsense_ook_1kbps_39MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rfsense_ook_1kbps_39MHz_channels[];
+
+#endif // __SL_RAIL_RFSENSE_OOK_CONFIG_39MHZ_H__

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_rfsense_ook_config_40MHz.c

@@ -0,0 +1,344 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#include "em_device.h"
+#include "sl_rail_rfsense_ook_config_40MHz.h"
+
+static const uint8_t irCalConfig[] = {
+  25, 63, 1, 6, 4, 16, 1, 0, 0, 1, 0, 2, 2, 0, 0, 0, 0, 5, 0, 1, 1, 0, 0, 0, 0, 0
+};
+
+static const int32_t timingConfig[] = {
+  1103579, 1103579, 500000, 0
+};
+
+static const uint8_t hfxoRetimingConfigEntries[] = {
+  2, 0, 0, 0, 0x00, 0x5a, 0x62, 0x02, 6, 20, 0, 0, 0x00, 0xb4, 0xc4, 0x04, 7, 56, 0, 0, 0xa0, 0x08, 0, 0, 0, 0, 0x58, 0x09, 1, 4, 7, 6, 0x10, 0x0a, 1, 4, 7, 7, 0xc8, 0x0a, 0, 4, 8, 7, 0x80, 0x0b, 0, 4, 8, 8, 0x38, 0x0c, 0, 4, 9, 8, 0x61, 0x08, 0, 0, 0, 0, 0xc2, 0x08, 0, 0, 0, 0, 0xc7, 0x09, 1, 4, 4, 3, 0xc4, 0x09, 0, 0, 0, 0, 0x2c, 0x0b, 1, 4, 4, 4, 0xc4, 0x09, 0, 0, 0, 0, 0x92, 0x0c, 1, 4, 5, 4
+};
+
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+static const uint8_t stackInfo_0[2] = { 0x00, 0x00 };
+#endif // RADIO_CONFIG_ENABLE_STACK_INFO
+
+static RAIL_ChannelConfigEntryAttr_t channelConfigEntryAttr = {
+#if RAIL_SUPPORTS_OFDM_PA
+  {
+#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+    { 0xFFFFFFFFUL, 0xFFFFFFFFUL, },
+#else
+    { 0xFFFFFFFFUL },
+#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+    { 0xFFFFFFFFUL, 0xFFFFFFFFUL }
+  }
+#else // RAIL_SUPPORTS_OFDM_PA
+#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+  { 0xFFFFFFFFUL, 0xFFFFFFFFUL, },
+#else
+  { 0xFFFFFFFFUL },
+#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+#endif // RAIL_SUPPORTS_OFDM_PA
+};
+
+static const uint32_t phyInfo[] = {
+  18UL,
+  0x00000000UL, // 0.0
+  (uint32_t) NULL,
+  (uint32_t) irCalConfig,
+  (uint32_t) timingConfig,
+  0x00000000UL,
+  0UL,
+  22950000UL,
+  1000UL,
+  0x00F20201UL,
+  0x03100418UL,
+  (uint32_t) NULL,
+  (uint32_t) hfxoRetimingConfigEntries,
+  (uint32_t) NULL,
+  0UL,
+  0UL,
+  2000UL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+  (uint32_t) NULL,
+};
+
+const uint32_t sl_rfsense_ook_1kbps_40MHz_modemConfigBase[] = {
+  0x0002400CUL, 0x00000000UL,
+  /*    4010 */ 0x00004000UL,
+  0x00024020UL, 0x0000000FUL,
+  /*    4024 */ 0x00000000UL,
+  0x00074030UL, 0x00000000UL,
+  /*    4034 */ 0x00000000UL,
+  /*    4038 */ 0x00000000UL,
+  /*    403C */ 0x00000000UL,
+  /*    4040 */ 0x00000000UL,
+  /*    4044 */ 0x00004000UL,
+  /*    4048 */ 0x03000700UL,
+  0x00014050UL, 0x00000000UL,
+  0x0002405CUL, 0x00000000UL,
+  /*    4060 */ 0x00000000UL,
+  0x000140A8UL, 0x00000007UL,
+  0x000440BCUL, 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  0x00044108UL, 0x000040FFUL,
+  /*    410C */ 0x00000000UL,
+  /*    4110 */ 0x000041FFUL,
+  /*    4114 */ 0x00000000UL,
+  0x1001C020UL, 0x0007F800UL,
+  0x3001C020UL, 0x01280100UL,
+  0x1001C024UL, 0x000000FFUL,
+  0x3001C024UL, 0x00001300UL,
+  0x0008C028UL, 0x03B380ECUL,
+  /*    C02C */ 0x51407543UL,
+  /*    C030 */ 0xF8000FA0UL,
+  /*    C034 */ 0x00004000UL,
+  /*    C038 */ 0x0007AAA8UL,
+  /*    C03C */ 0x00000000UL,
+  /*    C040 */ 0x00000000UL,
+  /*    C044 */ 0x00000000UL,
+  0x0010C054UL, 0x00302151UL,
+  /*    C058 */ 0xE6E900FAUL,
+  /*    C05C */ 0x000056CEUL,
+  /*    C060 */ 0xE1D5BC8AUL,
+  /*    C064 */ 0x000000E9UL,
+  /*    C068 */ 0x0002C688UL,
+  /*    C06C */ 0x00000740UL,
+  /*    C070 */ 0x000010BAUL,
+  /*    C074 */ 0x00200400UL,
+  /*    C078 */ 0x00801804UL,
+  /*    C07C */ 0x01203C0BUL,
+  /*    C080 */ 0x02107C18UL,
+  /*    C084 */ 0x06E0FC2FUL,
+  /*    C088 */ 0x0000007FUL,
+  /*    C08C */ 0x00000000UL,
+  /*    C090 */ 0x00000000UL,
+  0x0005C0A8UL, 0x15724BBDUL,
+  /*    C0AC */ 0x0518A311UL,
+  /*    C0B0 */ 0x76543210UL,
+  /*    C0B4 */ 0x00000A98UL,
+  /*    C0B8 */ 0x00000000UL,
+  0x0004C0CCUL, 0x00000001UL,
+  /*    C0D0 */ 0x00000000UL,
+  /*    C0D4 */ 0x000A0001UL,
+  /*    C0D8 */ 0x00280001UL,
+  0x01010008UL, 0x00000744UL,
+  0x01010018UL, 0x00000000UL,
+  0x01010020UL, 0x0000A001UL,
+  0x01254040UL, 0x00000000UL,
+  /*    4044 */ 0x00000000UL,
+  /*    4048 */ 0x00000010UL,
+  /*    404C */ 0x00000191UL,
+  /*    4050 */ 0x0602C001UL,
+  /*    4054 */ 0x00003000UL,
+  /*    4058 */ 0x00000000UL,
+  /*    405C */ 0x03000000UL,
+  /*    4060 */ 0x20000000UL,
+  /*    4064 */ 0x00000000UL,
+  /*    4068 */ 0x00067530UL,
+  /*    406C */ 0x00000841UL,
+  /*    4070 */ 0x000407F0UL,
+  /*    4074 */ 0x00000010UL,
+  /*    4078 */ 0x00000000UL,
+  /*    407C */ 0x00000000UL,
+  /*    4080 */ 0x08AC0000UL,
+  /*    4084 */ 0x00000000UL,
+  /*    4088 */ 0x000F031CUL,
+  /*    408C */ 0x60000000UL,
+  /*    4090 */ 0x00000000UL,
+  /*    4094 */ 0x00000000UL,
+  /*    4098 */ 0x00000000UL,
+  /*    409C */ 0x00000000UL,
+  /*    40A0 */ 0x00000000UL,
+  /*    40A4 */ 0x00000000UL,
+  /*    40A8 */ 0x00000000UL,
+  /*    40AC */ 0x00000000UL,
+  /*    40B0 */ 0x00000000UL,
+  /*    40B4 */ 0x00000000UL,
+  /*    40B8 */ 0x00000000UL,
+  /*    40BC */ 0x00000000UL,
+  /*    40C0 */ 0x00000000UL,
+  /*    40C4 */ 0x00000000UL,
+  /*    40C8 */ 0x00000000UL,
+  /*    40CC */ 0x00000000UL,
+  /*    40D0 */ 0x00000000UL,
+  0x010140E0UL, 0x00000200UL,
+  0x01024110UL, 0x00051E33UL,
+  /*    4114 */ 0x00000000UL,
+  0x010E411CUL, 0x8B561000UL,
+  /*    4120 */ 0x00000000UL,
+  /*    4124 */ 0x078304FFUL,
+  /*    4128 */ 0x3AC81388UL,
+  /*    412C */ 0x0C6606FFUL,
+  /*    4130 */ 0x078304FFUL,
+  /*    4134 */ 0x03FF1388UL,
+  /*    4138 */ 0xF00A20BCUL,
+  /*    413C */ 0x00503354UL,
+  /*    4140 */ 0x00000000UL,
+  /*    4144 */ 0x123556B7UL,
+  /*    4148 */ 0x50000000UL,
+  /*    414C */ 0x00003B80UL,
+  /*    4150 */ 0x00000000UL,
+  0x01024158UL, 0x00000000UL,
+  /*    415C */ 0x00000000UL,
+  0x010D4164UL, 0x0000010CUL,
+  /*    4168 */ 0x00FA53E8UL,
+  /*    416C */ 0x40000000UL,
+  /*    4170 */ 0x00000000UL,
+  /*    4174 */ 0x00000000UL,
+  /*    4178 */ 0x00000000UL,
+  /*    417C */ 0x00000000UL,
+  /*    4180 */ 0x00000000UL,
+  /*    4184 */ 0x00000101UL,
+  /*    4188 */ 0x00000000UL,
+  /*    418C */ 0x00000000UL,
+  /*    4190 */ 0x00000000UL,
+  /*    4194 */ 0x00000000UL,
+  0x010241A4UL, 0x00000000UL,
+  /*    41A8 */ 0x00000000UL,
+  0x010241B0UL, 0x00000000UL,
+  /*    41B4 */ 0x00200000UL,
+  0x010341BCUL, 0x00000000UL,
+  /*    41C0 */ 0x003C0000UL,
+  /*    41C4 */ 0x00066666UL,
+  0x010341D0UL, 0x00000000UL,
+  /*    41D4 */ 0x00000010UL,
+  /*    41D8 */ 0x00020000UL,
+  0x011641E0UL, 0x00000000UL,
+  /*    41E4 */ 0x0BFFE7E6UL,
+  /*    41E8 */ 0x000AA1CDUL,
+  /*    41EC */ 0x006A06BDUL,
+  /*    41F0 */ 0x004DB05EUL,
+  /*    41F4 */ 0x0E42027DUL,
+  /*    41F8 */ 0x0222B6A5UL,
+  /*    41FC */ 0x34B225FFUL,
+  /*    4200 */ 0x0BFFE7E6UL,
+  /*    4204 */ 0x000AA1CDUL,
+  /*    4208 */ 0x006A06BDUL,
+  /*    420C */ 0x004DB05EUL,
+  /*    4210 */ 0x0E42027DUL,
+  /*    4214 */ 0x0222B6A5UL,
+  /*    4218 */ 0x34B225FFUL,
+  /*    421C */ 0x00000000UL,
+  /*    4220 */ 0x00000000UL,
+  /*    4224 */ 0x00000005UL,
+  /*    4228 */ 0x00000000UL,
+  /*    422C */ 0x40001860UL,
+  /*    4230 */ 0x00000000UL,
+  /*    4234 */ 0x00000000UL,
+  0x0101423CUL, 0x00000000UL,
+  0x01034244UL, 0x00000014UL,
+  /*    4248 */ 0x00000000UL,
+  /*    424C */ 0x04000008UL,
+  0x01014268UL, 0x00000000UL,
+  0x01024280UL, 0x00000000UL,
+  /*    4284 */ 0x00000081UL,
+  0x01054298UL, 0x0200003FUL,
+  /*    429C */ 0x0000FFFFUL,
+  /*    42A0 */ 0x0000FFFFUL,
+  /*    42A4 */ 0x000003FFUL,
+  /*    42A8 */ 0x0000FFFFUL,
+  0x010142B4UL, 0x00000000UL,
+  0x010A4330UL, 0x01200040UL,
+  /*    4334 */ 0x000000A0UL,
+  /*    4338 */ 0x01005008UL,
+  /*    433C */ 0x1F1F1F1FUL,
+  /*    4340 */ 0x1B1F1F1FUL,
+  /*    4344 */ 0x11131518UL,
+  /*    4348 */ 0x0C0D0E10UL,
+  /*    434C */ 0x2F87C145UL,
+  /*    4350 */ 0x00000000UL,
+  /*    4354 */ 0x00000000UL,
+  0x01018010UL, 0x00000003UL,
+  0x01028038UL, 0x00100418UL,
+  /*    803C */ 0x00000001UL,
+  0x0103809CUL, 0x00000000UL,
+  /*    80A0 */ 0x00037870UL,
+  /*    80A4 */ 0x000000D0UL,
+  0x110180A8UL, 0x000001F0UL,
+  0x310180A8UL, 0x01CB4205UL,
+  0x110180ACUL, 0x000001F0UL,
+  0x310180ACUL, 0x00FD3E05UL,
+  0x010280B0UL, 0x02000300UL,
+  /*    80B4 */ 0x01000037UL,
+  0x0201009CUL, 0x04000C00UL,
+  0x020300D8UL, 0xAA400005UL,
+  /*    00DC */ 0x00000188UL,
+  /*    00E0 */ 0x000000C0UL,
+  0x120100ECUL, 0x00000FE0UL,
+  0x320100ECUL, 0x5151200CUL,
+  0x020100F0UL, 0x0000012BUL,
+  0x12010110UL, 0x000FFF00UL,
+  0x32010110UL, 0x31000002UL,
+  0x12010150UL, 0x0001C000UL,
+  0x32010150UL, 0x00A200C1UL,
+  0x02010174UL, 0x0C1B8169UL,
+  0x12010178UL, 0x001C0000UL,
+  0x32010178UL, 0xCFE00410UL,
+  0x12010180UL, 0x00000779UL,
+  0x32010180UL, 0x00000002UL,
+  0x02020184UL, 0x00001000UL,
+  /*    0188 */ 0x00000050UL,
+  0x03014FFCUL, (uint32_t) &phyInfo,
+  0xFFFFFFFFUL,
+};
+
+const RAIL_ChannelConfigEntry_t sl_rfsense_ook_1kbps_40MHz_channels[] = {
+  {
+    .phyConfigDeltaAdd = NULL,
+    .baseFrequency = 2450000000,
+    .channelSpacing = 1000000,
+    .physicalChannelOffset = 0,
+    .channelNumberStart = 0,
+    .channelNumberEnd = 0,
+    .maxPower = RAIL_TX_POWER_MAX,
+    .attr = &channelConfigEntryAttr,
+#ifdef RADIO_CONFIG_ENABLE_CONC_PHY
+    .entryType = 0,
+#endif
+#ifdef RADIO_CONFIG_ENABLE_STACK_INFO
+    .stackInfo = stackInfo_0,
+#endif
+    .alternatePhy = NULL,
+  },
+};
+
+const RAIL_ChannelConfig_t sl_rfsense_ook_1kbps_40MHz_channelConfig = {
+  .phyConfigBase = sl_rfsense_ook_1kbps_40MHz_modemConfigBase,
+  .phyConfigDeltaSubtract = NULL,
+  .configs = sl_rfsense_ook_1kbps_40MHz_channels,
+  .length = 1U,
+  .signature = 0UL,
+  .xtalFrequencyHz = 40000000UL,
+};

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_rfsense_ook_config_40MHz.h

@@ -0,0 +1,48 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @details
+ *   WARNING: Auto-Generated Radio Config Header  -  DO NOT EDIT
+ *   Radio Configurator Version: 2404.4.4
+ *   RAIL Adapter Version: 2.4.33
+ *   RAIL Compatibility: 2.x
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __SL_RAIL_RFSENSE_OOK_CONFIG_40MHZ_H__
+#define __SL_RAIL_RFSENSE_OOK_CONFIG_40MHZ_H__
+
+#include <stdint.h>
+#include "rail_types.h"
+
+extern const uint32_t sl_rfsense_ook_1kbps_40MHz_modemConfigBase[];
+
+#define RAIL0_SL_RFSENSE_OOK_1KBPS_40MHZ_PHY_RFSENSE_2450M_OOK_1KBPS
+#define RAIL0_SL_RFSENSE_OOK_1KBPS_40MHZ_PROFILE_BASE
+extern const RAIL_ChannelConfig_t sl_rfsense_ook_1kbps_40MHz_channelConfig;
+extern const RAIL_ChannelConfigEntry_t sl_rfsense_ook_1kbps_40MHz_channels[];
+
+#endif // __SL_RAIL_RFSENSE_OOK_CONFIG_40MHZ_H__

Libs/platform/radio/rail_lib/plugin/rail_util_built_in_phys/sl_rail_phy_overrides.c

@@ -0,0 +1,355 @@
+/***************************************************************************//**
+ * @file sl_rail_phy_overrides.c
+ * @brief Applies PHY overrides based on a device's HFXO frequency.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef SL_COMPONENT_CATALOG_PRESENT
+#include "sl_component_catalog.h"
+#endif // SL_COMPONENT_CATALOG_PRESENT
+
+#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT)
+#include "sl_clock_manager_oscillator_config.h"
+#define SL_RAIL_PHY_INIT_HFXO_FREQ   SL_CLOCK_MANAGER_HFXO_FREQ
+#else // !defined(SL_CATALOG_CLOCK_MANAGER_PRESENT)
+#include "sl_device_init_hfxo_config.h"
+#define SL_RAIL_PHY_INIT_HFXO_FREQ   SL_DEVICE_INIT_HFXO_FREQ
+#endif // defined(SL_CATALOG_CLOCK_MANAGER_PRESENT)
+
+#include "sl_rail_ble_config_38M4Hz.h"
+#include "sl_rail_ieee802154_config_38M4Hz.h"
+#include "sl_rail_rfsense_ook_config_38M4Hz.h"
+#include "sl_rail_ble_config_39MHz.h"
+#include "sl_rail_ieee802154_config_39MHz.h"
+#include "sl_rail_rfsense_ook_config_39MHz.h"
+#include "sl_rail_ble_config_40MHz.h"
+#include "sl_rail_ieee802154_config_40MHz.h"
+#include "sl_rail_rfsense_ook_config_40MHz.h"
+
+#if SL_RAIL_PHY_INIT_HFXO_FREQ == 38400000
+
+#if RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1Mbps =
+  &sl_rail_ble_phy_1Mbps_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2Mbps =
+  &sl_rail_ble_phy_2Mbps_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_1MBPS_VITERBI
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1MbpsViterbi =
+  &sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_2MBPS_VITERBI
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbi =
+  &sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_channelConfig;
+#if RAIL_BLE_SUPPORTS_AOX
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsAox =
+  &sl_rail_ble_phy_2Mbps_aox_38M4Hz_channelConfig;
+#endif
+#endif
+
+#if RAIL_BLE_SUPPORTS_CS
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1MbpsViterbiCs = NULL;
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbiCs = NULL;
+#endif
+
+#if RAIL_BLE_SUPPORTS_CODED_PHY
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy125kbps =
+  &sl_rail_ble_phy_125kbps_38M4Hz_channelConfig;
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy500kbps =
+  &sl_rail_ble_phy_500kbps_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_SIMULSCAN_PHY
+const RAIL_ChannelConfig_t *const RAIL_BLE_PhySimulscan =
+  &sl_rail_ble_phy_simulscan_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_SUPPORTS_2P4GHZ_BAND && RAIL_SUPPORTS_PROTOCOL_IEEE802154
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz =
+  &sl_rail_ieee802154_phy_2G4Hz_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_2MBPS_PHY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz1MbpsFec =
+  &sl_rail_ieee802154_phy_2G4Hz_1Mbps_fec_38M4Hz_channelConfig;
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz2Mbps =
+  &sl_rail_ieee802154_phy_2G4Hz_2Mbps_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_SUPPORTS_ANTENNA_DIVERSITY && RAIL_SUPPORTS_2P4GHZ_BAND \
+  && RAIL_SUPPORTS_PROTOCOL_IEEE802154
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDiv =
+  &sl_rail_ieee802154_phy_2G4Hz_antdiv_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING && (_SILICON_LABS_32B_SERIES_2_CONFIG != 1)
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzRxChSwitching =
+  &sl_rail_ieee802154_phy_2G4Hz_fast_switch_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_COEX_PHY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCoex =
+  &sl_rail_ieee802154_phy_2G4Hz_coex_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_COEX_PHY && RAIL_SUPPORTS_ANTENNA_DIVERSITY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivCoex =
+  &sl_rail_ieee802154_phy_2G4Hz_antdiv_coex_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_FEM_PHY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzFem =
+  &sl_rail_ieee802154_phy_2G4Hz_fem_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_FEM_PHY && RAIL_SUPPORTS_ANTENNA_DIVERSITY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivFem =
+  &sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_FEM_PHY && RAIL_IEEE802154_SUPPORTS_COEX_PHY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCoexFem =
+  &sl_rail_ieee802154_phy_2G4Hz_coex_fem_38M4Hz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_FEM_PHY && RAIL_IEEE802154_SUPPORTS_COEX_PHY \
+  && RAIL_SUPPORTS_ANTENNA_DIVERSITY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivCoexFem =
+  &sl_rail_ieee802154_phy_2G4Hz_antdiv_coex_fem_38M4Hz_channelConfig;
+#endif
+
+const RAIL_ChannelConfig_t *const RAIL_RFSENSE_OOK_Phy1kbps =
+  &sl_rfsense_ook_1kbps_38M4Hz_channelConfig;
+
+#elif SL_RAIL_PHY_INIT_HFXO_FREQ == 39000000
+
+#if RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1Mbps =
+  &sl_rail_ble_phy_1Mbps_39MHz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2Mbps =
+  &sl_rail_ble_phy_2Mbps_39MHz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_1MBPS_VITERBI
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1MbpsViterbi =
+  &sl_rail_ble_phy_1Mbps_viterbi_39MHz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_2MBPS_VITERBI
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbi =
+  &sl_rail_ble_phy_2Mbps_viterbi_39MHz_channelConfig;
+#if RAIL_BLE_SUPPORTS_AOX
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsAox =
+  &sl_rail_ble_phy_2Mbps_aox_39MHz_channelConfig;
+#endif
+#endif
+
+#if RAIL_BLE_SUPPORTS_CS
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1MbpsViterbiCs = NULL;
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbiCs = NULL;
+#endif
+
+#if RAIL_BLE_SUPPORTS_CODED_PHY
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy125kbps =
+  &sl_rail_ble_phy_125kbps_39MHz_channelConfig;
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy500kbps =
+  &sl_rail_ble_phy_500kbps_39MHz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_SIMULSCAN_PHY
+const RAIL_ChannelConfig_t *const RAIL_BLE_PhySimulscan =
+  &sl_rail_ble_phy_simulscan_39MHz_channelConfig;
+#endif
+
+#if RAIL_SUPPORTS_2P4GHZ_BAND && RAIL_SUPPORTS_PROTOCOL_IEEE802154
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz =
+  &sl_rail_ieee802154_phy_2G4Hz_39MHz_channelConfig;
+#endif
+
+#if RAIL_SUPPORTS_ANTENNA_DIVERSITY && RAIL_SUPPORTS_2P4GHZ_BAND \
+  && RAIL_SUPPORTS_PROTOCOL_IEEE802154
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDiv =
+  &sl_rail_ieee802154_phy_2G4Hz_antdiv_39MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING && (_SILICON_LABS_32B_SERIES_2_CONFIG != 1)
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzRxChSwitching =
+  &sl_rail_ieee802154_phy_2G4Hz_fast_switch_39MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_COEX_PHY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCoex =
+  &sl_rail_ieee802154_phy_2G4Hz_coex_39MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_COEX_PHY && RAIL_SUPPORTS_ANTENNA_DIVERSITY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivCoex =
+  &sl_rail_ieee802154_phy_2G4Hz_antdiv_coex_39MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_2MBPS_PHY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz1MbpsFec =
+  &sl_rail_ieee802154_phy_2G4Hz_1Mbps_fec_39MHz_channelConfig;
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz2Mbps =
+  &sl_rail_ieee802154_phy_2G4Hz_2Mbps_39MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_FEM_PHY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzFem =
+  &sl_rail_ieee802154_phy_2G4Hz_fem_39MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_FEM_PHY && RAIL_SUPPORTS_ANTENNA_DIVERSITY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivFem =
+  &sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_39MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_FEM_PHY && RAIL_IEEE802154_SUPPORTS_COEX_PHY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCoexFem =
+  &sl_rail_ieee802154_phy_2G4Hz_coex_fem_39MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_FEM_PHY && RAIL_IEEE802154_SUPPORTS_COEX_PHY \
+  && RAIL_SUPPORTS_ANTENNA_DIVERSITY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivCoexFem =
+  &sl_rail_ieee802154_phy_2G4Hz_antdiv_coex_fem_39MHz_channelConfig;
+#endif
+
+const RAIL_ChannelConfig_t *const RAIL_RFSENSE_OOK_Phy1kbps =
+  &sl_rfsense_ook_1kbps_39MHz_channelConfig;
+
+#elif SL_RAIL_PHY_INIT_HFXO_FREQ == 40000000
+
+#if RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1Mbps =
+  &sl_rail_ble_phy_1Mbps_40MHz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2Mbps =
+  &sl_rail_ble_phy_2Mbps_40MHz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_1MBPS_VITERBI
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1MbpsViterbi =
+  &sl_rail_ble_phy_1Mbps_viterbi_40MHz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_2MBPS_VITERBI
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbi =
+  &sl_rail_ble_phy_2Mbps_viterbi_40MHz_channelConfig;
+#if RAIL_BLE_SUPPORTS_AOX
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsAox =
+  &sl_rail_ble_phy_2Mbps_aox_40MHz_channelConfig;
+#endif
+#endif
+
+#if RAIL_BLE_SUPPORTS_CS
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1MbpsViterbiCs =
+  &sl_rail_ble_phy_1Mbps_viterbi_cs_40MHz_channelConfig;
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbiCs =
+  &sl_rail_ble_phy_2Mbps_viterbi_cs_40MHz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_CODED_PHY
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy125kbps =
+  &sl_rail_ble_phy_125kbps_40MHz_channelConfig;
+const RAIL_ChannelConfig_t *const RAIL_BLE_Phy500kbps =
+  &sl_rail_ble_phy_500kbps_40MHz_channelConfig;
+#endif
+
+#if RAIL_BLE_SUPPORTS_SIMULSCAN_PHY
+const RAIL_ChannelConfig_t *const RAIL_BLE_PhySimulscan =
+  &sl_rail_ble_phy_simulscan_40MHz_channelConfig;
+#endif
+
+#if RAIL_SUPPORTS_2P4GHZ_BAND && RAIL_SUPPORTS_PROTOCOL_IEEE802154
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz =
+  &sl_rail_ieee802154_phy_2G4Hz_40MHz_channelConfig;
+#endif
+
+#if RAIL_SUPPORTS_ANTENNA_DIVERSITY && RAIL_SUPPORTS_2P4GHZ_BAND \
+  && RAIL_SUPPORTS_PROTOCOL_IEEE802154
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDiv =
+  &sl_rail_ieee802154_phy_2G4Hz_antdiv_40MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING && (_SILICON_LABS_32B_SERIES_2_CONFIG != 1)
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzRxChSwitching =
+  &sl_rail_ieee802154_phy_2G4Hz_fast_switch_40MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_COEX_PHY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCoex =
+  &sl_rail_ieee802154_phy_2G4Hz_coex_40MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_COEX_PHY && RAIL_SUPPORTS_ANTENNA_DIVERSITY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivCoex =
+  &sl_rail_ieee802154_phy_2G4Hz_antdiv_coex_40MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_2MBPS_PHY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz1MbpsFec =
+  &sl_rail_ieee802154_phy_2G4Hz_1Mbps_fec_40MHz_channelConfig;
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz2Mbps =
+  &sl_rail_ieee802154_phy_2G4Hz_2Mbps_40MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_FEM_PHY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzFem =
+  &sl_rail_ieee802154_phy_2G4Hz_fem_40MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_FEM_PHY && RAIL_SUPPORTS_ANTENNA_DIVERSITY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivFem =
+  &sl_rail_ieee802154_phy_2G4Hz_antdiv_fem_40MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_FEM_PHY && RAIL_IEEE802154_SUPPORTS_COEX_PHY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCoexFem =
+  &sl_rail_ieee802154_phy_2G4Hz_coex_fem_40MHz_channelConfig;
+#endif
+
+#if RAIL_IEEE802154_SUPPORTS_FEM_PHY && RAIL_IEEE802154_SUPPORTS_COEX_PHY \
+  && RAIL_SUPPORTS_ANTENNA_DIVERSITY
+const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivCoexFem =
+  &sl_rail_ieee802154_phy_2G4Hz_antdiv_coex_fem_40MHz_channelConfig;
+#endif
+
+const RAIL_ChannelConfig_t *const RAIL_RFSENSE_OOK_Phy1kbps =
+  &sl_rfsense_ook_1kbps_40MHz_channelConfig;
+
+#endif // SL_RAIL_PHY_INIT_HFXO_FREQ

Libs/platform/radio/rail_lib/plugin/rail_util_power_manager_init/sl_rail_util_power_manager_init.c

@@ -0,0 +1,39 @@
+/***************************************************************************//**
+ * @file
+ * @brief Initialize RAIL power manager
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#include "rail.h"
+#include "sl_rail_util_power_manager_init.h"
+#include "sl_rail_util_power_manager_init_config.h"
+
+void sl_rail_util_power_manager_init(void)
+{
+#if SL_RAIL_UTIL_RAIL_POWER_MANAGER_INIT == 1
+  RAIL_InitPowerManager();
+#endif
+}

Libs/platform/radio/rail_lib/plugin/rail_util_power_manager_init/sl_rail_util_power_manager_init.h

@@ -0,0 +1,50 @@
+/***************************************************************************//**
+ * @file
+ * @brief Initialize RAIL power manager
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SL_RAIL_UTIL_POWER_MANAGER_INIT_H
+#define SL_RAIL_UTIL_POWER_MANAGER_INIT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Initialize RAIL power manager
+ *
+ * @note: This function should be called during application initialization,
+ *        after sl_power_manager_init function has been called.
+ */
+void sl_rail_util_power_manager_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SL_RAIL_UTIL_POWER_MANAGER_INIT_H

Libs/platform/radio/rail_lib/plugin/rail_util_pti/sl_rail_util_pti.c

@@ -0,0 +1,67 @@
+/***************************************************************************//**
+ * @file
+ * @brief Packet Trace Information
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include "em_device.h"
+#include "sl_gpio.h"
+
+#include "rail.h"
+#include "sl_rail_util_pti.h"
+#include "sl_rail_util_pti_config.h"
+
+void sl_rail_util_pti_init(void)
+{
+  RAIL_PtiConfig_t railPtiConfig = {
+    .mode = SL_RAIL_UTIL_PTI_MODE,
+    .baud = SL_RAIL_UTIL_PTI_BAUD_RATE_HZ,
+#if defined(SL_RAIL_UTIL_PTI_DOUT_PORT) && defined(SL_RAIL_UTIL_PTI_DOUT_PIN)
+    .doutPort = (uint8_t)SL_RAIL_UTIL_PTI_DOUT_PORT,
+    .doutPin = SL_RAIL_UTIL_PTI_DOUT_PIN,
+  #ifdef SL_RAIL_UTIL_PTI_DOUT_LOC
+    .doutLoc = SL_RAIL_UTIL_PTI_DOUT_LOC,
+  #endif // SL_RAIL_UTIL_PTI_DOUT_LOC
+#endif // dout support
+#if defined(SL_RAIL_UTIL_PTI_DCLK_PORT) && defined(SL_RAIL_UTIL_PTI_DCLK_PIN)
+    .dclkPort = (uint8_t)SL_RAIL_UTIL_PTI_DCLK_PORT,
+    .dclkPin = SL_RAIL_UTIL_PTI_DCLK_PIN,
+  #ifdef SL_RAIL_UTIL_PTI_DCLK_LOC
+    .dclkLoc = SL_RAIL_UTIL_PTI_DCLK_LOC,
+  #endif // SL_RAIL_UTIL_PTI_DCLK_LOC
+#endif // dclk support
+#if defined(SL_RAIL_UTIL_PTI_DFRAME_PORT) && defined(SL_RAIL_UTIL_PTI_DFRAME_PIN)
+    .dframePort = (uint8_t)SL_RAIL_UTIL_PTI_DFRAME_PORT,
+    .dframePin = SL_RAIL_UTIL_PTI_DFRAME_PIN,
+  #ifdef SL_RAIL_UTIL_PTI_DFRAME_LOC
+    .dframeLoc = SL_RAIL_UTIL_PTI_DFRAME_LOC,
+  #endif // SL_RAIL_UTIL_PTI_DFRAME_LOC
+#endif // dframe support
+  };
+
+  RAIL_ConfigPti(RAIL_EFR32_HANDLE, &railPtiConfig);
+}

Libs/platform/radio/rail_lib/plugin/rail_util_pti/sl_rail_util_pti.h

@@ -0,0 +1,49 @@
+/***************************************************************************//**
+ * @file
+ * @brief Packet Trace Information initialization and usage
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SL_RAIL_UTIL_PTI_H
+#define SL_RAIL_UTIL_PTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Initialize the RAIL PTI Utility.
+ *
+ * @note: This function should be called during application initialization.
+ */
+void sl_rail_util_pti_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SL_RAIL_UTIL_PTI_H

Libs/platform/radio/rail_lib/plugin/rail_util_rssi/sl_rail_util_rssi.c

@@ -0,0 +1,38 @@
+/***************************************************************************//**
+ * @file
+ * @brief Default RSSI setup
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include "rail.h"
+#include "sl_rail_util_rssi.h"
+#include "sl_rail_util_rssi_config.h"
+
+void sl_rail_util_rssi_init(void)
+{
+  (void)RAIL_SetRssiOffset(RAIL_EFR32_HANDLE, (int8_t)SL_RAIL_UTIL_RSSI_OFFSET);
+}

Libs/platform/radio/rail_lib/plugin/rail_util_rssi/sl_rail_util_rssi.h

@@ -0,0 +1,50 @@
+/***************************************************************************//**
+ * @file
+ * @brief Default RSSI setup
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SL_RAIL_UTIL_RSSI_H
+#define SL_RAIL_UTIL_RSSI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Initialize the default RSSI.
+ *
+ * @note: This function should be called during application initialization
+ *        before \ref RAIL_Init has been called.
+ */
+void sl_rail_util_rssi_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SL_RAIL_UTIL_RSSI_H

Libs/platform/radio/rail_lib/plugin/rail_util_sequencer/sl_rail_util_sequencer.c

@@ -0,0 +1,45 @@
+/***************************************************************************//**
+ * @file
+ * @brief
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2023 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#include "sl_rail_util_sequencer_config.h"
+#include "rail.h"
+
+#if !SL_RAIL_UTIL_SEQUENCER_RUNTIME_IMAGE_SELECTION \
+  && defined(SL_RAIL_UTIL_SEQUENCER_IMAGE)
+RAIL_Status_t RAILCb_RadioSequencerImageLoad(void)
+{
+#if SL_RAIL_UTIL_SEQUENCER_IMAGE == RAIL_SEQ_IMAGE_1
+  return RAIL_LoadSequencerImage1(RAIL_EFR32_HANDLE);
+#elif SL_RAIL_UTIL_SEQUENCER_IMAGE == RAIL_SEQ_IMAGE_2
+  return RAIL_LoadSequencerImage2(RAIL_EFR32_HANDLE);
+#else
+  #error "Must choose a valid sequencer image!"
+#endif
+}
+#endif

Libs/platform/radio/rail_lib/protocol/sidewalk/rail_sidewalk.h

@@ -0,0 +1,85 @@
+/***************************************************************************//**
+ * @file
+ * @brief The Sidewalk specific header file for the RAIL library.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2023 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef RAIL_SIDEWALK_H
+#define RAIL_SIDEWALK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Get the standard include types
+#include <stdint.h>
+#include <stdbool.h>
+
+// Get the RAIL specific structures and types
+#include "rail_types.h"
+
+/// @addtogroup SIDEWALK_PHY Sidewalk Radio Configurations
+/// @ingroup Protocol_Specific
+/// Radio configurations for the RAIL Sidewalk Accelerator
+///
+/// These radio configurations are used to configure Sidewalk when a function
+/// such as \ref RAIL_Sidewalk_ConfigPhy2GFSK50kbps() is called. Each radio
+/// configuration listed below is compiled into the RAIL library as a weak
+/// symbol that will take into account per-die defaults. If the board
+/// configuration in use has different settings than the default, such as a
+/// different radio subsystem clock frequency, these radio configurations can
+/// be overriden to account for those settings.
+/// @{
+
+/**
+ * Default PHY to use for Sidewalk 2GFSK 50kbps. Will be NULL if
+ * \ref RAIL_SUPPORTS_PROTOCOL_SIDEWALK is 0.
+ */
+extern const RAIL_ChannelConfig_t *const RAIL_Sidewalk_Phy2GFSK50kbps;
+
+/**
+ * Switch to the 2GFSK 50 kbps Sidewalk PHY.
+ *
+ * @param[in] railHandle A handle for RAIL instance.
+ * @return Status code indicating success of the function call.
+ *
+ * Use this function to switch to the 2GFSK 50 kbps Sidewalk PHY.
+ *
+ * @note The Sidewalk PHY is supported only on some parts.
+ *   The preprocessor symbol \ref RAIL_SUPPORTS_PROTOCOL_SIDEWALK and the
+ *   runtime function \ref RAIL_SupportsProtocolSidewalk() may be used to
+ *   test for support of the Sidewalk PHY.
+ */
+RAIL_Status_t RAIL_Sidewalk_ConfigPhy2GFSK50kbps(RAIL_Handle_t railHandle);
+
+/// @} // End of group SIDEWALK_PHY
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // RAIL_SIDEWALK_H

Libs/platform/radio/rail_lib/protocol/wmbus/rail_wmbus.h

@@ -0,0 +1,91 @@
+/***************************************************************************//**
+ * @file
+ * @brief The WMBUS specific header file for the RAIL library.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2023 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __RAIL_WMBUS_H__
+#define __RAIL_WMBUS_H__
+
+#include "rail_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @addtogroup WMBUS Wireless M-Bus
+/// @ingroup Protocol_Specific
+/// @brief Wireless M-Bus (WMBUS) configuration
+/// @{
+
+/**
+ * @enum RAIL_WMBUS_Phy_t
+ * @brief The RX variant of the WMBUS T+C PHY.
+ */
+RAIL_ENUM(RAIL_WMBUS_Phy_t) {
+  /** \ref RAIL_RxPacketDetails_t::subPhyId indicating a mode T frame A packet */
+  RAIL_WMBUS_ModeTFrameA = 0U,
+  /** \ref RAIL_RxPacketDetails_t::subPhyId indicating a mode C frame A packet */
+  RAIL_WMBUS_ModeCFrameA = 2U,
+  /** \ref RAIL_RxPacketDetails_t::subPhyId indicating a mode C frame B packet */
+  RAIL_WMBUS_ModeCFrameB = 3U,
+};
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+#define RAIL_WMBUS_ModeTFrameA ((RAIL_WMBUS_Phy_t) RAIL_WMBUS_ModeTFrameA)
+#define RAIL_WMBUS_ModeCFrameA ((RAIL_WMBUS_Phy_t) RAIL_WMBUS_ModeCFrameA)
+#define RAIL_WMBUS_ModeCFrameB ((RAIL_WMBUS_Phy_t) RAIL_WMBUS_ModeCFrameB)
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+/**
+ * Configure WMBUS simultaneous M2O RX of T and C modes feature.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] enableSimultaneousTCRx true to enable WMBUS simultaneous M2O RX of T and C modes.
+ * @return Status code indicating success of the function call.
+ *
+ * If simultaneous M2O RX of T and C modes is enabled, when
+ * PHY_wMbus_ModeTC_M2O_100k_frameA is loaded, mode T Frame A and mode C frame
+ * A/B can be received. The mode and frame type of the last received packet is
+ * available in \ref RAIL_RxPacketDetails_t::subPhyId.
+ *
+ * @note This WMBUS feature is supported only on some parts.
+ * The preprocessor symbol \ref RAIL_WMBUS_SUPPORTS_SIMULTANEOUS_T_C_RX and the
+ * runtime function \ref RAIL_WMBUS_SupportsSimultaneousTCRx() may be used to
+ * test for support.
+ */
+RAIL_Status_t RAIL_WMBUS_Config(RAIL_Handle_t railHandle,
+                                bool enableSimultaneousTCRx);
+
+/// @} // End of group WMBUS
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __RAIL_WMBUS_H__

Libs/platform/radio/rail_lib/protocol/zwave/rail_zwave.h

@@ -0,0 +1,999 @@
+/***************************************************************************//**
+ * @file
+ * @brief The Z-Wave specific header file for the RAIL library.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef __RAIL_ZWAVE_H__
+#define __RAIL_ZWAVE_H__
+
+#include "rail_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @addtogroup Z_Wave Z-Wave
+/// @ingroup Protocol_Specific
+/// @brief Z-Wave configuration routines
+///
+/// The functions in this group configure RAIL Z-Wave hardware
+/// acceleration features.
+///
+/// To configure Z-Wave functionality, the application must first set up
+/// a RAIL instance with \ref RAIL_Init() and other setup functions.
+/// @code{.c}
+/// RAIL_ZWAVE_NodeId_t gRecentBeamNodeId;
+/// uint8_t gRecentBeamChannelIndex;
+///
+/// // Main RAIL_EVENT callback
+/// static void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events)
+/// {
+///   // Get beam Node Id and channel index from beam packet
+///   if (events & RAIL_EVENT_ZWAVE_BEAM) {
+///     if (RAIL_ZWAVE_IsEnabled(railHandle)) {
+///       if ((RAIL_ZWAVE_GetBeamNodeId(railHandle, &gRecentBeamNodeId)
+///            != RAIL_STATUS_NO_ERROR)
+///           || (RAIL_ZWAVE_GetBeamChannelIndex(railHandle, &gRecentBeamChannelIndex)
+///               != RAIL_STATUS_NO_ERROR)) {
+///         return;
+///       }
+///     }
+///   }
+/// }
+///
+/// static const RAIL_ZWAVE_Config_t zwaveConfig = {
+///   .options = RAIL_ZWAVE_OPTIONS_DEFAULT
+/// };
+///
+/// RAIL_Status_t zwaveInit(void)
+/// {
+///   // initialize Z-Wave
+///   RAIL_Status_t status = RAIL_ZWAVE_Init(railHandle, &zwaveConfig);
+///
+///   if (status != RAIL_STATUS_NO_ERROR) {
+///     return status;
+///   }
+///
+///   uint8_t myHomeId[4] = { 0xDE, 0xAD, 0xBE, 0xEF };
+///   RAIL_ZWAVE_SetNodeId(railHandle, RAIL_ZWAVE_NODE_ID_DEFAULT);
+///   RAIL_ZWAVE_SetHomeId(railHandle, myHomeId, RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE);
+///
+///   // configure region to EU(European Union)
+///   return RAIL_ZWAVE_ConfigRegion(railHandle, RAIL_ZWAVE_REGION_EU);
+/// }
+/// @endcode
+///
+/// @{
+
+/**
+ * @enum RAIL_ZWAVE_Options_t
+ * @brief Z-Wave options.
+ */
+RAIL_ENUM_GENERIC(RAIL_ZWAVE_Options_t, uint32_t) {
+  /** Shift position of \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE bit. */
+  RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE_SHIFT = 0,
+  /** Shift position of \ref RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES bit. */
+  RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES_SHIFT = 1,
+  /** Shift position of \ref RAIL_ZWAVE_OPTION_NODE_ID_FILTERING bit. */
+  RAIL_ZWAVE_OPTION_NODE_ID_FILTERING_SHIFT = 2,
+  /** Shift position of \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE bit. */
+  RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE_SHIFT = 3,
+};
+
+/** A value representing no options */
+#define RAIL_ZWAVE_OPTIONS_NONE 0U
+
+/** All options are disabled by default. */
+#define RAIL_ZWAVE_OPTIONS_DEFAULT RAIL_ZWAVE_OPTIONS_NONE
+
+/**
+ * An option to configure promiscuous mode, accepting non-beam packets
+ * regardless of their Home Id. By default packets are filtered by their Home Id.
+ * When true, such filtering is disabled.
+ */
+#define RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE \
+  (1u << RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE_SHIFT)
+
+/**
+ * An option to filter non-beam packets based on their Node Id when
+ * \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE is disabled.
+ *
+ * @note This option has no effect when
+ *   \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE is enabled.
+ */
+#define RAIL_ZWAVE_OPTION_NODE_ID_FILTERING \
+  (1u << RAIL_ZWAVE_OPTION_NODE_ID_FILTERING_SHIFT)
+
+/**
+ * An option to configure beam frame recognition. By default beams are not
+ * considered special and will be received as if they were normal Z-Wave
+ * frames, assuredly triggering \ref RAIL_EVENT_RX_FRAME_ERROR.
+ * When true, beam frames that are broadcast or match the Node Id and
+ * Home Id hash values will trigger \ref RAIL_EVENT_ZWAVE_BEAM event.
+ * (All beams additionally trigger \ref RAIL_EVENT_RX_PACKET_ABORTED
+ * regardless of Node Id / Home Id hash values.)
+ *
+ * @note This option takes precedence over \ref
+ *   RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE when receiving a beam frame.
+ *   For promiscuous beam handling see related
+ *   \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE option.
+ */
+#define RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES \
+  (1u << RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES_SHIFT)
+
+/**
+ * An option to receive all beams promiscuously when \ref
+ * RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES is enabled.
+ * When true, beam frames are received regardless of their Node Id or Home Id hash
+ * resulting in \ref RAIL_EVENT_ZWAVE_BEAM (and also \ref
+ * RAIL_EVENT_RX_PACKET_ABORTED) for each beam frame.
+ *
+ * @note This option has no effect when
+ *   \ref RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES is disabled.
+ */
+#define RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE \
+  (1u << RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE_SHIFT)
+
+/** A value representing all options */
+#define RAIL_ZWAVE_OPTIONS_ALL 0xFFFFFFFFU
+
+/**
+ * @enum RAIL_ZWAVE_NodeId_t
+ * @brief A Z-Wave Node Id.
+ *
+ * This data type is 12 bits wide when using the ZWave Long Range PHY, and
+ * 8 bits wide otherwise.
+ *
+ * @note When using the Long Range PHY, values 0xFA1..0xFFE are reserved.
+ *   Otherwise, values 0xE9..0xFE are reserved.
+ */
+RAIL_ENUM_GENERIC(RAIL_ZWAVE_NodeId_t, uint16_t) {
+  /** The unknown Node Id for uninitialized nodes. */
+  RAIL_ZWAVE_NODE_ID_NONE = 0x00U,
+  /** The broadcast Node Id. */
+  RAIL_ZWAVE_NODE_ID_BROADCAST = 0xFFU,
+  /** Default to the broadcast Node Id. */
+  RAIL_ZWAVE_NODE_ID_DEFAULT = RAIL_ZWAVE_NODE_ID_BROADCAST,
+  // All other values between 0x00 and 0xFE are valid Node Ids normally
+  /** The Long Range broadcast Node Id. */
+  RAIL_ZWAVE_NODE_ID_BROADCAST_LONGRANGE = 0xFFFU,
+  /** Default to the Long Range broadcast Node Id. */
+  RAIL_ZWAVE_NODE_ID_DEFAULT_LONGRANGE = RAIL_ZWAVE_NODE_ID_BROADCAST_LONGRANGE,
+  // All values from 0x001 to 0xFA1 are valid Node Ids with a Long Range PHY.
+};
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+#define RAIL_ZWAVE_NODE_ID_NONE                ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_NONE)
+#define RAIL_ZWAVE_NODE_ID_BROADCAST           ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_BROADCAST)
+#define RAIL_ZWAVE_NODE_ID_DEFAULT             ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_DEFAULT)
+#define RAIL_ZWAVE_NODE_ID_BROADCAST_LONGRANGE ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_BROADCAST_LONGRANGE)
+#define RAIL_ZWAVE_NODE_ID_DEFAULT_LONGRANGE   ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_DEFAULT_LONGRANGE)
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/** Defines for \ref RAIL_RxPacketDetails_t::subPhyId field. */
+#define RAIL_ZWAVE_RX_SUBPHY_ID_0     (0U)
+#define RAIL_ZWAVE_RX_SUBPHY_ID_1     (1U)
+#define RAIL_ZWAVE_RX_SUBPHY_ID_2     (2U)
+#define RAIL_ZWAVE_RX_SUBPHY_ID_3     (3U)
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+/**
+ * @enum RAIL_ZWAVE_HomeId_t
+ * @brief A Z-Wave Home Id.
+ *
+ * @note Home Ids in the range 0x54000000..0x55FFFFFF are illegal.
+ */
+RAIL_ENUM_GENERIC(RAIL_ZWAVE_HomeId_t, uint32_t) {
+  /** The unknown Home Id. */
+  RAIL_ZWAVE_HOME_ID_UNKNOWN = 0x00000000U,
+  /** An impossible and unlikely Home Id. */
+  RAIL_ZWAVE_HOME_ID_DEFAULT = 0x54545454U,
+};
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+#define RAIL_ZWAVE_HOME_ID_UNKNOWN ((RAIL_ZWAVE_HomeId_t) RAIL_ZWAVE_HOME_ID_UNKNOWN)
+#define RAIL_ZWAVE_HOME_ID_DEFAULT ((RAIL_ZWAVE_HomeId_t) RAIL_ZWAVE_HOME_ID_DEFAULT)
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+/**
+ * @enum RAIL_ZWAVE_HomeIdHash_t
+ * @brief A Z-Wave Home Id hash.
+ *
+ * @note Certain values (as shown) are illegal.
+ */
+RAIL_ENUM(RAIL_ZWAVE_HomeIdHash_t) {
+  /** An illegal Home Id hash value. */
+  RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_1 = 0x0AU,
+  /** An illegal Home Id hash value. */
+  RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_2 = 0x4AU,
+  /** An illegal Home Id hash value. */
+  RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_3 = 0x55U,
+  /**
+   * Illegal Home Id hash value that suppresses checking the
+   * Home Id hash field of beam packets.
+   */
+  RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE = 0x55U,
+  /** Default to don't care. */
+  RAIL_ZWAVE_HOME_ID_HASH_DEFAULT = RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE,
+};
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+#define RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_1 ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_1)
+#define RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_2 ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_2)
+#define RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_3 ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_3)
+#define RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE)
+#define RAIL_ZWAVE_HOME_ID_HASH_DEFAULT   ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_DEFAULT)
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+/**
+ * @struct RAIL_ZWAVE_Config_t
+ * @brief A configuration structure for Z-Wave in RAIL.
+ */
+typedef struct RAIL_ZWAVE_Config {
+  /**
+   * Defines Z-Wave options.
+   */
+  RAIL_ZWAVE_Options_t options;
+  /**
+   * Defines Z-Wave Acking configuration.
+   */
+  RAIL_AutoAckConfig_t ackConfig;
+  /**
+   * Defines state timings for Z-Wave.
+   */
+  RAIL_StateTiming_t timings;
+} RAIL_ZWAVE_Config_t;
+
+/**
+ * @enum RAIL_ZWAVE_Baud_t
+ * @brief Z-Wave supported baud rates or PHYs.
+ */
+RAIL_ENUM(RAIL_ZWAVE_Baud_t) {
+  /** 9.6 kbps baud rate. */
+  RAIL_ZWAVE_BAUD_9600,
+  /** 40 kbps baud rate. */
+  RAIL_ZWAVE_BAUD_40K,
+  /** 100 kbps baud rate. */
+  RAIL_ZWAVE_BAUD_100K,
+  /** Long Range PHY. */
+  RAIL_ZWAVE_LR,
+  /** Energy detection PHY. */
+  RAIL_ZWAVE_ENERGY_DETECT = RAIL_ZWAVE_LR,
+  /** Sentinel value for invalid baud rate. Must be last. */
+  RAIL_ZWAVE_BAUD_INVALID
+};
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+#define RAIL_ZWAVE_BAUD_9600     ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_9600)
+#define RAIL_ZWAVE_BAUD_40K      ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_40K)
+#define RAIL_ZWAVE_BAUD_100K     ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_100K)
+#define RAIL_ZWAVE_LR            ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_LR)
+#define RAIL_ZWAVE_ENERGY_DETECT ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_ENERGY_DETECT)
+#define RAIL_ZWAVE_INVALID       ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_INVALID)
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/**
+ * @enum RAIL_ZWAVE_RegionOptions_t
+ * @brief Region Specific Physical
+ */
+
+RAIL_ENUM(RAIL_ZWAVE_RegionOptions_t) {
+  /** Bit shift for US Long Range 3 */
+  RAIL_ZWAVE_REGION_LONG_RANGE_3_SHIFT = 0,
+  /** Bit shift for special low side config, mostly for Japan and Korea */
+  RAIL_ZWAVE_REGION_LOW_SIDE_SHIFT = 1,
+  /** Bit shift for US long range range configurations */
+  RAIL_ZWAVE_REGION_LONG_RANGE_SHIFT = 2,
+};
+
+/**
+ * RAIL_ZWAVE_RegionOptions_t bitmasks
+ */
+/** A value representing US Long Range regions  */
+#define RAIL_ZWAVE_REGION_LONG_RANGE_MASK  (1u << RAIL_ZWAVE_REGION_LONG_RANGE_SHIFT)
+/** A value representing lowside configurations: JP and KR */
+#define RAIL_ZWAVE_REGION_LOW_SIDE_MASK (1u << RAIL_ZWAVE_REGION_LOW_SIDE_SHIFT)
+/** A value representing Long Range 3 (end device) region */
+#define RAIL_ZWAVE_REGION_LONG_RANGE_3_MASK (1u << RAIL_ZWAVE_REGION_LONG_RANGE_3_SHIFT)
+/** @deprecated Backwards compatible name. */
+#define RAIL_ZWAVE_REGION_LONG_RANGE_END_MASK RAIL_ZWAVE_REGION_LONG_RANGE_3_MASK
+/** A value representing No bit to be enabled */
+#define RAIL_ZWAVE_REGION_SPECIFIC_NONE 0u
+#endif // DOXYGEN SHOULD SKIP THIS
+
+/**
+ * Sentinel value to indicate that a channel (and thus its frequency)
+ * are invalid.
+ */
+#define RAIL_ZWAVE_FREQ_INVALID 0xFFFFFFFFUL
+
+/**
+ * @enum RAIL_ZWAVE_RegionId_t
+ * @brief Z-Wave region identifications.
+ */
+RAIL_ENUM(RAIL_ZWAVE_RegionId_t) {
+  /** Unknown/Invalid. */
+  RAIL_ZWAVE_REGIONID_UNKNOWN = 0,
+  /** European Union. */
+  RAIL_ZWAVE_REGIONID_EU = 1,
+  /** United States. */
+  RAIL_ZWAVE_REGIONID_US = 2,
+  /** Australia/New Zealand. */
+  RAIL_ZWAVE_REGIONID_ANZ = 3,
+  /** Hong Kong. */
+  RAIL_ZWAVE_REGIONID_HK = 4,
+  /** Malaysia. */
+  RAIL_ZWAVE_REGIONID_MY = 5,
+  /** India. */
+  RAIL_ZWAVE_REGIONID_IN = 6,
+  /** Japan. */
+  RAIL_ZWAVE_REGIONID_JP = 7,
+  /** Russian Federation. */
+  RAIL_ZWAVE_REGIONID_RU = 8,
+  /** Israel. */
+  RAIL_ZWAVE_REGIONID_IL = 9,
+  /** Korea. */
+  RAIL_ZWAVE_REGIONID_KR = 10,
+  /** China. */
+  RAIL_ZWAVE_REGIONID_CN = 11,
+  /** United States, with first long range PHY. */
+  RAIL_ZWAVE_REGIONID_US_LR1 = 12,
+  /** United States, with second long range PHY. */
+  RAIL_ZWAVE_REGIONID_US_LR2 = 13,
+  /** United States, with third long range PHY. */
+  RAIL_ZWAVE_REGIONID_US_LR3 = 14,
+  /** @deprecated Backwards compatible name. */
+  RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE = RAIL_ZWAVE_REGIONID_US_LR3,
+  /** European Union, with first long range PHY. */
+  RAIL_ZWAVE_REGIONID_EU_LR1 = 15,
+  /** European Union, with second long range PHY. */
+  RAIL_ZWAVE_REGIONID_EU_LR2 = 16,
+  /** European Union, with third long range PHY. */
+  RAIL_ZWAVE_REGIONID_EU_LR3 = 17,
+  /** @deprecated Backwards compatible name. */
+  RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE = RAIL_ZWAVE_REGIONID_EU_LR3,
+  /** Count of known regions. Must be last. */
+  RAIL_ZWAVE_REGIONID_COUNT
+};
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+#define RAIL_ZWAVE_REGIONID_UNKNOWN ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_UNKNOWN)
+#define RAIL_ZWAVE_REGIONID_EU      ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU)
+#define RAIL_ZWAVE_REGIONID_US      ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US)
+#define RAIL_ZWAVE_REGIONID_ANZ     ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_ANZ)
+#define RAIL_ZWAVE_REGIONID_HK      ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_HK)
+#define RAIL_ZWAVE_REGIONID_MY      ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_MY)
+#define RAIL_ZWAVE_REGIONID_IN      ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_IN)
+#define RAIL_ZWAVE_REGIONID_JP      ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_JP)
+#define RAIL_ZWAVE_REGIONID_RU      ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_RU)
+#define RAIL_ZWAVE_REGIONID_IL      ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_IL)
+#define RAIL_ZWAVE_REGIONID_KR      ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_KR)
+#define RAIL_ZWAVE_REGIONID_CN      ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_CN)
+#define RAIL_ZWAVE_REGIONID_US_LR1  ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR1)
+#define RAIL_ZWAVE_REGIONID_US_LR2  ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR2)
+#define RAIL_ZWAVE_REGIONID_US_LR3  ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR3)
+#define RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE)
+#define RAIL_ZWAVE_REGIONID_EU_LR1  ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR1)
+#define RAIL_ZWAVE_REGIONID_EU_LR2  ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR2)
+#define RAIL_ZWAVE_REGIONID_EU_LR3  ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR3)
+#define RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE)
+#define RAIL_ZWAVE_REGIONID_COUNT   ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_COUNT)
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Largest Ack timeout period based on
+// aPhyTurnaroundTimeRxTx (1 ms max)+ (aMacTransferAckTimeTX (168 bits)* (1/data rate))
+// For slowest Data Rate R1 (19.6 kbit/s)
+#define RAIL_ZWAVE_MAX_ACK_TIMEOUT_US        (9600U)
+
+// Defines for Transition timing
+#define RAIL_ZWAVE_TIME_IDLE_TO_RX_US        (100U)
+#define RAIL_ZWAVE_TIME_TX_TO_RX_US          (0U)
+#define RAIL_ZWAVE_TIME_IDLE_TO_TX_US        (0U)
+#define RAIL_ZWAVE_TIME_RX_TO_TX_US          (1000U)
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+/**
+ * Invalid beam TX power value returned when \ref RAIL_ZWAVE_GetLrBeamTxPower()
+ * is called after receiving a regular non-long-range beam.
+ */
+#define RAIL_ZWAVE_LR_BEAM_TX_POWER_INVALID  (0xFFU)
+
+/**
+ * @struct RAIL_ZWAVE_LrAckData_t
+ * @brief Configuration structure for Z-Wave Long Range Ack.
+ */
+typedef struct RAIL_ZWAVE_LrAckData {
+  /// Radio noise level measured on the channel the frame is transmitted on.
+  int8_t noiseFloorDbm;
+  /// Transmit power used to transmit the ongoing Z-Wave Long Range Ack.
+  int8_t txPowerDbm;
+  /// Signal strength measured while receiving the Z-Wave Long Range frame.
+  int8_t receiveRssiDbm;
+} RAIL_ZWAVE_LrAckData_t;
+
+/**
+ * @struct RAIL_ZWAVE_BeamRxConfig_t
+ * @brief Configuration structure for Z-Wave beam detection.
+ *
+ * @warning This structure should not be used without direct instruction
+ *   by Silicon Labs. Appropriate defaults for this are built into
+ *   the RAIL library.
+ */
+typedef struct RAIL_ZWAVE_BeamRxConfig {
+  /// Channel hopping pattern to use for beam detection.
+  RAIL_RxChannelHoppingConfig_t channelHoppingConfig;
+  /// Amount of time to spend trying to receive a beam once detected.
+  /// 100kbps only
+  RAIL_RxDutyCycleConfig_t receiveConfig_100;
+  /// Amount of time to spend trying to receive a beam once detected.
+  /// 40kbps only
+  RAIL_RxDutyCycleConfig_t receiveConfig_40;
+} RAIL_ZWAVE_BeamRxConfig_t;
+
+/**
+ * Number of channels in each of Z-Wave's region-based PHYs.
+ */
+#define RAIL_NUM_ZWAVE_CHANNELS (4U)
+
+/**
+ * @struct RAIL_ZWAVE_RegionConfig_t
+ * @brief Each Z-Wave region supports 3 channels.
+ */
+typedef struct RAIL_ZWAVE_RegionConfig {
+  /** Channel frequency in hertz. */
+  uint32_t frequency[RAIL_NUM_ZWAVE_CHANNELS];
+  /** The maximum power allowed on the channel, in dBm. */
+  RAIL_TxPower_t maxPower[RAIL_NUM_ZWAVE_CHANNELS];
+  /** Channel baud rate index. */
+  RAIL_ZWAVE_Baud_t baudRate[RAIL_NUM_ZWAVE_CHANNELS];
+  /** Identification number for the region. */
+  RAIL_ZWAVE_RegionId_t regionId;
+  /** Encapsulates region-specific options. */
+  RAIL_ZWAVE_RegionOptions_t regionSpecific;
+} RAIL_ZWAVE_RegionConfig_t;
+
+/**
+ * @struct RAIL_ZWAVE_IrcalVal_t
+ * @brief Structure for Z-Wave Image Rejection Calibration.
+ *
+ * @note Index 0 will hold the low side image rejection calibration value (channel 0),
+ *   while index 1 will hold the high side image rejection value (channel 1).
+ */
+typedef struct RAIL_ZWAVE_IrcalVal {
+  /** Low side and high side image rejection values. */
+  RAIL_IrCalValues_t imageRejection[2];
+} RAIL_ZWAVE_IrcalVal_t;
+
+/**
+ * @typedef RAIL_RxChannelHoppingParameters_t
+ * @brief Rx channel hopping on-channel time for all Z-Wave channels in a region
+ */
+typedef RAIL_RxChannelHoppingParameter_t RAIL_RxChannelHoppingParameters_t[RAIL_NUM_ZWAVE_CHANNELS];
+
+/**
+ * Switch the Z-Wave region.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] regionCfg A pointer to a Z-Wave channel configuration for the selected region.
+ * @return Status code indicating success of the function call.
+ *
+ * @note Setting a new Z-Wave Region will default any Low Power values to
+ *   Normal Power values for the region.
+ *   Z-Wave Region configuration must always be followed by a Low Power setup
+ *   in case one desires to have the Low Power Acking functionality.
+ */
+RAIL_Status_t RAIL_ZWAVE_ConfigRegion(RAIL_Handle_t railHandle,
+                                      const RAIL_ZWAVE_RegionConfig_t *regionCfg);
+
+/**
+ * Perform image rejection calibration on all valid channels of a
+ * Z-Wave region.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in,out] pIrCalVals An application-provided pointer of
+ *   type \ref RAIL_ZWAVE_IrcalVal_t. This is populated with image rejection
+ *   calibration values, if not NULL or initialized with
+ *   \ref RAIL_CAL_INVALID_VALUE or if forceIrcal is true.
+ * @param[in] forceIrcal If true, will always perform image rejection calibration
+ *   and not use previously cached values.
+ * @return Status code indicating success of the function call.
+ *
+ * @note This function also calibrates for beam detection and should be
+ *   called before \ref RAIL_ZWAVE_ReceiveBeam() and after the Z-Wave region
+ *   has been configured via \ref RAIL_ZWAVE_ConfigRegion().
+ *   Channel hopping must be disabled otherwise this function will return
+ *   \ref RAIL_STATUS_INVALID_CALL.
+ */
+RAIL_Status_t RAIL_ZWAVE_PerformIrcal(RAIL_Handle_t railHandle,
+                                      RAIL_ZWAVE_IrcalVal_t *pIrCalVals,
+                                      bool forceIrcal);
+
+/**
+ * Initialize RAIL for Z-Wave features.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] config A pointer to a Z-Wave configuration structure.
+ * @return Status code indicating success of the function call.
+ *
+ * This function is the entry point for working with Z-Wave within
+ * RAIL. It sets up relevant hardware acceleration for Z-Wave-specific
+ * features, such as Home Id filtering and beam packets (as
+ * specified in the configuration) and allows users to select the
+ * relevant Z-Wave region-specific PHY via \ref RAIL_ZWAVE_ConfigRegion().
+ */
+RAIL_Status_t RAIL_ZWAVE_Init(RAIL_Handle_t railHandle,
+                              const RAIL_ZWAVE_Config_t *config);
+
+/**
+ * De-initialize Z-Wave hardware acceleration.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Status code indicating success of the function call.
+ *
+ * Disables and resets all Z-Wave hardware acceleration features. This
+ * function should only be called when the radio is idle.
+ */
+RAIL_Status_t RAIL_ZWAVE_Deinit(RAIL_Handle_t railHandle);
+
+/**
+ * Return whether Z-Wave hardware acceleration is currently enabled.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if Z-Wave hardware acceleration was enabled to start with
+ *   and false otherwise.
+ */
+bool RAIL_ZWAVE_IsEnabled(RAIL_Handle_t railHandle);
+
+/**
+ * Configure Z-Wave options.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] mask A bitmask containing which options should be modified.
+ * @param[in] options A bitmask containing desired configuration settings.
+ *   Bit positions for each option are found in the \ref RAIL_ZWAVE_Options_t.
+ * @return Status code indicating success of the function call.
+ */
+RAIL_Status_t RAIL_ZWAVE_ConfigOptions(RAIL_Handle_t railHandle,
+                                       RAIL_ZWAVE_Options_t mask,
+                                       RAIL_ZWAVE_Options_t options);
+
+/**
+ * Inform RAIL of the Z-Wave node's Node Id for receive filtering.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] nodeId A Z-Wave Node Id.
+ * @return Status code indicating success of the function call.
+ *
+ * @note Until this API is called, RAIL will assume the Node Id is
+ *   \ref RAIL_ZWAVE_NODE_ID_DEFAULT.
+ */
+RAIL_Status_t RAIL_ZWAVE_SetNodeId(RAIL_Handle_t railHandle,
+                                   RAIL_ZWAVE_NodeId_t nodeId);
+
+/**
+ * Inform RAIL of the Z-Wave node's Home Id and its hash for receive filtering.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] homeId A Z-Wave Home Id.
+ * @param[in] homeIdHash The hash of the Home Id expected in beam frames.
+ *   If this is \ref RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE, beam frame detection
+ *   will not check the Home Id hash in a received beam frame at all, and
+ *   \ref RAIL_EVENT_ZWAVE_BEAM will trigger based solely on the Node Id
+ *   in the beam frame.
+ * @return Status code indicating success of the function call.
+ *
+ * @note Until this API is called, RAIL will assume the Home Id is an
+ *   illegal one of \ref RAIL_ZWAVE_HOME_ID_DEFAULT, and its hash is \ref
+ *   RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE.
+ */
+RAIL_Status_t RAIL_ZWAVE_SetHomeId(RAIL_Handle_t railHandle,
+                                   RAIL_ZWAVE_HomeId_t homeId,
+                                   RAIL_ZWAVE_HomeIdHash_t homeIdHash);
+
+/**
+ * Get the Node Id of the most recently seen beam frame that triggered
+ * \ref RAIL_EVENT_ZWAVE_BEAM.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[out] pNodeId A pointer to \ref RAIL_ZWAVE_NodeId_t to populate.
+ * @return Status code indicating success of the function call.
+ *
+ * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM
+ *   event; if multiple beams are received only the most recent beam's NodeId
+ *   is provided.
+ */
+RAIL_Status_t RAIL_ZWAVE_GetBeamNodeId(RAIL_Handle_t railHandle,
+                                       RAIL_ZWAVE_NodeId_t *pNodeId);
+
+/**
+ * Get the Home Id hash of the most recently seen beam frame that triggered
+ * \ref RAIL_EVENT_ZWAVE_BEAM.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[out] pBeamHomeIdHash A pointer to \ref RAIL_ZWAVE_HomeIdHash_t to populate.
+ * @return Status code indicating success of the function call.
+ *
+ * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM
+ *   event; if multiple beams are received only the most recent beam's Home Id hash
+ *   is provided.
+ */
+RAIL_Status_t RAIL_ZWAVE_GetBeamHomeIdHash(RAIL_Handle_t railHandle,
+                                           RAIL_ZWAVE_HomeIdHash_t *pBeamHomeIdHash);
+
+/**
+ * Get the channel hopping index of the most recently seen beam frame that
+ * triggered \ref RAIL_EVENT_ZWAVE_BEAM.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[out] pChannelIndex A pointer to a uint8_t to populate with
+ *   the channel hopping index. If channel-hopping was off at the time
+ *   the beam packet was received, \ref RAIL_CHANNEL_HOPPING_INVALID_INDEX
+ *   is provided.
+ * @return Status code indicating success of the function call.
+ *
+ * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM
+ *   event; if multiple beams are received only the most recent beam's
+ *   channel hopping index is provided.
+ */
+RAIL_Status_t RAIL_ZWAVE_GetBeamChannelIndex(RAIL_Handle_t railHandle,
+                                             uint8_t *pChannelIndex);
+
+/**
+ * Get the TX power used by the transmitter of the most recently seen
+ * long range beam frame that triggered \ref RAIL_EVENT_ZWAVE_BEAM.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[out] pLrBeamTxPower An application provided pointer to a uint8_t to
+ *   be populated with the TX power of the latest long range beam. This will
+ *   be set to \ref RAIL_ZWAVE_LR_BEAM_TX_POWER_INVALID if this API is called
+ *   after receiving a regular non-long-range beam.
+ * @return Status code indicating success of the function call. This function
+ *   will return \ref RAIL_STATUS_INVALID_STATE if called after receiving a
+ *   regular (non-long-range) beam.
+ *
+ * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM
+ *   event; if multiple beams are received only the most recent long range
+ *   beam's TX power is provided.
+ *
+ * @note The following table shows long range beam TX power value to dBm
+ *   value mapping:
+ *
+ * <table>
+ * <tr><th>Tx Power Value <th>Description
+ * <tr><td>0 <td>-6 dBm
+ * <tr><td>1 <td>-2 dBm
+ * <tr><td>2 <td>+2 dBm
+ * <tr><td>3 <td>+6 dBm
+ * <tr><td>4 <td>+10 dBm
+ * <tr><td>5 <td>+13 dBm
+ * <tr><td>6 <td>+16 dBm
+ * <tr><td>7 <td>+19 dBm
+ * <tr><td>8 <td>+21 dBm
+ * <tr><td>9 <td>+23 dBm
+ * <tr><td>10 <td>+25 dBm
+ * <tr><td>11 <td>+26 dBm
+ * <tr><td>12 <td>+27 dBm
+ * <tr><td>13 <td>+28 dBm
+ * <tr><td>14 <td>+29 dBm
+ * <tr><td>15 <td>+30 dBm
+ * </table>
+ */
+RAIL_Status_t RAIL_ZWAVE_GetLrBeamTxPower(RAIL_Handle_t railHandle,
+                                          uint8_t *pLrBeamTxPower);
+
+/**
+ * Get the RSSI of the received beam frame.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[out] pBeamRssi An application provided pointer to a int8_t to
+ *   be populated with the latest beam's RSSI, in dBm.
+ * @return Status code indicating success of the function call. This function
+ *  will return \ref RAIL_STATUS_INVALID_STATE if called without ever
+ *  having received a beam.
+ *
+ * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM
+ *   event; if multiple beams are received only the most recent beam's
+ *   RSSI is provided.
+ */
+RAIL_Status_t RAIL_ZWAVE_GetBeamRssi(RAIL_Handle_t railHandle,
+                                     int8_t *pBeamRssi);
+
+/**
+ * Set the Raw Low Power settings.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] powerLevel Desired low power raw level.
+ * @return Status code indicating success of the function call.
+ *
+ * Low Power settings are required during Ack transmissions when
+ * the Low Power Bit is set. This setting is only valid for one
+ * subsequent transmission, after which all transmissions will be
+ * at the nominal power setting, until re-invoked.
+ */
+RAIL_Status_t RAIL_ZWAVE_SetTxLowPower(RAIL_Handle_t railHandle,
+                                       uint8_t powerLevel);
+
+/**
+ * Set the Low Power settings in deci-dBm.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] powerLevel Desired low power level deci-dBm.
+ * @return Status code indicating success of the function call.
+ *
+ * Low Power settings are required during Ack transmissions when
+ * the Low Power Bit is set. This setting is only valid for one
+ * subsequent transmission, after which all transmissions will be
+ * at the nominal power setting, until re-invoked.
+ */
+RAIL_Status_t RAIL_ZWAVE_SetTxLowPowerDbm(RAIL_Handle_t railHandle,
+                                          RAIL_TxPower_t powerLevel);
+
+/**
+ * Get the TX low power in raw units (see \ref rail_chip_specific.h for
+ * value ranges).
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return The chip-specific \ref RAIL_TxPowerLevel_t raw value of the low
+ *   transmit power.
+ *
+ * This API returns the low raw power value that was set by
+ * \ref RAIL_ZWAVE_SetTxLowPower().
+ *
+ * Calling this function before configuring the Low Power PA
+ * (i.e., before a successful
+ * call to \ref RAIL_ZWAVE_SetTxLowPowerDbm() or \ref RAIL_ZWAVE_SetTxLowPower())
+ * will return a low power value that is the same as the nominal power.
+ * Also, calling this function before configuring the PA
+ * (i.e., before a successful call to \ref RAIL_ConfigTxPower()) will return
+ * \ref RAIL_TX_POWER_LEVEL_INVALID.
+ */
+RAIL_TxPowerLevel_t RAIL_ZWAVE_GetTxLowPower(RAIL_Handle_t railHandle);
+
+/**
+ * Get the TX low power in terms of deci-dBm instead of raw power level.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return The chip-specific \ref RAIL_TxPower_t value of the low
+ *   transmit power in deci-dBm.
+ */
+RAIL_TxPower_t RAIL_ZWAVE_GetTxLowPowerDbm(RAIL_Handle_t railHandle);
+
+/**
+ * Implement beam detection and reception algorithms.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[out] beamDetectIndex A pointer to an indicator of whether or not a beam was detected
+ *   at all, regardless of if it was received, generally for use only by instruction
+ *   from Silicon Labs. Can be NULL.
+ * @param[in] schedulerInfo A pointer to information to allow the radio scheduler to place
+ *   this operation appropriately. This is only used in multiprotocol version of
+ *   RAIL and may be set to NULL in all other versions.
+ *   Note that Z-Wave currently does not support multiprotocol, so this
+ *   scheduler info exists to future proof the API for when it does.
+ * @return Status code indicating success of the function call.
+ *   Reasons for failure include an un-idled radio or a non-Japan non-Korea
+ *   region configured before calling this function.
+ *
+ * This function takes care of all configuration and radio setup to
+ * detect and receive beams in the current Z-Wave region.
+ * If a beam is detected, RAIL will provide
+ * the usual \ref RAIL_EVENT_ZWAVE_BEAM event during which time users can
+ * process the beam as expected. However, normal packets may also be
+ * received during this time (also triggering \ref RAIL_EVENTS_RX_COMPLETION
+ * events), in which case, this API may need to be re-called to receive
+ * a beam. Users should also listen for
+ * \ref RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE, which will indicate
+ * that no beam is heard. At that point, the radio will be automatically idled.
+ * Until one of these events is received, users should not try to
+ * reconfigure radio settings or start another radio operation. If an application
+ * needs to do some other operation or configuration, it must first call
+ * \ref RAIL_Idle() and wait for the radio to idle.
+ *
+ * @note: The radio must be idle before calling this function.
+ *
+ * @note: \ref RAIL_ConfigRxChannelHopping() must have been called successfully
+ *   in Z-Wave before this function is called to provide a valid memory buffer
+ *   for internal use (see \ref RAIL_RxChannelHoppingConfig_t::buffer).
+ *
+ * @note: This function alters radio functionality substantially. After calling
+ *   it, the user should call \ref RAIL_ZWAVE_ConfigRegion(),
+ *   \ref RAIL_ConfigRxChannelHopping(), \ref RAIL_EnableRxChannelHopping(),
+ *   and \ref RAIL_SetRxTransitions() to reset these parameters to whatever
+ *   behaviors were desired before calling this function. Additionally,
+ *   this function will idle the radio upon on exit.
+ */
+RAIL_Status_t RAIL_ZWAVE_ReceiveBeam(RAIL_Handle_t railHandle,
+                                     uint8_t *beamDetectIndex,
+                                     const RAIL_SchedulerInfo_t *schedulerInfo);
+
+/**
+ * Configure the receive algorithm used in \ref RAIL_ZWAVE_ReceiveBeam().
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] config A pointer to a configuration for the beam detection algorithm.
+ * @return Status code indicating success of the function call.
+ *
+ * @warning This function should not be used without direct instruction by Silicon Labs.
+ */
+RAIL_Status_t RAIL_ZWAVE_ConfigBeamRx(RAIL_Handle_t railHandle,
+                                      RAIL_ZWAVE_BeamRxConfig_t *config);
+
+/**
+ * Set the default RX beam configuration.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Status code indicating success of the function call.
+ *
+ * @note This function resets any changes made to the beam configuration via
+ *   \ref RAIL_ZWAVE_ConfigBeamRx() and the default beam configuration will be in effect
+ *   on subsequent call(s) to \ref RAIL_ZWAVE_ReceiveBeam().
+ */
+RAIL_Status_t RAIL_ZWAVE_SetDefaultRxBeamConfig(RAIL_Handle_t railHandle);
+
+/**
+ * Get the current RX beam configuration.
+ *
+ * @param[out] pConfig A pointer to \ref RAIL_ZWAVE_BeamRxConfig_t to be
+ *   populated with the current beam configuration.
+ * @return Status code indicating success of the function call.
+ */
+RAIL_Status_t RAIL_ZWAVE_GetRxBeamConfig(RAIL_ZWAVE_BeamRxConfig_t *pConfig);
+
+/**
+ * Configure the channel hop timings for use in Z-Wave RX channel hop configuration.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in,out] config A pointer to a configuration for Z-Wave RX channel hopping.
+ *   This structure must be allocated in application global read-write memory.
+ *   RAIL will populate fields within or referenced by this structure during its
+ *   operation. Be sure to allocate \ref RAIL_RxChannelHoppingConfigEntry_t
+ *   entries[] for \ref RAIL_NUM_ZWAVE_CHANNELS. Be sure to set \ref
+ *   RAIL_RxChannelHoppingConfig_t::numberOfChannels to the desired number of
+ *   channels.
+ * @return Status code indicating success of the function call.
+ *
+ * @warning This function should not be used without direct instruction by Silicon Labs.
+ *
+ * @note: This API must be called before \ref RAIL_EnableRxChannelHopping(). This
+ *   API must never be called while the radio is on with RX Duty Cycle or Channel
+ *   Hopping enabled.
+ */
+RAIL_Status_t RAIL_ZWAVE_ConfigRxChannelHopping(RAIL_Handle_t railHandle,
+                                                RAIL_RxChannelHoppingConfig_t *config);
+
+/**
+ * Get the Z-Wave region.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return The \ref RAIL_ZWAVE_RegionId_t value.
+ *
+ * @note \ref RAIL_ZWAVE_ConfigRegion() must have been called successfully
+ *   before this function is called. Otherwise, \ref RAIL_ZWAVE_REGIONID_UNKNOWN
+ *   is returned.
+ */
+RAIL_ZWAVE_RegionId_t RAIL_ZWAVE_GetRegion(RAIL_Handle_t railHandle);
+
+/**
+ * Write the Auto-Ack FIFO for the next outgoing Z-Wave Long Range Ack.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] pLrAckData An application provided pointer to a const
+ *   \ref RAIL_ZWAVE_LrAckData_t to populate the noise floor, TX power and receive
+ *   rssi bytes of the outgoing Z-Wave Long Range Ack packet.
+ * @return Status code indicating success of the function call.
+ *
+ * This function sets the Auto-Ack data to use in acknowledging the frame
+ * being received. It must only be called while processing the \ref
+ * RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND.
+ * This will return \ref RAIL_STATUS_INVALID_STATE if it is too late to
+ * write the outgoing Ack. When successful, the ackData will
+ * only be sent once. Subsequent packets needing an Z-Wave Long Range Ack will
+ * each need to call this function to write the Ack information.
+ */
+RAIL_Status_t RAIL_ZWAVE_SetLrAckData(RAIL_Handle_t railHandle,
+                                      const RAIL_ZWAVE_LrAckData_t *pLrAckData);
+
+/** EU-European Union */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU;
+
+/** US-United States */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US;
+
+/** ANZ-Australia/New Zealand */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_ANZ;
+
+/** HK-Hong Kong */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_HK;
+
+/** MY-Malaysia */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_MY;
+
+/** IN-India */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_IN;
+
+/** JP-Japan */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_JP;
+
+/** JP-Japan Energy-Detect */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_JPED;
+
+/** RU-Russia */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_RU;
+
+/** IL-Israel */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_IL;
+
+/** KR-Korea */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_KR;
+
+/** KR-Korea Energy-Detect */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_KRED;
+
+/** CN-China */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_CN;
+
+/** US-Long Range 1 */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR1;
+
+/** US-Long Range 2 */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR2;
+
+/** US-Long Range 3 */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR3;
+/** Backwards-compatible define */
+#define RAIL_ZWAVE_REGION_US_LR_END_DEVICE RAIL_ZWAVE_REGION_US_LR3
+
+/** EU-Long Range 1 */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR1;
+
+/** EU-Long Range 2 */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR2;
+
+/** EU-Long Range 3 */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR3;
+/** Backwards-compatible define */
+#define RAIL_ZWAVE_REGION_EU_LR_END_DEVICE RAIL_ZWAVE_REGION_EU_LR3
+
+/** Invalid Region */
+extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_INVALID;
+
+/** @} */ // end of Z_Wave
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __RAIL_ZWAVE_H__

Libs/platform/security/sl_component/se_manager/inc/sl_se_manager.h

@@ -0,0 +1,458 @@
+/***************************************************************************//**
+ * @file
+ * @brief Silicon Labs Secure Engine Manager API.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifndef SL_SE_MANAGER_H
+#define SL_SE_MANAGER_H
+
+#include "sli_se_manager_features.h"
+#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED)
+
+/***************************************************************************//**
+ * @addtogroup sl_se_manager SE Manager
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup sl_se_manager_core Core
+ *
+ * @brief
+ *   Secure Engine Manager Core API
+ *
+ * @details
+ *   API for initialization of SE Manager and SE command context with yield
+ *   attribute.
+ *
+ * @{
+ ******************************************************************************/
+
+#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
+  #include "sl_se_manager_key_handling.h"
+  #include "sl_se_manager_cipher.h"
+#endif // SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT
+#include "sl_se_manager_types.h"
+
+#include "sli_se_manager_mailbox.h"
+#include "sl_status.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// -----------------------------------------------------------------------------
+// Prototypes
+
+/***************************************************************************//**
+ * @brief
+ *   Initialize the SE Manager.
+ *
+ * @details
+ *   Initialize the SE Manager by checking hardware availability and setting up
+ *   internal module specific resources like mutexes etc.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_init(void);
+
+/***************************************************************************//**
+ * @brief
+ *   Denitialize the SE Manager.
+ *
+ * @details
+ *   Free resources held by the SE Manager.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_deinit(void);
+
+#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT)
+/***************************************************************************//**
+ * @brief
+ *   Set the yield attribute of the SE command context object.
+ *
+ * @param[in,out] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[in] yield
+ *   The user may set this parameter to true in order to tell the SE Manager
+ *   to yield the cpu core while waiting for the SE mailbox command to complete.
+ *   If false, the SE Manager will busy-wait, by polling the SE mailbox response
+ *   register until the SE mailbox command completes.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_set_yield(sl_se_command_context_t *cmd_ctx,
+                            bool yield);
+#endif // !SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT
+
+#if defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED)
+/***************************************************************************//**
+ * @brief
+ *   From VSE mailbox read which command, if any, was executed.
+ *
+ * @param[in,out] cmd_ctx
+ *   Pointer to an SE command context object. If this function returns
+ *   SL_STATUS_OK the command word of the SE command context object will be set.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_read_executed_command(sl_se_command_context_t *cmd_ctx);
+
+/***************************************************************************//**
+ * @brief
+ *   Acknowledge and get status and output data of a completed command.
+ *
+ * @details
+ *   This function acknowledges and gets the status and output data of a
+ *   completed mailbox command. The acknowledge operation invalidates the
+ *   contents of the output mailbox. The output data is copied into the linked
+ *   list of output buffers pointed to in the given command data structure.
+ *
+ * @param[in,out] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_ack_command(sl_se_command_context_t *cmd_ctx);
+#endif //defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED)
+
+/***************************************************************************//**
+ * @brief
+ *   Initialize an SE command context object
+ *
+ * @details
+ *   Initialize an SE command context which can be used in subsequent calls to
+ *   the SE Manager API in order to execute SE mailbox commands.
+ *
+ * @param[in,out] cmd_ctx
+ *   Pointer to an SE command context object to be initialized. This context
+ *   object should be used in subsequent calls to the SE Manager API in order
+ *   to execute SE mailbox commands. The same command context object cannot be
+ *   used concurrently, e.g. by two different threads. However a command context
+ *   object may be reused for the next and any subsequent mailbox operatons,
+ *   except when streaming commands are in progress in which case only streaming
+ *   commands of the same operation type is allowed until the streaming operation
+ *   is finished (i.e. the corresponding sl_se_xxx_finish is called).
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_init_command_context(sl_se_command_context_t *cmd_ctx);
+
+/***************************************************************************//**
+ * @brief
+ *   De-initialize an SE command context
+ *
+ * @details
+ *   De-initialize an SE command context object.
+ *
+ * @param[in,out] cmd_ctx
+ *   Pointer to an SE command context object to deinitialize.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_deinit_command_context(sl_se_command_context_t *cmd_ctx);
+
+#ifdef __cplusplus
+}
+#endif
+
+/// @} (end addtogroup sl_se_manager_core)
+/// @} (end addtogroup sl_se_manager)
+
+#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED)
+
+#endif // SL_SE_MANAGER_H
+
+// THE REST OF THE FILE IS DOCUMENTATION ONLY
+/// @addtogroup sl_se_manager
+/// @{
+/// @details
+///
+/// The Secure Engine (SE) Manager provides thread-safe APIs for the Secure Engine's mailbox interface. Note that PSA Crypto is the recommended device independent crypto API and should be used
+/// whenever possible. The SE manager APIs can be used directly for performance or space constrained applications.
+///
+/// Available functionality will vary between devices: device management, such as secure firmware upgrade, secure boot and secure debug implementation, is available on all series 2 devices.
+/// Devices with the SE subsystem includes a low level crypto API where the SE Manager will use the SE hardware peripherals to accelerate cryptographic operations. Finally, Vault High
+/// devices also include secure key storage functionality, anti-tamper protection, advanced crypto API and attestation.
+///
+/// @note Below are some of the useful application notes linked with Secure Engine Manager:\n
+/// - <a href="https://www.silabs.com/documents/public/application-notes/an1190-efr32-secure-debug.pdf">AN1190: Series 2 Secure Debug</a>\n
+/// - <a href="https://www.silabs.com/documents/public/application-notes/an1247-efr32-secure-vault-tamper.pdf">AN1247: Anti-Tamper Protection Configuration and Use</a>\n
+/// - <a href="https://www.silabs.com/documents/public/application-notes/an1268-efr32-secure-identity.pdf">AN1268: Authenticating Silicon Labs Devices Using Device Certificates</a>\n
+/// - <a href="https://www.silabs.com/documents/public/application-notes/an1271-efr32-secure-key-storage.pdf">AN1271: Secure Key Storage</a>\n
+/// - <a href="https://www.silabs.com/documents/public/application-notes/an1218-secure-boot-with-rtsl.pdf">AN1218: Series 2 Secure Boot with RTSL</a>\n
+///
+/// # Functionality
+///
+/// The functionality of the SE Manager includes
+///
+/// - Core API, inititalizing of SE Manager and SE command context (@ref sl_se_manager_core)
+/// - Secure key storage (@ref sl_se_manager_key_handling)
+///     - Key wrapping
+///     - Storing keys in the SE volatile storage
+///     - Using key by reference
+/// - Configuration of tamper responses (@ref sl_se_manager_util)
+///     - The available signals include core hard-fault, glitch detectors, PRS, and failed authenticated commands,
+///       while the responses vary from triggering an interrupt to the hardware autonomously erasing the one-time-programmable (OTP) memory
+/// - Block ciphers (@ref sl_se_manager_cipher)
+///     - Supports AES-ECB, AES-CBC, AES-CFB128, AES-CFB8, AES-CTR, AES-CCM, AES-GCM, CMAC, HMAC and ChaCha20/Poly1305
+///     - The cipher operations can be performed using plaintext keys, wrapped keys or referencing a key in the SE
+///     - Streaming operations are supported for AES-GCM and CMAC
+/// - Block and streaming hash operations (@ref sl_se_manager_hash)
+///     - Supports SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512
+/// - True Random Number Generator (@ref sl_se_manager_entropy)
+///     - Hardware block inside the SE used for generating random numbers. Can be used as a source of entropy, or to securely generate keys inside the SE
+/// - Elliptic Curve Signature operation (@ref sl_se_manager_signature)
+///     - ECDSA and EDDSA
+/// - Key agreement (@ref sl_se_manager_key_derivation)
+///     - Perform Elliptic Curve Diffie-Hellman and J-PAKE key agreement operations inside the SE
+/// - Key derivation functions (@ref sl_se_manager_key_derivation)
+///     - Perform HKDF and PBKDF2 key derivation functions inside the SE
+/// - Device configuration and utilities (@ref sl_se_manager_util)
+///     - Write to user data stored inside the SE
+///     - Configuration of debug locks
+///     - Configuration of secure boot
+///     - Configuration of flash lock
+///     - Read SE OTP contents
+///     - Read SE firmware version
+///     - Read provisioned certificates
+/// - Multi-thread safe APIs for MicriumOS and FreeRTOS
+/// - Retrieveing attestation tokens (@ref sl_se_manager_attestation)
+///
+/// ## Key Storage and Use of SE Wrapped Keys
+///
+/// The way keys are stored and operated on depends on the options set in the key descriptor used (@ref sl_se_key_descriptor_t).
+/// Each key descriptor is initialized with a storage location, a key type, and length of the key (some key types have a known length, and it is not required to be set).
+/// The storage location can either be application memory or inside the SE, for more details, see @ref sl_se_storage_method_t.
+/// Depending on the use-case, the key descriptors will also store the pointer to a key and an SE key slot, see @ref sl_se_key_slot_t for the list of available internal SE key slots.
+///
+/// For more information on the key handling APIs see @ref sl_se_manager_key_handling.
+///
+/// ### Supported Key Types
+/// Symmetric keys
+/// - AES-128 (16 bytes)
+/// - AES-192 (24 bytes)
+/// - AES-256 (32 bytes)
+/// - ChaCha20 (32 bytes)
+///
+/// Asymmetric keys for ECC
+/// - NIST P-192
+/// - NIST P-256
+/// - NIST P-384
+/// - NIST P-521
+/// - Curve25519
+/// - Curve448
+///
+/// Custom Weierstrass Prime curves are also supported (@ref sl_se_custom_weierstrass_prime_domain_t).
+///
+/// ### Example Usage of Keys
+///
+/// @code{.c}
+///     #define WRAPPED_KEY_OVERHEAD (12UL + 16UL)
+///     #define AES_256_KEY_SIZE 32UL
+///
+///     uint8_t key_buffer[AES_256_KEY_SIZE];
+///     uint8_t wrapped_key_buffer[AES_256_KEY_SIZE + WRAPPED_KEY_OVERHEAD];
+///
+///     void demo_se_create_key_in_slot(void) {
+///         sl_se_key_descriptor_t new_key = {
+///             .type = SL_SE_KEY_TYPE_AES_256,
+///             .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE,
+///             .storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE,
+///             .storage.location.slot = SL_SE_KEY_SLOT_VOLATILE_0,
+///         };
+///         sl_se_generate_key(&new_key);
+///     }
+///
+///     void demo_se_create_plaintext_key(void) {
+///         sl_se_key_descriptor_t new_key = {
+///             .type = SL_SE_KEY_TYPE_AES_256,
+///             .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT,
+///         };
+///         new_key.storage.location.buffer.pointer = key_buffer;
+///         new_key.storage.location.buffer.size = sizeof(key_buffer);
+///         sl_se_generate_key(&new_key);
+///     }
+///
+///     void demo_se_create_wrapped_key(void) {
+///         sl_se_key_descriptor_t new_wrapped_key = {
+///             .type = SL_SE_KEY_TYPE_AES_256,
+///             .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE,
+///             .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED,
+///         };
+///         new_wrapped_key.storage.location.buffer.pointer = wrapped_key_buffer;
+///         new_wrapped_key.storage.location.buffer.size = sizeof(wrapped_key_buffer);
+///         sl_se_generate_key(&new_wrapped_key);
+///     }
+///
+///     void demo_se_wrapped_key_to_volatile_slot(void) {
+///         sl_se_key_descriptor_t existing_wrapped_key = {
+///             .type = SL_SE_KEY_TYPE_AES_256,
+///             .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE,
+///             .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED,
+///         };
+///         existing_wrapped_key.storage.location.buffer.pointer = wrapped_key_buffer;
+///         existing_wrapped_key.storage.location.buffer.size = sizeof(wrapped_key_buffer);
+///         sl_se_key_descriptor_t key_in_slot = {
+///             .type = SL_SE_KEY_TYPE_AES_256,
+///             .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE,
+///             .storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE,
+///             .storage.location.slot = SL_SE_KEY_SLOT_VOLATILE_0,
+///         };
+///         sl_se_import_key(&existing_wrapped_key, &key_in_slot);
+///     }
+///
+///     void demo_se_volatile_slot_to_wrapped_key(void) {
+///         sl_se_key_descriptor_t existing_volatile_key = {
+///             .type = SL_SE_KEY_TYPE_AES_256,
+///             .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE,
+///             .storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE,
+///             .storage.location.slot = SL_SE_KEY_SLOT_VOLATILE_0,
+///         };
+///         sl_se_key_descriptor_t wrapped_key_out = {
+///             .type = SL_SE_KEY_TYPE_AES_256,
+///             .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE,
+///             .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED,
+///         };
+///         wrapped_key_out.storage.location.buffer.pointer = wrapped_key_buffer;
+///         wrapped_key_out.storage.location.buffer.size = sizeof(wrapped_key_buffer);
+///         sl_se_export_key(&existing_volatile_key, &wrapped_key_out);
+///     }
+///
+///     void demo_se_delete_from_volatile_slot(void) {
+///         sl_se_key_descriptor_t existing_volatile_key = {
+///             .type = SL_SE_KEY_TYPE_AES_256,
+///             .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE,
+///             .storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE,
+///             .storage.location.slot = SL_SE_KEY_SLOT_VOLATILE_0,
+///         };
+///         sl_se_delete_key(&existing_volatile_key);
+///     }
+/// @endcode
+///
+/// ## Tamper
+///
+/// The Secure Engine (SE) tamper module connects a number of hardware and software-driven tamper signals to a set of configurable hardware and software responses.
+/// This can be used to program the device to automatically respond to external events that could signal that someone is trying to tamper with the device,
+/// and very rapidly remove secrets stored in the SE. The available tamper signals range from signals based on failed authentication and secure boot to specialized glitch detectors.
+/// When any of these signals fire, the tamper block can be configured to trigger several different responses,
+/// ranging from triggering an interrupt to erasing the one-time-programmable (OTP) memory, removing all SE secrets and resulting in a permanently destroyed device.
+///
+/// A tamper signal can lead to a series of different autonomous responses from the tamper module. These responses are listed in the table below.
+/// |       | Response  | Description  |
+/// | ----: | :----:    | :---- |
+/// | 0     | Ignore    | No action is taken.    |
+/// | 1     | Interrupt | The SETAMPERHOST interrupt on the host is triggered.    |
+/// | 2     | Filter    | A counter in the tamper filter is increased.    |
+/// | 4     | Reset     | The device is reset.    |
+/// | 7     | Erase OTP | Erases the OTP configuration of the device.    |
+///
+/// These responses are cumulative, meaning that if a filter response is triggered, an interrupt will also be triggered. For a full overview of the tamper signals, see @ref sl_se_manager_defines.h.
+///
+/// The tamper configuration is one-time-programmable, and is done using the initialise OTP command to the SE (see @ref sl_se_init_otp).
+/// This means that tamper settings must be written together with secure boot settings, and are immutable after they are written.
+/// After tamper has been initialized, it is possible to temporarily disable one or several tamper signals using an authenticated command,
+/// similar to secure debug unlock. This is only possible if the debug public key has been installed on the device.
+/// It is only possible to disable the customer enabled response. The default response to a signal cannot be disabled.
+///
+/// Tamper is configured by providing the following:
+/// <table>
+/// <caption id="multi_row">Tamper configuration table</caption>
+/// <tr><th>Setting                       <th>Description
+/// <tr><td>Tamper response levels        <td>A response level for each tamper signal.\n\n It is not possible to degrade the default response level of a tamper signal, so if a response is set to a lower level than the default response level listed in the table in the Signals section, this won't have any effect.
+/// <tr><td>Filter settings               <td>The tamper filter counter has two settings:
+///                                                                       <ul>
+///                                                                         <li>Reset period
+///                                                                         <li>Trigger threshold
+///                                                                       </ul>
+///                                                                   These options can be set to the values given in the tables in the Response Filter section. Please see the examples section for a suggested use of the tamper filter signal.
+/// <tr><td>Flags                                         <td>The tamper flags is used to configure two options:
+///                                                                       <ul>
+///                                                                         <li>Digital Glitch Detector Always On – This option will keep the digital glitch detector running even while the SE is not performing any operations. This leads to increased energy consumption.
+///                                                                         <li>Keep Tamper Alive During Sleep (not available on EFR32xG21B devices) – If set, the tamper module keeps running at sleep mode (down to EM3).
+///                                                                       </ul>
+/// <tr><td>Reset threshold                       <td>The number of consecutive tamper resets before the the part enters debug mode.\n\n
+///                                                                           If the threshold is set to 0, the part will never enter the debug mode due to tamper reset.
+/// </table>
+///
+/// ### Example Usage
+///
+/// The glitch detectors can see spurious activations, and should typically not be used to directly drive a serious tamper response.
+/// Instead they should feed their signals into a tamper interrupt (to handle the response logic on the M33), or into the tamper filter counter,
+/// which can be used to activate a high level response if a number of incidents occur in a short time window.
+/// The time period and counter threshold must be tuned to the use case. In the following example the device will erase OTP and become inoperable if 4 glitch signals is seen in a 1 minute time period.
+///
+/// Since you can only configure tamper once for each device, please make sure that this is the configuration you actually want before you execute this example on actual device.
+///
+/// @code{.c}
+///     sl_se_otp_init_t otp_settings_init = SL_SE_OTP_INIT_DEFAULT;
+///
+///     // Configure tamper levels
+///     otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_FILTER] = SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP;
+///     otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_VGLITCHFALLING] = SL_SE_TAMPER_LEVEL_FILTER;
+///     otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_VGLITCHRISING] = SL_SE_TAMPER_LEVEL_FILTER;
+///     otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_DGLITCH] = SL_SE_TAMPER_LEVEL_FILTER;
+///
+///
+///     // Configure tamper filter options
+///     otp_settings_init.tamper_filter_period = SL_SE_TAMPER_FILTER_PERIOD_1MIN;
+///     otp_settings_init.tamper_filter_threshold = SL_SE_TAMPER_FILTER_THRESHOLD_4;
+///
+///
+///     // Commit OTP settings. This command is only available once!
+///     sl_se_init_otp(&otp_settings_init);
+/// @endcode
+///
+/// ## RTOS Mode and Multi-Thread Safety
+///
+/// @note The SE Manager API is multi-thread safe, but does not support preemption.
+///       This means the API cannot be called from ISR or critical/atomic sections when running in an RTOS thread.
+///       When using the SE Manager API in a bare-metal application, it is the application developer's responsibility
+///       to not call the SE Manager APIs when another operation is in progress.
+///
+/// The SE Manager supports multi-thread safe APIs for MicriumOS and FreeRTOS interfacing with CMSIS RTOS2 APIs.
+///
+/// In the cases where Micrium OS or FreeRTOS are included in the project (RTOS-mode), the SE Manager will be configured with threading and yield support.
+/// Configure ::sl_se_command_context_t with ::sl_se_set_yield to yield the CPU core when the SE Manager is waiting for the Secure Engine to complete a mailbox command.
+///
+/// For threading support the SE Manager applies an SE lock mechanism to protect the Secure Engine Mailbox interface from being accessed by more than one thread,
+/// ensuring multi-thread safety. For yielding the CPU core while waiting for the SE, the SE Manager APIs that invoke
+/// SE mailbox commands will wait on a semaphore which is signaled in the ISR that handles the SE mailbox completion interrupt.
+/// Hence other threads may run on the CPU core while the SE is processing the mailbox command.
+///
+/// @} (end addtogroup sl_se_manager)

Libs/platform/security/sl_component/se_manager/inc/sl_se_manager_attestation.h

@@ -0,0 +1,209 @@
+/***************************************************************************//**
+ * @file
+ * @brief Silicon Labs Secure Engine Manager API.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifndef SL_SE_MANAGER_ATTESTATION_H
+#define SL_SE_MANAGER_ATTESTATION_H
+
+#include "sli_se_manager_features.h"
+
+#if (defined(SLI_MAILBOX_COMMAND_SUPPORTED) \
+  && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT))
+
+/// @addtogroup sl_se_manager
+/// @{
+
+/***************************************************************************//**
+ * @addtogroup sl_se_manager_attestation Attestation
+ *
+ * @brief
+ *   System and configuration attestation
+ *
+ * @details
+ *   API for retrieveing attestation tokens from the SE.
+ *
+ * @{
+ ******************************************************************************/
+
+#include "sl_se_manager_key_handling.h"
+#include "sl_se_manager_types.h"
+#include "sli_se_manager_mailbox.h"
+#include "sl_status.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// -----------------------------------------------------------------------------
+// Defines
+
+/// 32 byte challenge size
+#define SL_SE_ATTESTATION_CHALLENGE_SIZE_32  (32U)
+/// 48 byte challenge size
+#define SL_SE_ATTESTATION_CHALLENGE_SIZE_48  (48U)
+/// 64 byte challenge size
+#define SL_SE_ATTESTATION_CHALLENGE_SIZE_64  (64U)
+
+// -----------------------------------------------------------------------------
+// Prototypes
+
+/***************************************************************************//**
+ * @brief
+ *   Get the PSA initial attest token from the SE
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[in] auth_challenge
+ *   Buffer with a challenge object selected by the caller.
+ *
+ * @param[in] challenge_size
+ *   Size of the challenge object in bytes. Must be either 32, 48 or 64.
+ *
+ * @param[out] token_buf
+ *   Buffer where the output token will be stored.
+ *
+ * @param[in] token_buf_size
+ *   Size of token_buf in bytes. Must be at least the size found by calling
+ *   \ref sl_se_attestation_get_psa_iat_token_size with equivalent arguments,
+ *   and padded to word alignment.
+ *
+ * @param[out] token_size
+ *   Number of bytes actually used in token_buf.
+ *
+ * @warning
+ *   Once a nonce/challenge has been used, the same challenge should not be used
+ *   ever again, to prevent replay attacks.
+ *
+ * @warning
+ *   The output will be length-extended to the next word-multiple.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_attestation_get_psa_iat_token(sl_se_command_context_t *cmd_ctx,
+                                                const uint8_t *auth_challenge,
+                                                size_t challenge_size,
+                                                uint8_t *token_buf,
+                                                size_t token_buf_size,
+                                                size_t *token_size);
+
+/***************************************************************************//**
+ * @brief
+ *   Get the size of a PSA initial attest token with the given nonce
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[in] challenge_size
+ *   Size of the challenge object in bytes. Must be either 32, 48 or 64.
+ *
+ * @param[out] token_size
+ *   Pointer to output word. Result is stored here.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_attestation_get_psa_iat_token_size(sl_se_command_context_t *cmd_ctx,
+                                                     size_t challenge_size,
+                                                     size_t *token_size);
+
+/***************************************************************************//**
+ * @brief
+ *    Get an attested (signed) security configuration token from the SE
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[in] auth_challenge
+ *   Buffer with a challenge object selected by the caller.
+ *
+ * @param[in] challenge_size
+ *   Size of the challenge object in bytes. Must be 32.
+ *
+ * @param[out] token_buf
+ *   Buffer where the output token will be stored.
+ *
+ * @param[in] token_buf_size
+ *   Size of token_buf in bytes. Must be at least the size found by calling
+ *   \ref sl_se_attestation_get_config_token_size with equivalent arguments,
+ *   and padded to word alignment.
+ *
+ * @param[out] token_size
+ *   Number of bytes actually used in token_buf.
+ *
+ * @warning
+ *   Once a nonce/challenge has been used, the same challenge should not be used
+ *   ever again, to prevent replay attacks.
+ *
+ * @warning
+ *   The output will be length-extended to the next word-multiple.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_attestation_get_config_token(sl_se_command_context_t *cmd_ctx,
+                                               const uint8_t *auth_challenge,
+                                               size_t challenge_size,
+                                               uint8_t *token_buf,
+                                               size_t token_buf_size,
+                                               size_t *token_size);
+
+/***************************************************************************//**
+ * @brief
+ *    Get the size of a security configuration token
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[in] challenge_size
+ *   Size of the challenge object in bytes. Must be 32.
+ *
+ * @param[out] token_size
+ *   Pointer to output word. Result is stored here.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_attestation_get_config_token_size(sl_se_command_context_t *cmd_ctx,
+                                                    size_t challenge_size,
+                                                    size_t *token_size);
+
+#ifdef __cplusplus
+}
+#endif
+
+/// @} (end addtogroup sl_se_manager_attestation)
+/// @} (end addtogroup sl_se_manager)
+
+#endif // SLI_MAILBOX_COMMAND_SUPPORTED && VAULT
+
+#endif // SL_SE_MANAGER_ATTESTATION_H

Libs/platform/security/sl_component/se_manager/inc/sl_se_manager_check_config.h

@@ -0,0 +1,61 @@
+/**************************************************************************/ /**
+ * @file
+ * @brief Consistency checks for SE Manager configuration options
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SL_SE_MANAGER_CHECK_CONFIG_H
+#define SL_SE_MANAGER_CHECK_CONFIG_H
+
+#if defined (SL_COMPONENT_CATALOG_PRESENT)
+#include "sl_component_catalog.h"
+#endif
+
+#if defined(SL_SE_MANAGER_THREADING)                                    \
+  && !defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) \
+  && !defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED)
+#error "Yield when waiting for SE commands to finish is currently required in RTOS mode."
+#endif
+#if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) \
+  && !defined(SL_SE_MANAGER_THREADING)
+#error "Yield when waiting for SE commands to finish currently requires RTOS mode. I.e. yield support is not available in bare metal mode."
+#endif
+
+#if (defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) || defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT)) \
+  && !defined(SL_SE_MANAGER_THREADING)
+#error "RTOS requires threading mode."
+#endif
+
+#if (defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) && defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION))
+#error "Yield support is not available on EFR32xG22 devices"
+#endif
+
+#if (SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED != 1)
+#error "Using multiple blocks for key stream computation is not supported"
+#endif
+
+#endif // SL_SE_MANAGER_CHECK_CONFIG_H

Libs/platform/security/sl_component/se_manager/inc/sl_se_manager_config.h

@@ -0,0 +1,63 @@
+/**************************************************************************/ /**
+ * @file
+ * @brief SE Manager configuration options
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SL_SE_MANAGER_CONFIG_H
+#define SL_SE_MANAGER_CONFIG_H
+
+/// This file include the configuration options of the SE Manager.
+/// For the time being the user should not change the default settings
+/// of the configuration options in this file.
+
+#if defined (SL_COMPONENT_CATALOG_PRESENT)
+  #include "sl_component_catalog.h"
+#endif
+
+#if defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) || defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT)
+// Threading support (as opposed to API calls only from a single thread)
+// is currently required in RTOS mode.
+  #define SL_SE_MANAGER_THREADING
+
+  #if !defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) && !defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED)
+// Enable yield support. Configure sl_se_command_context_t to yield CPU while waiting for SE commands.
+// This is not supported on EFR32xG22.
+    #define SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION
+  #endif
+#endif
+
+#ifndef SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED
+  #define SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED 1
+#endif
+
+// Check consistency of configuration options.
+// Always include se_manager_check_config.h in order to assert that the
+// configuration options dependencies and restrictions are ok.
+#include "sl_se_manager_check_config.h"
+
+#endif // SL_SE_MANAGER_CONFIG_H

Libs/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h

@@ -0,0 +1,533 @@
+/***************************************************************************//**
+ * @file
+ * @brief Silicon Labs Secure Engine Manager API definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifndef SL_SE_MANAGER_DEFINES_H
+#define SL_SE_MANAGER_DEFINES_H
+
+#include "sli_se_manager_features.h"
+
+#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED)
+
+#if !defined(SLI_SE_MANAGER_HOST_SYSTEM)
+#if !defined(SL_TRUSTZONE_NONSECURE)
+#if !defined(SE_MANAGER_CONFIG_FILE)
+#include "sl_se_manager_config.h"
+#else
+#include SE_MANAGER_CONFIG_FILE
+#endif // SE_MANAGER_CONFIG_FILE
+#endif // SL_TRUSTZONE_NONSECURE
+#endif // SLI_SE_MANAGER_HOST_SYSTEM
+
+#if defined (SL_COMPONENT_CATALOG_PRESENT)
+  #include "sl_component_catalog.h"
+#endif
+
+/// @addtogroup sl_se_manager
+/// @{
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// -----------------------------------------------------------------------------
+// Defines
+
+/// @addtogroup sl_se_manager_core
+/// @{
+
+/// Context initialization values. Some of the context values are not fully
+/// initialized. The user will need to call the corresponding initialization
+/// function in order to fully initialize the context objects for further use
+/// in the SE Manager API. The purpose of these initialization values is to set
+/// the context objects to a known safe state initially when the context object
+/// is declared.
+#define SL_SE_COMMAND_CONTEXT_INIT           { SLI_SE_MAILBOX_COMMAND_DEFAULT(0), false }
+
+/// @} (end addtogroup sl_se_manager_core)
+
+/// @addtogroup sl_se_manager_util
+/// @{
+
+/// Default configuration for OTP initialisation structure.
+#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)
+  #define SL_SE_OTP_INIT_DEFAULT                                \
+  {                                                             \
+    .enable_secure_boot = false,                                \
+    .verify_secure_boot_certificate = false,                    \
+    .enable_anti_rollback = false,                              \
+    .secure_boot_page_lock_narrow = false,                      \
+    .secure_boot_page_lock_full = false,                        \
+    .tamper_levels = { 0 },                                     \
+    .tamper_filter_period = SL_SE_TAMPER_FILTER_PERIOD_2MIN,    \
+    .tamper_filter_threshold = SL_SE_TAMPER_FILTER_THRESHOLD_4, \
+    .tamper_flags = 0,                                          \
+    .tamper_reset_threshold = 5                                 \
+  }
+#else
+  #define SL_SE_OTP_INIT_DEFAULT             \
+  {                                          \
+    .enable_secure_boot = false,             \
+    .verify_secure_boot_certificate = false, \
+    .enable_anti_rollback = false,           \
+    .secure_boot_page_lock_narrow = false,   \
+    .secure_boot_page_lock_full = false      \
+  }
+#endif
+
+/// @} (end addtogroup sl_se_manager_util)
+
+#if defined(SLI_MAILBOX_COMMAND_SUPPORTED)
+// -------------------------------
+// Defines for SE functionality
+
+/// @addtogroup sl_se_manager_key_handling
+/// @{
+
+/// Asymmetric key can only be used for signing (not key exchange)
+#define SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY (1UL << 10)
+/// Described key belongs to a custom ECC domain
+#define SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN (1UL << 12)
+/// Storage buffer contains public part of an asymmetric key
+#define SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY (1UL << 13)
+/// Storage buffer contains private part of an asymmetric key
+#define SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY (1UL << 14)
+/// Allow usage of this key by other bus masters or TrustZone levels than the
+/// one which created/imported the key
+#define SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS (1UL << 15)
+/// Old definition. Retained for backwards compatibility.
+#define SL_SE_KEY_FLAG_ASYMMMETRIC_SIGNING_ONLY \
+  (SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY)
+
+/// Do not allow exporting the key to plaintext
+#define SL_SE_KEY_FLAG_NON_EXPORTABLE (1UL << 24)
+/// Indicate that the key has been generated by this device. This flag is only
+/// valid when using the SE to generate a key and makes it non-exportable.
+#define SL_SE_KEY_FLAG_IS_DEVICE_GENERATED (1UL << 25)
+/// Indicate that the key can only be used to sign SE generated content. This
+/// flag is only valid when using the SE to generate a key and makes it
+/// non-exportable.
+#define SL_SE_KEY_FLAG_IS_RESTRICTED (1UL << 25 | 1UL << 24)
+
+/// Mask for algorithm field in key type
+#define SL_SE_KEY_TYPE_ALGORITHM_MASK       0xf0000000
+/// Offset of algorithm field in key type
+#define SL_SE_KEY_TYPE_ALGORITHM_OFFSET     28
+/// Mask for attributes field in key type
+#define SL_SE_KEY_TYPE_ATTRIBUTES_MASK      0x00007fff
+/// Offset of attributes field in key type
+#define SL_SE_KEY_TYPE_ATTRIBUTES_OFFSET    0
+
+/// Symmetric key type
+#define SL_SE_KEY_TYPE_SYMMETRIC    0x00000000
+/// Symmetric key type for AES-128 (16 byte key)
+#define SL_SE_KEY_TYPE_AES_128      0x00000010
+/// Symmetric key type for AES-192 (24 byte key)
+#define SL_SE_KEY_TYPE_AES_192      0x00000018
+/// Symmetric key type for AES-256 (32 byte key)
+#define SL_SE_KEY_TYPE_AES_256      0x00000020
+
+/// ECC Weierstrass Prime key type
+#define SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM     (0x8U << SL_SE_KEY_TYPE_ALGORITHM_OFFSET)
+/// ECC Montgomery key type
+#define SL_SE_KEY_TYPE_ECC_MONTGOMERY                   (0xbU << SL_SE_KEY_TYPE_ALGORITHM_OFFSET)
+/// EDDSA key type
+#define SL_SE_KEY_TYPE_ECC_EDDSA                        (0xcU << SL_SE_KEY_TYPE_ALGORITHM_OFFSET)
+
+/// ECC NIST P-192
+#define SL_SE_KEY_TYPE_ECC_P192     (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x18))
+/// ECC NIST P-224
+#define SL_SE_KEY_TYPE_ECC_P224     (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x1C))
+/// ECC NIST P-256
+#define SL_SE_KEY_TYPE_ECC_P256     (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x20))
+
+/// ECC Ed25519 key for EdDSA
+#define SL_SE_KEY_TYPE_ECC_ED25519  (SL_SE_KEY_TYPE_ECC_EDDSA | (0x20))
+
+/// ECC X25519 key for ECDH
+#define SL_SE_KEY_TYPE_ECC_X25519   (SL_SE_KEY_TYPE_ECC_MONTGOMERY | (0x20))
+
+#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)
+/// Symmetric key type for ChaCha20
+  #define SL_SE_KEY_TYPE_CHACHA20     0x00000020
+
+/// ECC NIST P-384
+  #define SL_SE_KEY_TYPE_ECC_P384     (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x30))
+/// ECC NIST P-521
+  #define SL_SE_KEY_TYPE_ECC_P521     (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x42))
+
+/// ECC X448 key for ECDH
+  #define SL_SE_KEY_TYPE_ECC_X448     (SL_SE_KEY_TYPE_ECC_MONTGOMERY | (0x38))
+
+/// ECC Ed448 key for EdDSA
+  #define SL_SE_KEY_TYPE_ECC_ED448    (SL_SE_KEY_TYPE_ECC_EDDSA | (0x38))
+
+#endif
+
+/// Key storage methods
+
+/// Key is stored in a plaintext buffer in application memory. Application
+/// can save its in-memory buffer to non-volatile memory as needed to
+/// provide key persistence.
+#define SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT 0x00
+#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)
+/// Key is stored encrypted in application memory. This ensures the key in
+/// wrapped form is only usable on a specific device. If the key
+/// additionally needs to be prevented from ever being output as plaintext,
+/// also set the corresponding permission bit. Application can save its
+/// in-memory buffer to non-volatile memory as needed to provide key
+/// persistence.
+/// Keys stored in this way should use the flag
+/// SL_SE_KEY_FLAG_NON_EXPORTABLE unless there is a specific need to access
+/// the key value outside the SE.
+  #define SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED 0x01
+/// Key is stored inside the SE, and will persist until system reset or
+/// explicitly deleted.
+/// Keys stored in this way should use the flag
+/// SL_SE_KEY_FLAG_NON_EXPORTABLE unless there is a specific need to access
+/// the key value outside the SE.
+  #define SL_SE_KEY_STORAGE_INTERNAL_VOLATILE 0x02
+#endif
+/// Key is one of the pre-defined keys (pre-loaded or write-once) available
+/// in the SE. See documentation for a list of available keys.
+#define SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE 0x03
+
+#if defined(_SILICON_LABS_32B_SERIES_3)
+/// Key is stored in the KSURAM, an internal Key Slot RAM.
+  #define SL_SE_KEY_STORAGE_INTERNAL_KSU      0x04
+#endif
+
+/// List of available internal SE key slots
+#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)
+  #define SL_SE_KEY_SLOT_VOLATILE_0 0x00 ///< Internal volatile slot 0
+  #define SL_SE_KEY_SLOT_VOLATILE_1 0x01 ///< Internal volatile slot 1
+  #define SL_SE_KEY_SLOT_VOLATILE_2 0x02 ///< Internal volatile slot 2
+  #define SL_SE_KEY_SLOT_VOLATILE_3 0x03 ///< Internal volatile slot 3
+#endif
+
+#if defined(SLI_SE_SUPPORTS_NVM3_INTERNAL_KEY)
+/// Minimum key slot value for internal keys
+  #define SL_SE_KEY_SLOT_INTERNAL_MIN                   0xF6
+/// Internal NVM3 key
+  #define SL_SE_KEY_SLOT_NVM3_KEY                       0xF6
+#else
+/// Minimum key slot value for internal keys
+  #define SL_SE_KEY_SLOT_INTERNAL_MIN                   0xF7
+#endif
+/// Internal TrustZone root key
+#define SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY             0xF7
+/// Internal immutable application secure debug key
+#define SL_SE_KEY_SLOT_APPLICATION_SECURE_DEBUG_KEY   0xF8
+/// Internal immutable application AES-128 key (bootloader key)
+#define SL_SE_KEY_SLOT_APPLICATION_AES_128_KEY        0xFA
+/// Internal immutable application secure boot key
+#define SL_SE_KEY_SLOT_APPLICATION_SECURE_BOOT_KEY    0xFC
+/// Internal immutable application attestation key
+#define SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY    0xFE
+/// Internal immutable SE attestation key
+#define SL_SE_KEY_SLOT_SE_ATTESTATION_KEY             0xFF
+
+/// Size overhead for wrapped keys
+#define SLI_SE_WRAPPED_KEY_OVERHEAD  (12 + 16)
+/// @} (end addtogroup sl_se_manager_key_handling)
+
+/// @addtogroup sl_se_manager_key_derivation
+/// @{
+
+/// Defines mapping the PBKDF2 PRFs to corresponding sl_se_hash_type_t values.
+#define SL_SE_PRF_AES_CMAC_128 SL_SE_HASH_NONE    ///< CMAC-AES-128
+#define SL_SE_PRF_HMAC_SHA1 SL_SE_HASH_SHA1       ///< HMAC-SHA-1
+#define SL_SE_PRF_HMAC_SHA224 SL_SE_HASH_SHA224   ///< HMAC-SHA-224
+#define SL_SE_PRF_HMAC_SHA256 SL_SE_HASH_SHA256   ///< HMAC-SHA-256
+#define SL_SE_PRF_HMAC_SHA384 SL_SE_HASH_SHA384   ///< HMAC-SHA-384
+#define SL_SE_PRF_HMAC_SHA512 SL_SE_HASH_SHA512   ///< HMAC-SHA-512
+
+/// @} (end addtogroup sl_se_manager_key_derivation)
+
+/// @addtogroup sl_se_manager_util
+/// @{
+
+/// SE Challenge size
+#define SL_SE_CHALLENGE_SIZE                      16
+
+/// Certificate key size
+#define SL_SE_CERT_KEY_SIZE                       64
+
+/// Certificate signature size
+#define SL_SE_CERT_SIGN_SIZE                      64
+
+/// Batch ID certificate
+#define SL_SE_CERT_BATCH                          0x01
+/// SE ID certificate
+#define SL_SE_CERT_DEVICE_SE                      0x02
+/// Host ID certificate
+#define SL_SE_CERT_DEVICE_HOST                    0x03
+
+/// @addtogroup sl_se_manager_util_tamper Tamper options
+/// @brief
+///   Tamper configuration options. Levels, signals and filter options.
+/// @{
+
+// SE tamper signal levels
+#define SL_SE_TAMPER_LEVEL_IGNORE                 0  ///< No action taken
+#define SL_SE_TAMPER_LEVEL_INTERRUPT              1  ///< Generate interrupt
+#define SL_SE_TAMPER_LEVEL_FILTER                 2  ///< Increment filter counter
+#define SL_SE_TAMPER_LEVEL_RESET                  4  ///< System reset
+#define SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP  7  ///< Erase OTP - THIS WILL MAKE THE DEVICE INOPERATIONAL!
+
+// SE tamper signals
+#if defined(SLI_SE_MAJOR_VERSION_ONE)
+
+#define SL_SE_TAMPER_SIGNAL_RESERVED_1                  0x0   ///< Reserved tamper signal
+#define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER              0x1   ///< Filter counter exceeds threshold
+#define SL_SE_TAMPER_SIGNAL_WATCHDOG                    0x2   ///< SE watchdog timeout
+#define SL_SE_TAMPER_SIGNAL_RESERVED_2                  0x3   ///< Reserved tamper signal
+#define SL_SE_TAMPER_SIGNAL_SE_RAM_CRC                  0x4   ///< SE RAM CRC parity error
+#define SL_SE_TAMPER_SIGNAL_SE_HARDFAULT                0x5   ///< SE CPU hardfault
+#define SL_SE_TAMPER_SIGNAL_RESERVED_3                  0x6   ///< Reserved tamper signal
+#define SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION       0x7   ///< SE software triggers an assert
+#define SL_SE_TAMPER_SIGNAL_SE_SECURE_BOOT_FAILED       0x8   ///< Secure boot of SE firmware failed
+#define SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED     0x9   ///< Secure boot of user code failed
+#define SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR 0xA   ///< Unauthorised command received over the Mailbox interface
+#define SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR     0xB   ///< Unauthorised command received over the DCI interface
+#define SL_SE_TAMPER_SIGNAL_FLASH_INTEGRITY_ERROR       0xC   ///< Flash content couldn't be properly authenticated
+#define SL_SE_TAMPER_SIGNAL_RESERVED_4                  0xD   ///< Reserved tamper signal
+#define SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED             0xE   ///< Integrity error of internal storage is detected
+#define SL_SE_TAMPER_SIGNAL_TRNG_MONITOR                0xF   ///< TRNG monitor detected lack of entropy
+#define SL_SE_TAMPER_SIGNAL_PRS0                        0x10  ///< PRS channel 0 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS1                        0x11  ///< PRS channel 1 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS2                        0x12  ///< PRS channel 2 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS3                        0x13  ///< PRS channel 3 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS4                        0x14  ///< PRS channel 4 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS5                        0x15  ///< PRS channel 5 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS6                        0x16  ///< PRS channel 6 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS7                        0x17  ///< PRS channel 7 asserted
+#define SL_SE_TAMPER_SIGNAL_DECOUPLE_BOD                0x18  ///< Decouple brown-out-detector threshold alert
+#define SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR          0x19  ///< On-device temperature sensor detects operation outside datasheet specification
+#define SL_SE_TAMPER_SIGNAL_VOLTAGE_GLITCH_FALLING      0x1A  ///< Voltage glitch detector detected falling glitch
+#define SL_SE_TAMPER_SIGNAL_VOLTAGE_GLITCH_RISING       0x1B  ///< Voltage glitch detector detected rising glitch
+#define SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR           0x1C  ///< Debug lock internal logic check failed
+#define SL_SE_TAMPER_SIGNAL_SE_DEBUG_GRANTED            0x1D  ///< SE debug granted
+#define SL_SE_TAMPER_SIGNAL_DIGITAL_GLITCH              0x1E  ///< Digital glitch detector detected an event
+#define SL_SE_TAMPER_SIGNAL_SE_ICACHE_ERROR             0x1F  ///< SE ICACHE checksum error
+#define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS                 0x20  ///< Number of tamper signals
+
+#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)
+
+// SE tamper signals for xG25 and xG29, with ETAMPDET signal included.
+#define SL_SE_TAMPER_SIGNAL_RESERVED_1                  0x0   ///< Reserved tamper signal
+#define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER              0x1   ///< Filter counter exceeds threshold
+#define SL_SE_TAMPER_SIGNAL_WATCHDOG                    0x2   ///< SE watchdog timeout
+#define SL_SE_TAMPER_SIGNAL_RESERVED_2                  0x3   ///< Reserved tamper signal
+#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2                0x4   ///< SE RAM 2-bit ECC error
+#define SL_SE_TAMPER_SIGNAL_SE_HARDFAULT                0x5   ///< SE CPU hardfault
+#define SL_SE_TAMPER_SIGNAL_RESERVED_3                  0x6   ///< Reserved tamper signal
+#define SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION       0x7   ///< SE software triggers an assert
+#define SL_SE_TAMPER_SIGNAL_SE_SECURE_BOOT_FAILED       0x8   ///< Secure boot of SE firmware failed
+#define SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED     0x9   ///< Secure boot of user code failed
+#define SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR 0xA   ///< Unauthorised command received over the Mailbox interface
+#define SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR     0xB   ///< Unauthorised command received over the DCI interface
+#define SL_SE_TAMPER_SIGNAL_FLASH_INTEGRITY_ERROR       0xC   ///< Flash content couldn't be properly authenticated
+#define SL_SE_TAMPER_SIGNAL_RESERVED_4                  0xD   ///< Reserved tamper signal
+#define SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED             0xE   ///< Integrity error of internal storage is detected
+#define SL_SE_TAMPER_SIGNAL_TRNG_MONITOR                0xF   ///< TRNG monitor detected lack of entropy
+#define SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR           0x10  ///< Debug lock internal logic check failed
+#define SL_SE_TAMPER_ATAMPDET_EMPGD                     0x11  ///< Electromagnetic pulse glitch detector
+#define SL_SE_TAMPER_ATAMPDET_SUPGD                     0x12  ///< Supply glitch detector
+#define SL_SE_TAMPER_SE_ICACHE_ERROR                    0x13  ///< SE ICache RAM error
+#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1                0x14  ///< SE RAM 1-bit ECC error
+#define SL_SE_TAMPER_SIGNAL_BOD                         0x15  ///< Brown-out-detector threshold alert
+#define SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR          0x16  ///< On-device temperature sensor
+#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_LOW          0x17  ///< DPLL lock fail low
+#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_HIGH         0x18  ///< DPLL lock fail high
+#define SL_SE_TAMPER_SIGNAL_ETAMPDET                    0x19  ///< External tamper detect
+#define SL_SE_TAMPER_SIGNAL_PRS0                        0x1a  ///< PRS channel 0 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS1                        0x1b  ///< PRS channel 1 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS2                        0x1c  ///< PRS channel 2 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS3                        0x1d  ///< PRS channel 3 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS4                        0x1e  ///< PRS channel 4 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS5                        0x1f  ///< PRS channel 5 asserted
+#define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS                 0x20  ///< Number of tamper signals
+
+#else
+
+// SE tamper signals
+#define SL_SE_TAMPER_SIGNAL_RESERVED_1                  0x0   ///< Reserved tamper signal
+#define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER              0x1   ///< Filter counter exceeds threshold
+#define SL_SE_TAMPER_SIGNAL_WATCHDOG                    0x2   ///< SE watchdog timeout
+#define SL_SE_TAMPER_SIGNAL_RESERVED_2                  0x3   ///< Reserved tamper signal
+#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2                0x4   ///< SE RAM 2-bit ECC error
+#define SL_SE_TAMPER_SIGNAL_SE_HARDFAULT                0x5   ///< SE CPU hardfault
+#define SL_SE_TAMPER_SIGNAL_RESERVED_3                  0x6   ///< Reserved tamper signal
+#define SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION       0x7   ///< SE software triggers an assert
+#define SL_SE_TAMPER_SIGNAL_SE_SECURE_BOOT_FAILED       0x8   ///< Secure boot of SE firmware failed
+#define SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED     0x9   ///< Secure boot of user code failed
+#define SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR 0xA   ///< Unauthorised command received over the Mailbox interface
+#define SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR     0xB   ///< Unauthorised command received over the DCI interface
+#define SL_SE_TAMPER_SIGNAL_FLASH_INTEGRITY_ERROR       0xC   ///< Flash content couldn't be properly authenticated
+#define SL_SE_TAMPER_SIGNAL_RESERVED_4                  0xD   ///< Reserved tamper signal
+#define SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED             0xE   ///< Integrity error of internal storage is detected
+#define SL_SE_TAMPER_SIGNAL_TRNG_MONITOR                0xF   ///< TRNG monitor detected lack of entropy
+#define SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR           0x10  ///< Debug lock internal logic check failed
+#define SL_SE_TAMPER_ATAMPDET_EMPGD                     0x11  ///< Electromagnetic pulse glitch detector
+#define SL_SE_TAMPER_ATAMPDET_SUPGD                     0x12  ///< Supply glitch detector
+#define SL_SE_TAMPER_SE_ICACHE_ERROR                    0x13  ///< SE ICache RAM error
+#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1                0x14  ///< SE RAM 1-bit ECC error
+#define SL_SE_TAMPER_SIGNAL_BOD                         0x15  ///< Brown-out-detector threshold alert
+#define SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR          0x16  ///< On-device temperature sensor
+#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_LOW          0x17  ///< DPLL lock fail low
+#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_HIGH         0x18  ///< DPLL lock fail high
+#define SL_SE_TAMPER_SIGNAL_PRS0                        0x19  ///< PRS channel 0 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS1                        0x1a  ///< PRS channel 1 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS2                        0x1b  ///< PRS channel 2 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS3                        0x1c  ///< PRS channel 3 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS4                        0x1d  ///< PRS channel 4 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS5                        0x1e  ///< PRS channel 5 asserted
+#define SL_SE_TAMPER_SIGNAL_PRS6                        0x1f  ///< PRS channel 6 asserted
+#define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS                 0x20  ///< Number of tamper signals
+
+#endif
+
+// SE tamper filter timeout period.
+#define SL_SE_TAMPER_FILTER_PERIOD_32MS     0x0   ///< Timeout ~32ms
+#define SL_SE_TAMPER_FILTER_PERIOD_64MS     0x1   ///< Timeout ~64ms
+#define SL_SE_TAMPER_FILTER_PERIOD_128MS    0x2   ///< Timeout ~128ms
+#define SL_SE_TAMPER_FILTER_PERIOD_256MS    0x3   ///< Timeout ~256ms
+#define SL_SE_TAMPER_FILTER_PERIOD_512MS    0x4   ///< Timeout ~512ms
+#define SL_SE_TAMPER_FILTER_PERIOD_1S       0x5   ///< Timeout ~1s
+#define SL_SE_TAMPER_FILTER_PERIOD_2S       0x6   ///< Timeout ~2s
+#define SL_SE_TAMPER_FILTER_PERIOD_4S       0x7   ///< Timeout ~4.1s
+#define SL_SE_TAMPER_FILTER_PERIOD_8S       0x8   ///< Timeout ~8.2s
+#define SL_SE_TAMPER_FILTER_PERIOD_16S      0x9   ///< Timeout ~16.4s
+#define SL_SE_TAMPER_FILTER_PERIOD_33S      0xA   ///< Timeout ~32.8s
+#define SL_SE_TAMPER_FILTER_PERIOD_1MIN     0xB   ///< Timeout ~1.1min
+#define SL_SE_TAMPER_FILTER_PERIOD_2MIN     0xC   ///< Timeout ~2.2min
+#define SL_SE_TAMPER_FILTER_PERIOD_4MIN     0xD   ///< Timeout ~4.4min
+#define SL_SE_TAMPER_FILTER_PERIOD_9MIN     0xE   ///< Timeout ~8.7min
+#define SL_SE_TAMPER_FILTER_PERIOD_18MIN    0xF   ///< Timeout ~17.5min
+#define SL_SE_TAMPER_FILTER_PERIOD_35MIN    0x10  ///< Timeout ~35min
+#define SL_SE_TAMPER_FILTER_PERIOD_1H       0x11  ///< Timeout ~1.2h
+#define SL_SE_TAMPER_FILTER_PERIOD_2H       0x12  ///< Timeout ~2.3h
+#define SL_SE_TAMPER_FILTER_PERIOD_5H       0x13  ///< Timeout ~4.7h
+#define SL_SE_TAMPER_FILTER_PERIOD_9H       0x14  ///< Timeout ~9.3h
+#define SL_SE_TAMPER_FILTER_PERIOD_19H      0x15  ///< Timeout ~18.6h
+#define SL_SE_TAMPER_FILTER_PERIOD_2DAYS    0x16  ///< Timeout ~1.6days
+#define SL_SE_TAMPER_FILTER_PERIOD_3DAYS    0x17  ///< Timeout ~3.1days
+#define SL_SE_TAMPER_FILTER_PERIOD_6DAYS    0x18  ///< Timeout ~6.2days
+#define SL_SE_TAMPER_FILTER_PERIOD_12DAYS   0x19  ///< Timeout ~12.4days
+#define SL_SE_TAMPER_FILTER_PERIOD_25DAYS   0x1A  ///< Timeout ~24.9days
+#define SL_SE_TAMPER_FILTER_PERIOD_50DAYS   0x1B  ///< Timeout ~49.7days
+#define SL_SE_TAMPER_FILTER_PERIOD_100DAYS  0x1C  ///< Timeout ~99.4days
+#define SL_SE_TAMPER_FILTER_PERIOD_199DAYS  0x1D  ///< Timeout ~198.8days
+#define SL_SE_TAMPER_FILTER_PERIOD_398DAYS  0x1E  ///< Timeout ~397.7days
+#define SL_SE_TAMPER_FILTER_PERIOD_795DAYS  0x1F  ///< Timeout ~795.4days
+
+// Number of tamper counts to trigger the filter signal.
+#define SL_SE_TAMPER_FILTER_THRESHOLD_2     0x7   ///< Counter threshold 2
+#define SL_SE_TAMPER_FILTER_THRESHOLD_4     0x6   ///< Counter threshold 4
+#define SL_SE_TAMPER_FILTER_THRESHOLD_8     0x5   ///< Counter threshold 8
+#define SL_SE_TAMPER_FILTER_THRESHOLD_16    0x4   ///< Counter threshold 16
+#define SL_SE_TAMPER_FILTER_THRESHOLD_32    0x3   ///< Counter threshold 32
+#define SL_SE_TAMPER_FILTER_THRESHOLD_64    0x2   ///< Counter threshold 64
+#define SL_SE_TAMPER_FILTER_THRESHOLD_128   0x1   ///< Counter threshold 128
+#define SL_SE_TAMPER_FILTER_THRESHOLD_256   0x0   ///< Counter threshold 256
+
+/// Tamper flags.
+#define SL_SE_TAMPER_FLAG_DGLITCH_ALWAYS_ON (1UL << 1) /// Digital glitch detector always on
+#define SL_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_DURING_SLEEP (1UL << 2) /// Tamper is kept alive during sleep (down to EM3)
+
+/// @} (end addtogroup sl_se_manager_util_tamper)
+/// @} (end addtogroup sl_se_manager_util)
+
+/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
+
+#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_2025_6
+/// Initial values for CMAC streaming context struct @ref sl_se_cmac_multipart_context_t
+#define SL_SE_CMAC_STREAMING_INIT_DEFAULT    { NULL, { 0 }, { 0 }, 0 }
+
+/// Initial values for AES-GCM streaming context struct @ref sl_se_gcm_multipart_context_t
+#define SL_SE_GCM_STREAMING_INIT_DEFAULT     { NULL, 0, 0, { 0 }, { 0 }, \
+                                               { 0 }, 0, 0 }
+#else
+#define SL_SE_GCM_STREAMING_INIT_DEFAULT _Pragma("GCC warning \"'SL_SE_GCM_STREAMING_INIT_DEFAULT' macro is deprecated as of Simplicity SDK release 2024.12\""){ NULL, 0, 0, { 0 }, { 0 }, \
+                                                                                                                                                                 { 0 }, 0, 0 }
+
+#define SL_SE_CMAC_STREAMING_INIT_DEFAULT _Pragma("GCC warning \"'SL_SE_CMAC_STREAMING_INIT_DEFAULT' macro is deprecated as of Simplicity SDK release 2024.12\"") { NULL, { 0 }, { 0 }, 0 }
+
+#endif
+/// @endcond
+
+/// @addtogroup sl_se_manager_cipher
+/// @{
+
+/// Block size for the AES
+#define SL_SE_AES_BLOCK_SIZE   (16u)
+
+/// @} (end addtogroup sl_se_manager_cipher)
+
+/// @addtogroup sl_se_manager_hash
+/// @{
+#define SL_SE_HASH_STREAMING_INIT_DEFAULT    { NULL, 0, 0, NULL }     ///< Default streaming hash context
+#define SL_SE_SHA1_STREAMING_INIT_DEFAULT    { { 0 }, { 0 }, { 0 } }  ///< SHA1 streaming hash context
+#define SL_SE_SHA224_STREAMING_INIT_DEFAULT  { { 0 }, { 0 }, { 0 } }  ///< SHA224 streaming hash context
+#define SL_SE_SHA256_STREAMING_INIT_DEFAULT  { { 0 }, { 0 }, { 0 } }  ///< SHA256 streaming hash context
+#define SL_SE_SHA384_STREAMING_INIT_DEFAULT  { { 0 }, { 0 }, { 0 } }  ///< SHA384 streaming hash context
+#define SL_SE_SHA512_STREAMING_INIT_DEFAULT  { { 0 }, { 0 }, { 0 } }  ///< SHA512 streaming hash context
+/// @} (end addtogroup sl_se_manager_hash)
+
+#elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) // defined(SLI_MAILBOX_COMMAND_SUPPORTED)
+// -------------------------------
+// Defines for Root code functionality
+
+#define SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT                       16U
+
+#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED)
+
+#if defined(_SILICON_LABS_32B_SERIES_3)
+/// @addtogroup sl_se_manager_extmem
+/// @{
+
+// The maximum number of code regions available on the device.
+// The number of available code regions may be different on future devices.
+#define SL_SE_MAX_CODE_REGIONS           8
+
+/// @} (end addtogroup sl_se_manager_extmem)
+
+#endif // defined(_SILICON_LABS_32B_SERIES_3)
+
+#ifdef __cplusplus
+}
+#endif
+
+/// @} (end addtogroup sl_se)
+
+#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED)
+
+#endif // SE_MANAGER_DEFINES_H

Libs/platform/security/sl_component/se_manager/inc/sl_se_manager_entropy.h

@@ -0,0 +1,97 @@
+/***************************************************************************//**
+ * @file
+ * @brief Silicon Labs Secure Engine Manager API.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifndef SL_SE_MANAGER_ENTROPY_H
+#define SL_SE_MANAGER_ENTROPY_H
+
+#include "sli_se_manager_features.h"
+
+#if defined(SLI_MAILBOX_COMMAND_SUPPORTED)
+
+/// @addtogroup sl_se_manager
+/// @{
+
+/***************************************************************************//**
+ * @addtogroup sl_se_manager_entropy Entropy
+ *
+ * @brief
+ *   Random number generators
+ * @details
+ *
+ *   API for getting randomness from the Secure Engine True Random Number
+ *   Generator (TRNG).
+ *
+ * @{
+ ******************************************************************************/
+
+#include "sl_se_manager_key_handling.h"
+#include "sl_se_manager_types.h"
+#include "sli_se_manager_mailbox.h"
+#include "sl_status.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// -----------------------------------------------------------------------------
+// Prototypes
+
+/***************************************************************************//**
+ * @brief
+ *   Get random data from hardware TRNG.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[out] data
+ *   Random data from TRNG.
+ *
+ * @param[in] num_bytes
+ *   Length of data request.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_get_random(sl_se_command_context_t *cmd_ctx,
+                             void *data,
+                             uint32_t num_bytes);
+
+#ifdef __cplusplus
+}
+#endif
+
+/// @} (end addtogroup sl_se_manager_entropy)
+/// @} (end addtogroup sl_se)
+
+#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED)
+
+#endif // SL_SE_MANAGER_ENTROPY_H

Libs/platform/security/sl_component/se_manager/inc/sl_se_manager_hash.h

@@ -0,0 +1,308 @@
+/***************************************************************************//**
+ * @file
+ * @brief Silicon Labs Secure Engine Manager API.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifndef SL_SE_MANAGER_HASH_H
+#define SL_SE_MANAGER_HASH_H
+
+#include "sli_se_manager_features.h"
+
+#if defined(SLI_MAILBOX_COMMAND_SUPPORTED)
+
+/// @addtogroup sl_se_manager
+/// @{
+
+/***************************************************************************//**
+ * @addtogroup sl_se_manager_hash Hashing
+ *
+ * @brief
+ *   Provides cryptographic hash functions (SHA-1, SHA-224, SHA-256, SHA-384,
+ *   SHA-512).
+ *
+ * @details
+ *   Provides API for one-way hashing functions.
+ *
+ * @{
+ ******************************************************************************/
+
+#include "sl_se_manager_key_handling.h"
+#include "sl_se_manager_types.h"
+#include "sli_se_manager_mailbox.h"
+#include "sl_status.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// -----------------------------------------------------------------------------
+// Prototypes
+
+/***************************************************************************//**
+ * @brief
+ *   Produce a message digest (a hash block) using the input data.
+ *
+ * @details
+ *   This function generates a message digest adhering to the given inputs.
+ *   For instance, if the algorithm is chosen to be SHA-256, it will generate
+ *   a 32 bytes message digest computed based on the input message.
+ *   This function supports SHA-1, SHA-256 and SHA-512 algorithms.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[in] hash_type
+ *   Which hashing algorithm to use.
+ *
+ * @param[in] message
+ *   Pointer to the message buffer to compute the hash/digest from.
+ *
+ * @param[in] message_size
+ *   Number of bytes in message.
+ *
+ * @param[out] digest
+ *   Pointer to block of memory to store the final digest.
+ *
+ * @param[in]  digest_len
+ *   The length of the message digest (hash), must be at least the size of the
+ *   corresponding hash type.
+ *
+ * @return Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_hash(sl_se_command_context_t *cmd_ctx,
+                       sl_se_hash_type_t hash_type,
+                       const uint8_t *message,
+                       unsigned int message_size,
+                       uint8_t* digest,
+                       size_t digest_len);
+
+/***************************************************************************//**
+ * @brief
+ *   Prepare a SHA1 hash streaming command context object.
+ *
+ * @details
+ *   Prepare a SHA1 hash streaming command context object to be used in
+ *   subsequent calls to hash streaming functions sl_se_hash_multipart_update() and
+ *   sl_se_hash_multipart_finish().
+ *
+ * @param[in] sha1_ctx
+ *   Pointer to a SHA1 streaming context object.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_hash_sha1_multipart_starts(sl_se_sha1_multipart_context_t *sha1_ctx,
+                                             sl_se_command_context_t *cmd_ctx);
+
+/***************************************************************************//**
+ * @brief
+ *   Prepare a SHA224 hash streaming command context object.
+ *
+ * @details
+ *   Prepare a SHA224 hash streaming command context object to be used in
+ *   subsequent calls to hash streaming functions sl_se_hash_multipart_update() and
+ *   sl_se_hash_multipart_finish().
+ *
+ * @param[in] sha224_ctx
+ *   Pointer to a SHA224 streaming context object.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_hash_sha224_multipart_starts(sl_se_sha224_multipart_context_t *sha224_ctx,
+                                               sl_se_command_context_t *cmd_ctx);
+
+/***************************************************************************//**
+ * @brief
+ *   Prepare a SHA256 hash streaming command context object.
+ *
+ * @details
+ *   Prepare a SHA256 hash streaming command context object to be used in
+ *   subsequent calls to hash streaming functions sl_se_hash_multipart_update() and
+ *   sl_se_hash_multipart_finish().
+ *
+ * @param[in] sha256_ctx
+ *   Pointer to a SHA256 streaming context object.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_hash_sha256_multipart_starts(sl_se_sha256_multipart_context_t *sha256_ctx,
+                                               sl_se_command_context_t *cmd_ctx);
+
+#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)
+/***************************************************************************//**
+ * @brief
+ *   Prepare a SHA384 streaming command context object.
+ *
+ * @details
+ *   Prepare a SHA384 hash streaming command context object to be used in
+ *   subsequent calls to hash streaming functions sl_se_hash_multipart_update() and
+ *   sl_se_hash_multipart_finish().
+ *
+ * @param[in] sha384_ctx
+ *   Pointer to a SHA384 streaming context object.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_hash_sha384_multipart_starts(sl_se_sha384_multipart_context_t *sha384_ctx,
+                                               sl_se_command_context_t *cmd_ctx);
+
+/***************************************************************************//**
+ * @brief
+ *   Prepare a SHA512 streaming command context object.
+ *
+ * @details
+ *   Prepare a SHA512 hash streaming command context object to be used in
+ *   subsequent calls to hash streaming functions sl_se_hash_multipart_update() and
+ *   sl_se_hash_multipart_finish().
+ *
+ * @param[in] sha512_ctx
+ *   Pointer to a SHA512 streaming context object.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_hash_sha512_multipart_starts(sl_se_sha512_multipart_context_t *sha512_ctx,
+                                               sl_se_command_context_t *cmd_ctx);
+
+#endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)
+
+/***************************************************************************//**
+ * @brief
+ *   Prepare a hash streaming command context object.
+ *
+ * @details
+ *   Prepare a hash (message digest) streaming command context object to be
+ *   used in subsequent calls to hash streaming functions sl_se_hash_multipart_update()
+ *   and sl_se_hash_multipart_finish().
+ *
+ * @param[in] hash_type_ctx
+ *   Pointer to a hash streaming context object specific to the hash type
+ *   specified by @p hash_type.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[in] hash_type
+ *   Type of hash algoritm
+ *
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_hash_multipart_starts(void *hash_type_ctx,
+                                        sl_se_command_context_t *cmd_ctx,
+                                        sl_se_hash_type_t hash_type);
+
+/***************************************************************************//**
+ * @brief
+ *   Feeds an input buffer into an ongoing hash computation.
+ *
+ *   This function is called between @ref sl_se_hash_multipart_starts() and
+ *   @ref sl_se_hash_multipart_finish().
+ *   This function can be called repeatedly.
+ *
+ * @param[in] hash_type_ctx
+ *   Pointer to a hash streaming context object specific to the hash type
+ *   specified by @p hash_type.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[in] input
+ *   Buffer holding the input data, must be at least @p ilen bytes wide.
+ *
+ * @param[in] input_len
+ *   The length of the input data in bytes.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_hash_multipart_update(void *hash_type_ctx,
+                                        sl_se_command_context_t *cmd_ctx,
+                                        const uint8_t *input,
+                                        size_t input_len);
+
+/***************************************************************************//**
+ * @brief
+ *   Finish a hash streaming operation and return the resulting hash digest.
+ *
+ *   This function is called after sl_se_hash_multipart_update().
+ *
+ * @param[in] hash_type_ctx
+ *   Pointer to a hash streaming context object specific to the hash type
+ *   specified by @p hash_type.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[out] digest_out
+ *   Buffer for holding the message digest (hash), must be at least the size
+ *   of the corresponding message digest type.
+ *
+ * @param[in]  digest_len
+ *   The length of the message digest (hash), must be at least the size of the
+ *   corresponding hash type.
+ *
+ * @return
+ *   Status code, @ref sl_status.h.
+ ******************************************************************************/
+sl_status_t sl_se_hash_multipart_finish(void *hash_type_ctx,
+                                        sl_se_command_context_t *cmd_ctx,
+                                        uint8_t *digest_out,
+                                        size_t digest_len);
+
+#ifdef __cplusplus
+}
+#endif
+
+/// @} (end addtogroup sl_se_manager_hash)
+/// @} (end addtogroup sl_se_manager)
+
+#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED)
+
+#endif // SL_SE_MANAGER_HASH_H

Libs/platform/security/sl_component/se_manager/inc/sl_se_manager_internal_keys.h

@@ -0,0 +1,143 @@
+/***************************************************************************//**
+ * @file
+ * @brief Silicon Labs Secure Engine Manager Internal key defines
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifndef SL_SE_MANAGER_INTERNAL_KEYS
+#define SL_SE_MANAGER_INTERNAL_KEYS
+
+#include "sli_se_manager_features.h"
+#include "sl_se_manager_defines.h"
+
+#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)
+
+#if defined(SLI_SE_MAJOR_VERSION_ONE)
+/// Key descriptor for internal application attestation key
+  #define SL_SE_APPLICATION_ATTESTATION_KEY                     \
+  {                                                             \
+    .type = SL_SE_KEY_TYPE_ECC_P256,                            \
+    .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE                      \
+             | SL_SE_KEY_FLAG_IS_DEVICE_GENERATED               \
+             | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY \
+             | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY,          \
+    .storage = {                                                \
+      .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE,           \
+      .location = {                                             \
+        .slot = SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY,     \
+      },                                                        \
+    },                                                          \
+  }
+#else
+/// Key descriptor for internal application attestation key
+  #define SL_SE_APPLICATION_ATTESTATION_KEY                     \
+  {                                                             \
+    .type = SL_SE_KEY_TYPE_ECC_P256,                            \
+    .flags = SL_SE_KEY_FLAG_IS_DEVICE_GENERATED                 \
+             | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY \
+             | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY,          \
+    .storage = {                                                \
+      .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE,           \
+      .location = {                                             \
+        .slot = SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY,     \
+      },                                                        \
+    },                                                          \
+  }
+#endif
+
+/// Key descriptor for internal SE attestation key
+/// @note: Can only be used to get the public part
+  #define SL_SE_SYSTEM_ATTESTATION_KEY                          \
+  {                                                             \
+    .type = SL_SE_KEY_TYPE_ECC_P256,                            \
+    .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE                      \
+             | SL_SE_KEY_FLAG_IS_DEVICE_GENERATED               \
+             | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY \
+             | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY,          \
+    .storage = {                                                \
+      .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE,           \
+      .location = {                                             \
+        .slot = SL_SE_KEY_SLOT_SE_ATTESTATION_KEY,              \
+      },                                                        \
+    },                                                          \
+  }
+
+#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT
+
+/// Key descriptor for secure boot public key
+#define SL_SE_APPLICATION_SECURE_BOOT_KEY                    \
+  {                                                          \
+    .type = SL_SE_KEY_TYPE_ECC_P256,                         \
+    .flags = SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY \
+             | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY,       \
+    .storage = {                                             \
+      .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE,        \
+      .location = {                                          \
+        .slot = SL_SE_KEY_SLOT_APPLICATION_SECURE_BOOT_KEY,  \
+      },                                                     \
+    },                                                       \
+  }
+
+/// Key descriptor for secure debug public key
+#define SL_SE_APPLICATION_SECURE_DEBUG_KEY                   \
+  {                                                          \
+    .type = SL_SE_KEY_TYPE_ECC_P256,                         \
+    .flags = SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY \
+             | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY,       \
+    .storage = {                                             \
+      .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE,        \
+      .location = {                                          \
+        .slot = SL_SE_KEY_SLOT_APPLICATION_SECURE_DEBUG_KEY, \
+      },                                                     \
+    },                                                       \
+  }
+
+/// Key descriptor for application AES-128 key
+#define SL_SE_APPLICATION_AES_128_KEY                   \
+  {                                                     \
+    .type = SL_SE_KEY_TYPE_AES_128,                     \
+    .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE,             \
+    .storage = {                                        \
+      .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE,   \
+      .location = {                                     \
+        .slot = SL_SE_KEY_SLOT_APPLICATION_AES_128_KEY, \
+      },                                                \
+    },                                                  \
+  }
+
+/// Key descriptor for TrustZone root key
+#define SL_SE_TRUSTZONE_ROOT_KEY                      \
+  {                                                   \
+    .type = SL_SE_KEY_TYPE_AES_256,                   \
+    .flags = SL_SE_KEY_FLAG_IS_DEVICE_GENERATED,      \
+    .storage = {                                      \
+      .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \
+      .location = {                                   \
+        .slot = SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY,    \
+      },                                              \
+    },                                                \
+  }
+#endif // SL_SE_MANAGER_INTERNAL_KEYS

Libs/platform/security/sl_component/se_manager/inc/sl_se_manager_key_derivation.h

@@ -0,0 +1,436 @@
+/***************************************************************************//**
+ * @file
+ * @brief Silicon Labs Secure Engine Manager API.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+#ifndef SL_SE_MANAGER_KEY_DERIVATION_H
+#define SL_SE_MANAGER_KEY_DERIVATION_H
+
+#include "sli_se_manager_features.h"
+
+#if defined(SLI_MAILBOX_COMMAND_SUPPORTED)
+
+/// @addtogroup sl_se_manager
+/// @{
+
+/***************************************************************************//**
+ * @addtogroup sl_se_manager_key_derivation Key derivation
+ *
+ * @brief
+ *   API for key derivation and key agreement (ECDH, EC J-PAKE, HKDF, PBKDF2).
+ *
+ * @details
+ *   Contains key derivation functions (HKDF, PBKDF2) and key agreement
+ *   functions (ECDH, ECJPAKE).
+ *
+ * @{
+ ******************************************************************************/
+
+#include "sl_se_manager_key_handling.h"
+#include "sl_se_manager_types.h"
+#include "sli_se_manager_mailbox.h"
+#include "sl_status.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// -----------------------------------------------------------------------------
+// Prototypes
+
+// -------------------------------
+// Elliptic-curve Diffie–Hellman
+
+/***************************************************************************//**
+ * @brief
+ *   This function computes the shared secret with Elliptic Curve Diffie Hellman
+ *   (ECDH) algorithm
+ *
+ * @details
+ *   Performs Elliptic Curve Diffie Hellman shared secret computation.
+ *
+ * @note
+ *   P-521 Elliptic Curve based Elliptic Curve Diffie Hellman (ECDH) expects
+ *   a 544 bits (68 bytes) buffer for storing private keys, and
+ *   a 1088 bits (136 bytes) buffer for storing public keys and shared secret.
+ *   The first 23 bits of d, Qx, Qy and shared secret are padding bits to comply
+ *   word-aligned addressing. The padding bits are ignored in the computation.
+ *
+ *   This function does not implement the value-checking of the shared secret
+ *   as described in RFC7748 when using Montgomery keys.
+ *
+ *   In case of using custom domain curves, \p key_in_priv defines the domain
+ *   parameters. Moreover, \p key_in_pub should always contain a public key.
+ *   If key_in_pub contains a private key, sl_se_export_public_key() can be
+ *   used to export the public key.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[in] key_in_priv
+ *   Our private key.
+ *
+ * @param[in] key_in_pub
+ *   Their public key.
+ *
+ * @param[out] key_out
+ *   Shared secret key. Montgomery curve result is one single coordinate.
+ *   Other curve types result in one pair of coordinate.
+ *
+ * @return
+ *   SL_STATUS_INVALID_KEY if \p key_in_pub does not contain a public key
+ *   when using custom domain curves, otherwise an appropriate error code
+ *   (@ref sl_status.h).
+ ******************************************************************************/
+sl_status_t sl_se_ecdh_compute_shared_secret(sl_se_command_context_t *cmd_ctx,
+                                             const sl_se_key_descriptor_t *key_in_priv,
+                                             const sl_se_key_descriptor_t *key_in_pub,
+                                             const sl_se_key_descriptor_t *key_out);
+
+// -------------------------------
+// EC J-PAKE
+
+/***************************************************************************//**
+ * @brief
+ *   Check if an EC J-PAKE context is ready for use.
+ *
+ * @param[in] ctx
+ *   The EC J-PAKE context to check. This must be initialized.
+ *
+ * @return
+ *   SL_STATUS_OK when the command was executed successfully, otherwise an
+ *   appropriate error code (@ref sl_status.h).
+ ******************************************************************************/
+sl_status_t sl_se_ecjpake_check(const sl_se_ecjpake_context_t *ctx);
+
+/***************************************************************************//**
+ * @brief
+ *   Derive the shared secret (TLS: Pre-Master Secret).
+ *
+ * @param[in] ctx
+ *   The EC J-PAKE context to use. This must be initialized, set up and have
+ *   performed both round one and two.
+ *
+ * @param[out] buf
+ *   The buffer to write the derived secret to. This must be a writable buffer
+ *   of length @p len bytes.
+ *
+ * @param[in] len
+ *   The length of @p buf in bytes.
+ *
+ * @param[out] olen
+ *   The address at which to store the total number of bytes written to @p buf.
+ *   This must not be @c NULL.
+ *
+ * @return
+ *   SL_STATUS_OK when the command was executed successfully, otherwise an
+ *   appropriate error code (@ref sl_status.h).
+ ******************************************************************************/
+sl_status_t sl_se_ecjpake_derive_secret(sl_se_ecjpake_context_t *ctx,
+                                        unsigned char *buf,
+                                        size_t len,
+                                        size_t *olen);
+
+/***************************************************************************//**
+ * @brief
+ *   This clears an EC J-PAKE context and frees any embedded data structure.
+ *
+ * @param[in] ctx
+ *   The EC J-PAKE context to free. This may be @c NULL, in which case this
+ *   function does nothing. If it is not @c NULL, it must point to an
+ *   initialized EC J-PAKE context.
+ *
+ * @return
+ *   SL_STATUS_OK when the command was executed successfully, otherwise an
+ *   appropriate error code (@ref sl_status.h).
+ ******************************************************************************/
+sl_status_t sl_se_ecjpake_free(sl_se_ecjpake_context_t *ctx);
+
+/***************************************************************************//**
+ * @brief
+ *   Initialize an EC J-PAKE context.
+ *
+ * @param[in] ctx
+ *   The EC J-PAKE context to initialize. This must not be @c NULL.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @return
+ *   SL_STATUS_OK when the command was executed successfully, otherwise an
+ *   appropriate error code (@ref sl_status.h).
+ ******************************************************************************/
+sl_status_t sl_se_ecjpake_init(sl_se_ecjpake_context_t *ctx,
+                               sl_se_command_context_t *cmd_ctx);
+
+/***************************************************************************//**
+ * @brief
+ *   Read and process the first round message (TLS: contents of the
+ *   Client/ServerHello extension, excluding extension type and length bytes).
+ *
+ * @param[in] ctx
+ *   The EC J-PAKE context to use. This must be initialized and set up.
+ *
+ * @param[in] buf
+ *   The buffer holding the first round message. This must be a readable buffer
+ *   of length @p len bytes.
+ *
+ * @param[in] len
+ *   The length in bytes of @p buf.
+ *
+ * @return
+ *   SL_STATUS_OK when the command was executed successfully, otherwise an
+ *   appropriate error code (@ref sl_status.h).
+ ******************************************************************************/
+sl_status_t sl_se_ecjpake_read_round_one(sl_se_ecjpake_context_t *ctx,
+                                         const unsigned char *buf,
+                                         size_t len);
+
+/***************************************************************************//**
+ * @brief
+ *   Read and process the second round message (TLS: contents of the
+ *   Client/ServerKeyExchange).
+ *
+ * @param[in] ctx
+ *   The EC J-PAKE context to use. This must be initialized and set up and already
+ *   have performed round one.
+ *
+ * @param[in] buf
+ *   The buffer holding the second round message. This must be a readable buffer
+ *   of length @p len bytes.
+ *
+ * @param[in] len
+ *   The length in bytes of @p buf.
+ *
+ * @return
+ *   SL_STATUS_OK when the command was executed successfully, otherwise an
+ *   appropriate error code (@ref sl_status.h).
+ ******************************************************************************/
+sl_status_t sl_se_ecjpake_read_round_two(sl_se_ecjpake_context_t *ctx,
+                                         const unsigned char *buf,
+                                         size_t len);
+
+/***************************************************************************//**
+ * @brief
+ *   Set up an EC J-PAKE context for use.
+ *
+ * @note
+ *   Currently the only values for hash/curve allowed by the standard are
+ *   @ref SL_SE_HASH_SHA256 / @ref SL_SE_KEY_TYPE_ECC_P256.
+ *
+ * @param[in] ctx
+ *   The EC J-PAKE context to set up. This must be initialized.
+ *
+ * @param[in] role
+ *   The role of the caller. This must be either @ref SL_SE_ECJPAKE_CLIENT or
+ *   @ref SL_SE_ECJPAKE_SERVER.
+ *
+ * @param[in] hash
+ *   The identifier of the hash function to use, for example
+ *   @ref SL_SE_HASH_SHA256.
+ *
+ * @param[in] curve
+ *   The identifier of the elliptic curve to use, for example
+ *   @ref SL_SE_KEY_TYPE_ECC_P256.
+ *
+ * @param[in] secret
+ *   The pre-shared secret (passphrase). This must be a readable buffer of
+ *   length @p len bytes. It need only be valid for the duration of this call.
+ *
+ * @param[in] len
+ *   The length of the pre-shared secret @p secret.
+ *
+ * @return
+ *   SL_STATUS_OK when the command was executed successfully, otherwise an
+ *   appropriate error code (@ref sl_status.h).
+ ******************************************************************************/
+sl_status_t sl_se_ecjpake_setup(sl_se_ecjpake_context_t *ctx,
+                                sl_se_ecjpake_role_t role,
+                                sl_se_hash_type_t hash,
+                                uint32_t curve,
+                                const unsigned char *secret,
+                                size_t len);
+
+/***************************************************************************//**
+ * @brief
+ *   Generate and write the first round message (TLS: contents of the
+ *   Client/ServerHello extension, excluding extension type and length bytes).
+ *
+ * @param[in] ctx
+ *   The EC J-PAKE context to use. This must be initialized and set up.
+ *
+ * @param[out] buf
+ *   The buffer to write the contents to. This must be a writable buffer of
+ *   length @p len bytes.
+ *
+ * @param[in] len
+ *   The length of @p buf in bytes.
+ *
+ * @param[out] olen
+ *   The address at which to store the total number of bytes written to @p buf.
+ *   This must not be @c NULL.
+ *
+ * @return
+ *   SL_STATUS_OK when the command was executed successfully, otherwise an
+ *   appropriate error code (@ref sl_status.h).
+ ******************************************************************************/
+sl_status_t sl_se_ecjpake_write_round_one(sl_se_ecjpake_context_t *ctx,
+                                          unsigned char *buf,
+                                          size_t len,
+                                          size_t *olen);
+
+/***************************************************************************//**
+ * @brief
+ *   Generate and write the second round message (TLS: contents of the
+ *   Client/ServerKeyExchange).
+ *
+ * @param[in] ctx
+ *   The EC J-PAKE context to use. This must be initialized, set up, and already
+ *   have performed round one.
+ *
+ * @param[out] buf
+ *   The buffer to write the round two contents to. This must be a writable
+ *   buffer of length @p len bytes.
+ *
+ * @param[in] len
+ *   The size of @p buf in bytes.
+ *
+ * @param[out] olen
+ *   The address at which to store the total number of bytes written to @p buf.
+ *   This must not be @c NULL.
+ *
+ * @return
+ *   SL_STATUS_OK when the command was executed successfully, otherwise an
+ *   appropriate error code (@ref sl_status.h).
+ ******************************************************************************/
+sl_status_t sl_se_ecjpake_write_round_two(sl_se_ecjpake_context_t *ctx,
+                                          unsigned char *buf,
+                                          size_t len,
+                                          size_t *olen);
+
+// -------------------------------
+// Key derivation functions
+
+#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)
+/***************************************************************************//**
+ * @brief
+ *   Derive a pseudorandom key from the input key material using HKDF.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[in] in_key
+ *   Pointer to the input key material.
+ *
+ * @param[in] hash
+ *   Which hashing algorithm to use.
+ *
+ * @param[in] salt
+ *   An optional salt value (a non-secret random value).
+ *
+ * @param[in] salt_len
+ *   The length of the salt.
+ *
+ * @param[in] info
+ *   An optional context and application specific information string.
+ *
+ * @param[in] info_len
+ *   The length of info.
+ *
+ * @param[in,out] out_key
+ *   Pointer to the generated key material. The length member of out_key is
+ *   used to request a given length of the generated key.
+ *
+ * @return
+ *   SL_STATUS_OK if the signature is successfully verified, otherwise an
+ *   appropriate error code (@ref sl_status.h).
+ ******************************************************************************/
+sl_status_t sl_se_derive_key_hkdf(sl_se_command_context_t *cmd_ctx,
+                                  const sl_se_key_descriptor_t *in_key,
+                                  sl_se_hash_type_t hash,
+                                  const unsigned char *salt,
+                                  size_t salt_len,
+                                  const unsigned char *info,
+                                  size_t info_len,
+                                  sl_se_key_descriptor_t *out_key);
+
+/***************************************************************************//**
+ * @brief
+ *   Derive a pseudorandom key from the input key material using PBKDF2.
+ *
+ * @param[in] cmd_ctx
+ *   Pointer to an SE command context object.
+ *
+ * @param[in] in_key
+ *   Pointer to the input key material.
+ *
+ * @param[in] prf
+ *   The underlying psuedorandom function (PRF) to use in the algorithm. The
+ *   most common choice of HMAC-SHA-{1, 224, 256, 384, 512} is supported on all
+ *   Series-2 devices (with Vault High Security). Newer chips, EFR32xG23 and
+ *   later, also support usage of AES-CMAC-PRF-128.
+ *
+ * @param[in] salt
+ *   An optional salt value (a non-secret random value).
+ *
+ * @param[in] salt_len
+ *   The length of the salt.
+ *
+ * @param[in] iterations
+ *   The number of iterations to use. Up to 16384 iterations is supported.
+ *
+ * @param[in,out] out_key
+ *   Pointer to the generated key material. The length member of out_key is
+ *   used to request a given length of the generated key.
+ *
+ * @return
+ *   SL_STATUS_OK if the signature is successfully verified, otherwise an
+ *   appropriate error code (@ref sl_status.h).
+ ******************************************************************************/
+sl_status_t sl_se_derive_key_pbkdf2(sl_se_command_context_t *cmd_ctx,
+                                    const sl_se_key_descriptor_t *in_key,
+                                    sl_se_pbkdf2_prf_type_t prf,
+                                    const unsigned char *salt,
+                                    size_t salt_len,
+                                    uint32_t iterations,
+                                    sl_se_key_descriptor_t *out_key);
+
+#endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)
+
+#ifdef __cplusplus
+}
+#endif
+
+/// @} (end addtogroup sl_se_manager_key_derivation)
+/// @} (end addtogroup sl_se_manager)
+
+#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED)
+
+#endif // SL_SE_MANAGER_KEY_DERIVATION_H