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GClarkson
2025-04-12 23:37:19 +01:00
parent 264a3462e0
commit 9d06f983af
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Libs/platform/bootloader/core/btl_util.h Normal file
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#ifndef BTL_UTIL_H
#define BTL_UTIL_H
#define BTL_STR_HELPER(x) #x
#define QUOTE(x) BTL_STR_HELPER(x)
#if defined(__CSTAT__)
#define MISRAC_DISABLE _Pragma( \
"cstat_disable= \
\"MISRAC2012-Dir-4.3\",\"MISRAC2012-Dir-4.4\",\"MISRAC2012-Dir-4.5\", \
\"MISRAC2012-Dir-4.6_a\",\"MISRAC2012-Dir-4.6_b\",\"MISRAC2012-Dir-4.7_a\", \
\"MISRAC2012-Dir-4.7_b\",\"MISRAC2012-Dir-4.7_c\",\"MISRAC2012-Dir-4.8\", \
\"MISRAC2012-Dir-4.9\",\"MISRAC2012-Dir-4.10\",\"MISRAC2012-Dir-4.11_a\", \
\"MISRAC2012-Dir-4.11_b\",\"MISRAC2012-Dir-4.11_c\",\"MISRAC2012-Dir-4.11_d\", \
\"MISRAC2012-Dir-4.11_e\",\"MISRAC2012-Dir-4.11_f\",\"MISRAC2012-Dir-4.11_g\", \
\"MISRAC2012-Dir-4.11_h\",\"MISRAC2012-Dir-4.11_i\",\"MISRAC2012-Dir-4.12\", \
\"MISRAC2012-Dir-4.13_b\",\"MISRAC2012-Dir-4.13_c\",\"MISRAC2012-Dir-4.13_d\", \
\"MISRAC2012-Dir-4.13_e\",\"MISRAC2012-Dir-4.13_f\",\"MISRAC2012-Dir-4.13_g\", \
\"MISRAC2012-Dir-4.13_h\",\"MISRAC2012-Rule-1.3_a\",\"MISRAC2012-Rule-1.3_b\", \
\"MISRAC2012-Rule-1.3_c\",\"MISRAC2012-Rule-1.3_d\",\"MISRAC2012-Rule-1.3_e\", \
\"MISRAC2012-Rule-1.3_f\",\"MISRAC2012-Rule-1.3_g\",\"MISRAC2012-Rule-1.3_h\", \
\"MISRAC2012-Rule-1.3_i\",\"MISRAC2012-Rule-1.3_j\",\"MISRAC2012-Rule-1.3_k\", \
\"MISRAC2012-Rule-1.3_m\",\"MISRAC2012-Rule-1.3_n\",\"MISRAC2012-Rule-1.3_o\", \
\"MISRAC2012-Rule-1.3_p\",\"MISRAC2012-Rule-1.3_q\",\"MISRAC2012-Rule-1.3_r\", \
\"MISRAC2012-Rule-1.3_s\",\"MISRAC2012-Rule-1.3_t\",\"MISRAC2012-Rule-1.3_u\", \
\"MISRAC2012-Rule-1.3_v\",\"MISRAC2012-Rule-1.3_w\",\"MISRAC2012-Rule-2.1_a\", \
\"MISRAC2012-Rule-2.1_b\",\"MISRAC2012-Rule-2.2_a\",\"MISRAC2012-Rule-2.2_b\", \
\"MISRAC2012-Rule-2.2_c\",\"MISRAC2012-Rule-2.3\",\"MISRAC2012-Rule-2.4\", \
\"MISRAC2012-Rule-2.5\",\"MISRAC2012-Rule-2.6\",\"MISRAC2012-Rule-2.7\", \
\"MISRAC2012-Rule-3.1\",\"MISRAC2012-Rule-3.2\",\"MISRAC2012-Rule-5.1\", \
\"MISRAC2012-Rule-5.2_c89\",\"MISRAC2012-Rule-5.2_c99\", \
\"MISRAC2012-Rule-5.3_c89\",\"MISRAC2012-Rule-5.3_c99\", \
\"MISRAC2012-Rule-5.4_c89\",\"MISRAC2012-Rule-5.4_c99\", \
\"MISRAC2012-Rule-5.5_c89\",\"MISRAC2012-Rule-5.5_c99\", \
\"MISRAC2012-Rule-5.6\",\"MISRAC2012-Rule-5.7\",\"MISRAC2012-Rule-5.8\", \
\"MISRAC2012-Rule-5.9\",\"MISRAC2012-Rule-6.1\",\"MISRAC2012-Rule-6.2\", \
\"MISRAC2012-Rule-7.1\",\"MISRAC2012-Rule-7.2\",\"MISRAC2012-Rule-7.3\", \
\"MISRAC2012-Rule-7.4_a\",\"MISRAC2012-Rule-7.4_b\",\"MISRAC2012-Rule-8.1\", \
\"MISRAC2012-Rule-8.2_a\",\"MISRAC2012-Rule-8.2_b\",\"MISRAC2012-Rule-8.3_b\", \
\"MISRAC2012-Rule-8.4\",\"MISRAC2012-Rule-8.5_a\",\"MISRAC2012-Rule-8.5_b\", \
\"MISRAC2012-Rule-8.6\",\"MISRAC2012-Rule-8.7\",\"MISRAC2012-Rule-8.9_a\", \
\"MISRAC2012-Rule-8.9_b\",\"MISRAC2012-Rule-8.10\",\"MISRAC2012-Rule-8.11\", \
\"MISRAC2012-Rule-8.12\",\"MISRAC2012-Rule-8.13\",\"MISRAC2012-Rule-8.14\", \
\"MISRAC2012-Rule-9.1_a\",\"MISRAC2012-Rule-9.1_b\",\"MISRAC2012-Rule-9.1_c\", \
\"MISRAC2012-Rule-9.1_d\",\"MISRAC2012-Rule-9.1_e\",\"MISRAC2012-Rule-9.1_f\", \
\"MISRAC2012-Rule-9.2\",\"MISRAC2012-Rule-9.3\",\"MISRAC2012-Rule-9.4\", \
\"MISRAC2012-Rule-9.5_a\",\"MISRAC2012-Rule-9.5_b\",\"MISRAC2012-Rule-10.1_R2\", \
\"MISRAC2012-Rule-10.1_R3\",\"MISRAC2012-Rule-10.1_R4\", \
\"MISRAC2012-Rule-10.1_R5\",\"MISRAC2012-Rule-10.1_R6\", \
\"MISRAC2012-Rule-10.1_R7\",\"MISRAC2012-Rule-10.1_R8\", \
\"MISRAC2012-Rule-10.2\",\"MISRAC2012-Rule-10.3\",\"MISRAC2012-Rule-10.4_a\", \
\"MISRAC2012-Rule-10.4_b\",\"MISRAC2012-Rule-10.5\",\"MISRAC2012-Rule-10.6\", \
\"MISRAC2012-Rule-10.7\",\"MISRAC2012-Rule-10.8\",\"MISRAC2012-Rule-11.1\", \
\"MISRAC2012-Rule-11.2\",\"MISRAC2012-Rule-11.3\",\"MISRAC2012-Rule-11.4\", \
\"MISRAC2012-Rule-11.5\",\"MISRAC2012-Rule-11.6\",\"MISRAC2012-Rule-11.7\", \
\"MISRAC2012-Rule-11.8\",\"MISRAC2012-Rule-11.9\",\"MISRAC2012-Rule-12.1\", \
\"MISRAC2012-Rule-12.2\",\"MISRAC2012-Rule-12.3\",\"MISRAC2012-Rule-13.1\", \
\"MISRAC2012-Rule-13.2_a\",\"MISRAC2012-Rule-13.2_b\",\"MISRAC2012-Rule-13.2_c\", \
\"MISRAC2012-Rule-13.3\",\"MISRAC2012-Rule-13.4_a\",\"MISRAC2012-Rule-13.4_b\", \
\"MISRAC2012-Rule-13.5\",\"MISRAC2012-Rule-13.6\",\"MISRAC2012-Rule-14.1_a\", \
\"MISRAC2012-Rule-14.1_b\",\"MISRAC2012-Rule-14.2\",\"MISRAC2012-Rule-14.3_a\", \
\"MISRAC2012-Rule-14.3_b\",\"MISRAC2012-Rule-14.4_a\",\"MISRAC2012-Rule-14.4_b\", \
\"MISRAC2012-Rule-14.4_c\",\"MISRAC2012-Rule-14.4_d\",\"MISRAC2012-Rule-15.1\", \
\"MISRAC2012-Rule-15.2\",\"MISRAC2012-Rule-15.3\",\"MISRAC2012-Rule-15.4\", \
\"MISRAC2012-Rule-15.5\",\"MISRAC2012-Rule-15.6_a\",\"MISRAC2012-Rule-15.6_b\", \
\"MISRAC2012-Rule-15.6_c\",\"MISRAC2012-Rule-15.6_d\",\"MISRAC2012-Rule-15.6_e\", \
\"MISRAC2012-Rule-15.7\",\"MISRAC2012-Rule-16.1\",\"MISRAC2012-Rule-16.2\", \
\"MISRAC2012-Rule-16.3\",\"MISRAC2012-Rule-16.4\",\"MISRAC2012-Rule-16.5\", \
\"MISRAC2012-Rule-16.6\",\"MISRAC2012-Rule-16.7\",\"MISRAC2012-Rule-17.1\", \
\"MISRAC2012-Rule-17.2_a\",\"MISRAC2012-Rule-17.2_b\",\"MISRAC2012-Rule-17.3\", \
\"MISRAC2012-Rule-17.4\",\"MISRAC2012-Rule-17.5\",\"MISRAC2012-Rule-17.6\", \
\"MISRAC2012-Rule-17.7\",\"MISRAC2012-Rule-17.8\",\"MISRAC2012-Rule-18.1_a\", \
\"MISRAC2012-Rule-18.1_b\",\"MISRAC2012-Rule-18.1_c\",\"MISRAC2012-Rule-18.1_d\", \
\"MISRAC2012-Rule-18.2\",\"MISRAC2012-Rule-18.3\",\"MISRAC2012-Rule-18.4\", \
\"MISRAC2012-Rule-18.5\",\"MISRAC2012-Rule-18.6_a\",\"MISRAC2012-Rule-18.6_b\", \
\"MISRAC2012-Rule-18.6_c\",\"MISRAC2012-Rule-18.6_d\",\"MISRAC2012-Rule-18.7\", \
\"MISRAC2012-Rule-18.8\",\"MISRAC2012-Rule-19.1\",\"MISRAC2012-Rule-19.2\", \
\"MISRAC2012-Rule-20.1\",\"MISRAC2012-Rule-20.2\",\"MISRAC2012-Rule-20.4_c89\", \
\"MISRAC2012-Rule-20.4_c99\",\"MISRAC2012-Rule-20.5\",\"MISRAC2012-Rule-20.7\", \
\"MISRAC2012-Rule-20.10\",\"MISRAC2012-Rule-21.1\",\"MISRAC2012-Rule-21.2\", \
\"MISRAC2012-Rule-21.3\",\"MISRAC2012-Rule-21.4\",\"MISRAC2012-Rule-21.5\", \
\"MISRAC2012-Rule-21.6\",\"MISRAC2012-Rule-21.7\",\"MISRAC2012-Rule-21.8\", \
\"MISRAC2012-Rule-21.9\",\"MISRAC2012-Rule-21.10\",\"MISRAC2012-Rule-21.11\", \
\"MISRAC2012-Rule-21.12_a\",\"MISRAC2012-Rule-21.12_b\",\"MISRAC2012-Rule-22.1_a\", \
\"MISRAC2012-Rule-22.1_b\",\"MISRAC2012-Rule-22.2_a\",\"MISRAC2012-Rule-22.2_b\", \
\"MISRAC2012-Rule-22.2_c\",\"MISRAC2012-Rule-22.3\",\"MISRAC2012-Rule-22.4\", \
\"MISRAC2012-Rule-22.5_a\",\"MISRAC2012-Rule-22.5_b\",\"MISRAC2012-Rule-22.6\"")
#define MISRAC_ENABLE _Pragma( \
"cstat_restore= \
\"MISRAC2012-Dir-4.3\",\"MISRAC2012-Dir-4.4\",\"MISRAC2012-Dir-4.5\", \
\"MISRAC2012-Dir-4.6_a\",\"MISRAC2012-Dir-4.6_b\",\"MISRAC2012-Dir-4.7_a\", \
\"MISRAC2012-Dir-4.7_b\",\"MISRAC2012-Dir-4.7_c\",\"MISRAC2012-Dir-4.8\", \
\"MISRAC2012-Dir-4.9\",\"MISRAC2012-Dir-4.10\",\"MISRAC2012-Dir-4.11_a\", \
\"MISRAC2012-Dir-4.11_b\",\"MISRAC2012-Dir-4.11_c\",\"MISRAC2012-Dir-4.11_d\", \
\"MISRAC2012-Dir-4.11_e\",\"MISRAC2012-Dir-4.11_f\",\"MISRAC2012-Dir-4.11_g\", \
\"MISRAC2012-Dir-4.11_h\",\"MISRAC2012-Dir-4.11_i\",\"MISRAC2012-Dir-4.12\", \
\"MISRAC2012-Dir-4.13_b\",\"MISRAC2012-Dir-4.13_c\",\"MISRAC2012-Dir-4.13_d\", \
\"MISRAC2012-Dir-4.13_e\",\"MISRAC2012-Dir-4.13_f\",\"MISRAC2012-Dir-4.13_g\", \
\"MISRAC2012-Dir-4.13_h\",\"MISRAC2012-Rule-1.3_a\",\"MISRAC2012-Rule-1.3_b\", \
\"MISRAC2012-Rule-1.3_c\",\"MISRAC2012-Rule-1.3_d\",\"MISRAC2012-Rule-1.3_e\", \
\"MISRAC2012-Rule-1.3_f\",\"MISRAC2012-Rule-1.3_g\",\"MISRAC2012-Rule-1.3_h\", \
\"MISRAC2012-Rule-1.3_i\",\"MISRAC2012-Rule-1.3_j\",\"MISRAC2012-Rule-1.3_k\", \
\"MISRAC2012-Rule-1.3_m\",\"MISRAC2012-Rule-1.3_n\",\"MISRAC2012-Rule-1.3_o\", \
\"MISRAC2012-Rule-1.3_p\",\"MISRAC2012-Rule-1.3_q\",\"MISRAC2012-Rule-1.3_r\", \
\"MISRAC2012-Rule-1.3_s\",\"MISRAC2012-Rule-1.3_t\",\"MISRAC2012-Rule-1.3_u\", \
\"MISRAC2012-Rule-1.3_v\",\"MISRAC2012-Rule-1.3_w\",\"MISRAC2012-Rule-2.1_a\", \
\"MISRAC2012-Rule-2.1_b\",\"MISRAC2012-Rule-2.2_a\",\"MISRAC2012-Rule-2.2_b\", \
\"MISRAC2012-Rule-2.2_c\",\"MISRAC2012-Rule-2.3\",\"MISRAC2012-Rule-2.4\", \
\"MISRAC2012-Rule-2.5\",\"MISRAC2012-Rule-2.6\",\"MISRAC2012-Rule-2.7\", \
\"MISRAC2012-Rule-3.1\",\"MISRAC2012-Rule-3.2\",\"MISRAC2012-Rule-5.1\", \
\"MISRAC2012-Rule-5.2_c89\",\"MISRAC2012-Rule-5.2_c99\", \
\"MISRAC2012-Rule-5.3_c89\",\"MISRAC2012-Rule-5.3_c99\", \
\"MISRAC2012-Rule-5.4_c89\",\"MISRAC2012-Rule-5.4_c99\", \
\"MISRAC2012-Rule-5.5_c89\",\"MISRAC2012-Rule-5.5_c99\", \
\"MISRAC2012-Rule-5.6\",\"MISRAC2012-Rule-5.7\",\"MISRAC2012-Rule-5.8\", \
\"MISRAC2012-Rule-5.9\",\"MISRAC2012-Rule-6.1\",\"MISRAC2012-Rule-6.2\", \
\"MISRAC2012-Rule-7.1\",\"MISRAC2012-Rule-7.2\",\"MISRAC2012-Rule-7.3\", \
\"MISRAC2012-Rule-7.4_a\",\"MISRAC2012-Rule-7.4_b\",\"MISRAC2012-Rule-8.1\", \
\"MISRAC2012-Rule-8.2_a\",\"MISRAC2012-Rule-8.2_b\",\"MISRAC2012-Rule-8.3_b\", \
\"MISRAC2012-Rule-8.4\",\"MISRAC2012-Rule-8.5_a\",\"MISRAC2012-Rule-8.5_b\", \
\"MISRAC2012-Rule-8.6\",\"MISRAC2012-Rule-8.7\",\"MISRAC2012-Rule-8.9_a\", \
\"MISRAC2012-Rule-8.9_b\",\"MISRAC2012-Rule-8.10\",\"MISRAC2012-Rule-8.11\", \
\"MISRAC2012-Rule-8.12\",\"MISRAC2012-Rule-8.13\",\"MISRAC2012-Rule-8.14\", \
\"MISRAC2012-Rule-9.1_a\",\"MISRAC2012-Rule-9.1_b\",\"MISRAC2012-Rule-9.1_c\", \
\"MISRAC2012-Rule-9.1_d\",\"MISRAC2012-Rule-9.1_e\",\"MISRAC2012-Rule-9.1_f\", \
\"MISRAC2012-Rule-9.2\",\"MISRAC2012-Rule-9.3\",\"MISRAC2012-Rule-9.4\", \
\"MISRAC2012-Rule-9.5_a\",\"MISRAC2012-Rule-9.5_b\",\"MISRAC2012-Rule-10.1_R2\", \
\"MISRAC2012-Rule-10.1_R3\",\"MISRAC2012-Rule-10.1_R4\", \
\"MISRAC2012-Rule-10.1_R5\",\"MISRAC2012-Rule-10.1_R6\", \
\"MISRAC2012-Rule-10.1_R7\",\"MISRAC2012-Rule-10.1_R8\", \
\"MISRAC2012-Rule-10.2\",\"MISRAC2012-Rule-10.3\",\"MISRAC2012-Rule-10.4_a\", \
\"MISRAC2012-Rule-10.4_b\",\"MISRAC2012-Rule-10.5\",\"MISRAC2012-Rule-10.6\", \
\"MISRAC2012-Rule-10.7\",\"MISRAC2012-Rule-10.8\",\"MISRAC2012-Rule-11.1\", \
\"MISRAC2012-Rule-11.2\",\"MISRAC2012-Rule-11.3\",\"MISRAC2012-Rule-11.4\", \
\"MISRAC2012-Rule-11.5\",\"MISRAC2012-Rule-11.6\",\"MISRAC2012-Rule-11.7\", \
\"MISRAC2012-Rule-11.8\",\"MISRAC2012-Rule-11.9\",\"MISRAC2012-Rule-12.1\", \
\"MISRAC2012-Rule-12.2\",\"MISRAC2012-Rule-12.3\",\"MISRAC2012-Rule-13.1\", \
\"MISRAC2012-Rule-13.2_a\",\"MISRAC2012-Rule-13.2_b\",\"MISRAC2012-Rule-13.2_c\", \
\"MISRAC2012-Rule-13.3\",\"MISRAC2012-Rule-13.4_a\",\"MISRAC2012-Rule-13.4_b\", \
\"MISRAC2012-Rule-13.5\",\"MISRAC2012-Rule-13.6\",\"MISRAC2012-Rule-14.1_a\", \
\"MISRAC2012-Rule-14.1_b\",\"MISRAC2012-Rule-14.2\",\"MISRAC2012-Rule-14.3_a\", \
\"MISRAC2012-Rule-14.3_b\",\"MISRAC2012-Rule-14.4_a\",\"MISRAC2012-Rule-14.4_b\", \
\"MISRAC2012-Rule-14.4_c\",\"MISRAC2012-Rule-14.4_d\",\"MISRAC2012-Rule-15.1\", \
\"MISRAC2012-Rule-15.2\",\"MISRAC2012-Rule-15.3\",\"MISRAC2012-Rule-15.4\", \
\"MISRAC2012-Rule-15.5\",\"MISRAC2012-Rule-15.6_a\",\"MISRAC2012-Rule-15.6_b\", \
\"MISRAC2012-Rule-15.6_c\",\"MISRAC2012-Rule-15.6_d\",\"MISRAC2012-Rule-15.6_e\", \
\"MISRAC2012-Rule-15.7\",\"MISRAC2012-Rule-16.1\",\"MISRAC2012-Rule-16.2\", \
\"MISRAC2012-Rule-16.3\",\"MISRAC2012-Rule-16.4\",\"MISRAC2012-Rule-16.5\", \
\"MISRAC2012-Rule-16.6\",\"MISRAC2012-Rule-16.7\",\"MISRAC2012-Rule-17.1\", \
\"MISRAC2012-Rule-17.2_a\",\"MISRAC2012-Rule-17.2_b\",\"MISRAC2012-Rule-17.3\", \
\"MISRAC2012-Rule-17.4\",\"MISRAC2012-Rule-17.5\",\"MISRAC2012-Rule-17.6\", \
\"MISRAC2012-Rule-17.7\",\"MISRAC2012-Rule-17.8\",\"MISRAC2012-Rule-18.1_a\", \
\"MISRAC2012-Rule-18.1_b\",\"MISRAC2012-Rule-18.1_c\",\"MISRAC2012-Rule-18.1_d\", \
\"MISRAC2012-Rule-18.2\",\"MISRAC2012-Rule-18.3\",\"MISRAC2012-Rule-18.4\", \
\"MISRAC2012-Rule-18.5\",\"MISRAC2012-Rule-18.6_a\",\"MISRAC2012-Rule-18.6_b\", \
\"MISRAC2012-Rule-18.6_c\",\"MISRAC2012-Rule-18.6_d\",\"MISRAC2012-Rule-18.7\", \
\"MISRAC2012-Rule-18.8\",\"MISRAC2012-Rule-19.1\",\"MISRAC2012-Rule-19.2\", \
\"MISRAC2012-Rule-20.1\",\"MISRAC2012-Rule-20.2\",\"MISRAC2012-Rule-20.4_c89\", \
\"MISRAC2012-Rule-20.4_c99\",\"MISRAC2012-Rule-20.5\",\"MISRAC2012-Rule-20.7\", \
\"MISRAC2012-Rule-20.10\",\"MISRAC2012-Rule-21.1\",\"MISRAC2012-Rule-21.2\", \
\"MISRAC2012-Rule-21.3\",\"MISRAC2012-Rule-21.4\",\"MISRAC2012-Rule-21.5\", \
\"MISRAC2012-Rule-21.6\",\"MISRAC2012-Rule-21.7\",\"MISRAC2012-Rule-21.8\", \
\"MISRAC2012-Rule-21.9\",\"MISRAC2012-Rule-21.10\",\"MISRAC2012-Rule-21.11\", \
\"MISRAC2012-Rule-21.12_a\",\"MISRAC2012-Rule-21.12_b\",\"MISRAC2012-Rule-22.1_a\", \
\"MISRAC2012-Rule-22.1_b\",\"MISRAC2012-Rule-22.2_a\",\"MISRAC2012-Rule-22.2_b\", \
\"MISRAC2012-Rule-22.2_c\",\"MISRAC2012-Rule-22.3\",\"MISRAC2012-Rule-22.4\", \
\"MISRAC2012-Rule-22.5_a\",\"MISRAC2012-Rule-22.5_b\",\"MISRAC2012-Rule-22.6\"")
#elif defined(__ICCARM__)
#define MISRAC_DISABLE _Pragma( \
"diag_suppress= \
Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
Pm155")
#define MISRAC_ENABLE _Pragma( \
"diag_default= \
Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
Pm155")
#else
#define MISRAC_DISABLE
#define MISRAC_ENABLE
#endif
#endif

233
Libs/platform/bootloader/core/flash/btl_internal_flash.c Normal file
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/***************************************************************************//**
* @file
* @brief Abstraction of internal flash read and write routines.
*******************************************************************************
* # License
* <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* The licensor of this software is Silicon Laboratories Inc. Your use of this
* software is governed by the terms of Silicon Labs Master Software License
* Agreement (MSLA) available at
* www.silabs.com/about-us/legal/master-software-license-agreement. This
* software is distributed to you in Source Code format and is governed by the
* sections of the MSLA applicable to Source Code.
*
******************************************************************************/
#include "core/flash/btl_internal_flash.h"
#include "core/btl_util.h"
MISRAC_DISABLE
#include "em_cmu.h"
#include "em_msc.h"
MISRAC_ENABLE
#if !defined(_SILICON_LABS_32B_SERIES_2)
static MSC_Status_TypeDef writeHalfword(uint32_t address,
uint16_t data);
static MSC_Status_TypeDef writeHalfwordDMA(uint32_t address,
uint16_t data,
int ch);
static MSC_Status_TypeDef writeHalfword(uint32_t address,
uint16_t data)
{
uint32_t address32, data32;
MSC_Status_TypeDef retval;
address32 = address & ~3UL;
if (address & 2UL) {
data32 = 0x0000FFFFUL | ((uint32_t)data << 16UL);
} else {
data32 = 0xFFFF0000UL | (uint32_t)data;
}
retval = MSC_WriteWord((uint32_t *)address32, &data32, 4U);
return retval;
}
static MSC_Status_TypeDef writeHalfwordDMA(uint32_t address,
uint16_t data,
int ch)
{
uint32_t address32, data32;
MSC_Status_TypeDef retval;
address32 = address & ~3UL;
if (address & 2UL) {
data32 = 0x0000FFFFUL | ((uint32_t)data << 16UL);
} else {
data32 = 0xFFFF0000UL | (uint32_t)data;
}
// ch is verified by flash_writeBuffer_dma, which calls this function.
retval = MSC_WriteWordDma(ch, (uint32_t *)address32, &data32, 4U);
return retval;
}
#endif // !defined(_SILICON_LABS_32B_SERIES_2)
bool flash_erasePage(uint32_t address)
{
#if defined(_CMU_CLKEN1_MASK)
CMU->CLKEN1_SET = CMU_CLKEN1_MSC;
#endif
MSC_Status_TypeDef retval = MSC_ErasePage((uint32_t *)address);
if (retval == mscReturnOk) {
return true;
} else {
return false;
}
}
bool flash_writeBuffer_dma(uint32_t address,
const void *data,
size_t length,
int ch)
{
MSC_Status_TypeDef retval = mscReturnOk;
if ((ch < 0) || (ch >= (int)DMA_CHAN_COUNT)) {
return false;
}
MISRAC_DISABLE
CMU_ClockEnable(cmuClock_LDMA, true);
#if defined(CMU_CLKEN0_LDMAXBAR)
CMU_ClockEnable(cmuClock_LDMAXBAR, true);
#endif
MISRAC_ENABLE
if (length == 0UL) {
// Attempt to write zero-length array, return immediately
return true;
}
#if defined(_SILICON_LABS_32B_SERIES_2)
if ((address & 3UL) || (length & 3UL)) {
// Unaligned write, return early
return false;
}
#if defined(_CMU_CLKEN1_MASK)
CMU->CLKEN1_SET = CMU_CLKEN1_MSC;
#endif
retval = MSC_WriteWordDma(ch, (uint32_t *)address, data, length);
#else
uint16_t * data16 = (uint16_t *)data;
if ((address & 1UL) || (length & 1UL)) {
// Unaligned write, return early
return false;
}
// Flash unaligned data at start
if (address & 2UL) {
if ((writeHalfwordDMA(address, *data16, ch)) != mscReturnOk) {
return false;
}
address += 2UL;
length -= 2UL;
data16++;
}
// Flash word-aligned data
if (length >= 4UL) {
uint32_t length16 = (length & ~3UL);
retval = MSC_WriteWordDma(ch, (uint32_t *)address, data16, length16);
data16 += length16 / sizeof(uint16_t);
address += length16;
length -= length16;
}
if (retval != mscReturnOk) {
return false;
}
// Flash unaligned data at end
if (length > 0UL) {
retval = writeHalfwordDMA(address, *data16, ch);
address += 2UL;
length -= 2UL;
}
#endif // #if defined(_SILICON_LABS_32B_SERIES_2)
if (retval == mscReturnOk) {
return true;
} else {
return false;
}
}
bool flash_writeBuffer(uint32_t address,
const void *data,
size_t length)
{
MSC_Status_TypeDef retval = mscReturnOk;
if (length == 0UL) {
// Attempt to write zero-length array, return immediately
return true;
}
#if defined(_SILICON_LABS_32B_SERIES_2)
if ((address & 3UL) || (length & 3UL)) {
// Unaligned write, return early
return false;
}
#if defined(_CMU_CLKEN1_MASK)
CMU->CLKEN1_SET = CMU_CLKEN1_MSC;
#endif
retval = MSC_WriteWord((uint32_t *)address, data, length);
#else
uint16_t * data16 = (uint16_t *)data;
if ((address & 1UL) || (length & 1UL)) {
// Unaligned write, return early
return false;
}
// Flash unaligned data at start
if (address & 2UL) {
if ((writeHalfword(address, *data16)) != mscReturnOk) {
return false;
}
address += 2UL;
length -= 2UL;
data16++;
}
// Flash word-aligned data
if (length >= 4UL) {
uint32_t length16 = (length & ~3UL);
retval = MSC_WriteWord((uint32_t *)address, data16, length16);
data16 += length16 / sizeof(uint16_t);
address += length16;
length -= length16;
}
if (retval != mscReturnOk) {
return false;
}
// Flash unaligned data at end
if (length > 0UL) {
retval = writeHalfword(address, *data16);
address += 2UL;
length -= 2UL;
}
#endif // #if defined(_SILICON_LABS_32B_SERIES_2)
if (retval == mscReturnOk) {
return true;
} else {
return false;
}
}

84
Libs/platform/bootloader/core/flash/btl_internal_flash.h Normal file
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/***************************************************************************//**
* @file
* @brief Abstraction of internal flash read and write routines.
*******************************************************************************
* # License
* <b>Copyright 2021 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* The licensor of this software is Silicon Laboratories Inc. Your use of this
* software is governed by the terms of Silicon Labs Master Software License
* Agreement (MSLA) available at
* www.silabs.com/about-us/legal/master-software-license-agreement. This
* software is distributed to you in Source Code format and is governed by the
* sections of the MSLA applicable to Source Code.
*
******************************************************************************/
#ifndef BTL_INTERNAL_FLASH_H
#define BTL_INTERNAL_FLASH_H
#include "core/btl_util.h"
MISRAC_DISABLE
#include "em_device.h"
MISRAC_ENABLE
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
/***************************************************************************//**
* @addtogroup Core Bootloader Core
* @{
* @addtogroup Flash
* @brief Interface to internal flash
* @details Used for writing application images to the main flash.
* @{
******************************************************************************/
// -----------------------------------------------------------------------------
// Defines
/// DMA Channel for MSC write
#define SL_GBL_MSC_LDMA_CHANNEL 2
// -----------------------------------------------------------------------------
// Prototypes
/**
* Erase a flash page.
*
* @param[in] address Start address of the flash page to erase.
* @return True if operation was successful
*/
bool flash_erasePage(uint32_t address);
/**
* Write buffer to internal flash.
*
* @param address Starting address to write data to. Must be half-word aligned.
* @param data Data buffer to write to internal flash
* @param length Amount of bytes in the data buffer to write
* @param ch DMA channel to use
* @return True if operation was successful
*/
bool flash_writeBuffer_dma(uint32_t address,
const void *data,
size_t length,
int ch);
/**
* Write buffer to internal flash.
*
* @param address Starting address to write data to. Must be half-word aligned.
* @param data Data buffer to write to internal flash
* @param length Amount of bytes in the data buffer to write
* @return True if operation was successful
*/
bool flash_writeBuffer(uint32_t address,
const void *data,
size_t length);
/** @} addtogroup internal_flash */
/** @} addtogroup core */
#endif // BTL_INTERNAL_FLASH_H