1094 lines
54 KiB
C
1094 lines
54 KiB
C
/***************************************************************************//**
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* @file
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* @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
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* peripheral API
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*******************************************************************************
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* # License
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* <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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******************************************************************************/
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#ifndef EM_USART_H
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#define EM_USART_H
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#include "em_device.h"
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#if defined(USART_COUNT) && (USART_COUNT > 0)
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************************************************************//**
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* @addtogroup usart USART - Synchronous/Asynchronous Serial
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* @brief Universal Synchronous/Asynchronous Receiver/Transmitter
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* Peripheral API
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* @details
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* The Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
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* is a very flexible serial I/O module. It supports full duplex asynchronous UART
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* communication as well as RS-485, SPI, MicroWire, and 3-wire. It can also interface
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* with ISO7816 Smart-Cards, and IrDA devices.
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*
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* The USART has a wide selection of operating modes, frame formats, and baud rates.
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* All features are supported through the API of this module.
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*
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* Triple buffering and DMA support makes high data-rates possible with minimal
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* CPU intervention. It is possible to transmit and receive large frames while
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* the MCU remains in EM1 Sleep.
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*
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* This module does not support DMA configuration. The UARTDRV and SPIDRV drivers
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* provide full support for DMA and more.
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*
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* The following steps are necessary for basic operation:
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*
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* Clock enable:
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* @include em_usart_clock_enable.c
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*
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* To initialize the USART for asynchronous operation (e.g., UART):
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* @include em_usart_init_async.c
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*
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* To initialize the USART for synchronous operation (e.g., SPI):
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* @include em_usart_init_sync.c
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*
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* After pins are assigned for the application/board, enable pins at the
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* desired location. Available locations can be obtained from the Pin Definitions
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* section in the data sheet.
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* @if DOXYDOC_P1_DEVICE
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* @include em_usart_route_p1.c
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* @note UART hardware flow control is not directly supported in hardware on
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* _SILICON_LABS_32B_SERIES_0 parts.
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* @endif
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* @if DOXYDOC_P2_DEVICE
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* @include em_usart_route_p2.c
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* @endif
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* @note UARTDRV supports all types of UART flow control. Software assisted
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* hardware flow control is available for parts without true UART hardware
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* flow control.
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* @{
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******************************************************************************/
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/*******************************************************************************
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******************************** ENUMS ************************************
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******************************************************************************/
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/** Databit selection. */
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typedef enum {
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usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 data bits (not available for UART). */
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usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 data bits (not available for UART). */
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usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 data bits (not available for UART). */
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usartDatabits7 = USART_FRAME_DATABITS_SEVEN, /**< 7 data bits (not available for UART). */
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usartDatabits8 = USART_FRAME_DATABITS_EIGHT, /**< 8 data bits. */
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usartDatabits9 = USART_FRAME_DATABITS_NINE, /**< 9 data bits. */
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usartDatabits10 = USART_FRAME_DATABITS_TEN, /**< 10 data bits (not available for UART). */
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usartDatabits11 = USART_FRAME_DATABITS_ELEVEN, /**< 11 data bits (not available for UART). */
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usartDatabits12 = USART_FRAME_DATABITS_TWELVE, /**< 12 data bits (not available for UART). */
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usartDatabits13 = USART_FRAME_DATABITS_THIRTEEN, /**< 13 data bits (not available for UART). */
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usartDatabits14 = USART_FRAME_DATABITS_FOURTEEN, /**< 14 data bits (not available for UART). */
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usartDatabits15 = USART_FRAME_DATABITS_FIFTEEN, /**< 15 data bits (not available for UART). */
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usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 data bits (not available for UART). */
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} USART_Databits_TypeDef;
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/** Enable selection. */
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typedef enum {
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/** Disable both receiver and transmitter. */
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usartDisable = 0x0,
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/** Enable receiver only, transmitter disabled. */
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usartEnableRx = USART_CMD_RXEN,
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/** Enable transmitter only, receiver disabled. */
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usartEnableTx = USART_CMD_TXEN,
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/** Enable both receiver and transmitter. */
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usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN)
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} USART_Enable_TypeDef;
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/** Oversampling selection, used for asynchronous operation. */
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typedef enum {
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usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */
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usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */
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usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */
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usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */
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} USART_OVS_TypeDef;
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/** Parity selection, mainly used for asynchronous operation. */
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typedef enum {
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usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */
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usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */
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usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */
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} USART_Parity_TypeDef;
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/** Stop bits selection, used for asynchronous operation. */
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typedef enum {
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usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stop bits. */
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usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stop bits. */
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usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stop bits. */
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usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stop bits. */
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} USART_Stopbits_TypeDef;
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#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
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/** Hardware Flow Control Selection. */
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typedef enum {
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/** No hardware flow control. */
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usartHwFlowControlNone = 0,
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/** CTS signal is enabled for TX flow control. */
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usartHwFlowControlCts = USART_ROUTEPEN_CTSPEN,
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/** RTS signal is enabled for RX flow control. */
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usartHwFlowControlRts = USART_ROUTEPEN_RTSPEN,
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/** CTS and RTS signals are enabled for TX and RX flow control. */
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usartHwFlowControlCtsAndRts = USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN,
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} USART_HwFlowControl_TypeDef;
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#elif defined(USART_CTRLX_CTSEN)
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/** Hardware Flow Control Selection. */
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typedef enum {
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/** No hardware flow control. */
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usartHwFlowControlNone = 0,
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/** CTS signal is enabled for TX flow control. */
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usartHwFlowControlCts,
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/** RTS signal is enabled for RX flow control. */
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usartHwFlowControlRts,
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/** CTS and RTS signals are enabled for TX and RX flow control. */
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usartHwFlowControlCtsAndRts
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} USART_HwFlowControl_TypeDef;
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#endif
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/** Clock polarity/phase mode. */
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typedef enum {
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/** Clock idle low, sample on rising edge. */
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usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING,
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/** Clock idle low, sample on falling edge. */
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usartClockMode1 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLETRAILING,
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/** Clock idle high, sample on falling edge. */
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usartClockMode2 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLELEADING,
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/** Clock idle high, sample on rising edge. */
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usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING
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} USART_ClockMode_TypeDef;
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/** Pulse width selection for IrDA mode. */
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typedef enum {
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/** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */
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usartIrDAPwONE = USART_IRCTRL_IRPW_ONE,
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/** IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 */
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usartIrDAPwTWO = USART_IRCTRL_IRPW_TWO,
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/** IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 */
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usartIrDAPwTHREE = USART_IRCTRL_IRPW_THREE,
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/** IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 */
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usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR
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} USART_IrDAPw_Typedef;
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/** PRS Channel type */
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typedef uint8_t USART_PRS_Channel_t;
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/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
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/** Deprecated PRS channel selector value.
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* New code should use an integer instead. */
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#define usartIrDAPrsCh0 0U
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#define usartIrDAPrsCh1 1U
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#define usartIrDAPrsCh2 2U
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#define usartIrDAPrsCh3 3U
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#define usartIrDAPrsCh4 4U
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#define usartIrDAPrsCh5 5U
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#define usartIrDAPrsCh6 6U
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#define usartIrDAPrsCh7 7U
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#define usartPrsRxCh0 0U
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#define usartPrsRxCh1 1U
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#define usartPrsRxCh2 2U
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#define usartPrsRxCh3 3U
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#define usartPrsRxCh4 4U
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#define usartPrsRxCh5 5U
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#define usartPrsRxCh6 6U
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#define usartPrsRxCh7 7U
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#define usartPrsRxCh8 8U
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#define usartPrsRxCh9 9U
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#define usartPrsRxCh10 10U
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#define usartPrsRxCh11 11U
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#define usartPrsTriggerCh0 0U
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#define usartPrsTriggerCh1 1U
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#define usartPrsTriggerCh2 2U
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#define usartPrsTriggerCh3 3U
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#define usartPrsTriggerCh4 4U
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#define usartPrsTriggerCh5 5U
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#define usartPrsTriggerCh6 6U
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#define usartPrsTriggerCh7 7U
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/** @endcond */
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#if defined(_USART_I2SCTRL_MASK) && defined(USART_I2SCTRL_I2SEN)
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/** I2S format selection. */
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typedef enum {
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usartI2sFormatW32D32 = USART_I2SCTRL_I2SFORMAT_W32D32, /**< 32-bit word, 32-bit data */
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usartI2sFormatW32D24M = USART_I2SCTRL_I2SFORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */
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usartI2sFormatW32D24 = USART_I2SCTRL_I2SFORMAT_W32D24, /**< 32-bit word, 24-bit data */
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usartI2sFormatW32D16 = USART_I2SCTRL_I2SFORMAT_W32D16, /**< 32-bit word, 16-bit data */
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usartI2sFormatW32D8 = USART_I2SCTRL_I2SFORMAT_W32D8, /**< 32-bit word, 8-bit data */
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usartI2sFormatW16D16 = USART_I2SCTRL_I2SFORMAT_W16D16, /**< 16-bit word, 16-bit data */
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usartI2sFormatW16D8 = USART_I2SCTRL_I2SFORMAT_W16D8, /**< 16-bit word, 8-bit data */
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usartI2sFormatW8D8 = USART_I2SCTRL_I2SFORMAT_W8D8 /**< 8-bit word, 8-bit data */
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} USART_I2sFormat_TypeDef;
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/** I2S frame data justify. */
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typedef enum {
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usartI2sJustifyLeft = USART_I2SCTRL_I2SJUSTIFY_LEFT, /**< Data is left-justified within the frame */
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usartI2sJustifyRight = USART_I2SCTRL_I2SJUSTIFY_RIGHT /**< Data is right-justified within the frame */
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} USART_I2sJustify_TypeDef;
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#elif defined(_USART_I2SCTRL_MASK)
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/** I2S format selection. */
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typedef enum {
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usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data. */
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usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked. */
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usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data. */
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usartI2sFormatW32D16 = USART_I2SCTRL_FORMAT_W32D16, /**< 32-bit word, 16-bit data. */
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usartI2sFormatW32D8 = USART_I2SCTRL_FORMAT_W32D8, /**< 32-bit word, 8-bit data. */
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usartI2sFormatW16D16 = USART_I2SCTRL_FORMAT_W16D16, /**< 16-bit word, 16-bit data. */
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usartI2sFormatW16D8 = USART_I2SCTRL_FORMAT_W16D8, /**< 16-bit word, 8-bit data. */
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usartI2sFormatW8D8 = USART_I2SCTRL_FORMAT_W8D8 /**< 8-bit word, 8-bit data. */
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} USART_I2sFormat_TypeDef;
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/** I2S frame data justify. */
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typedef enum {
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usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame. */
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usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame. */
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} USART_I2sJustify_TypeDef;
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#endif
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/*******************************************************************************
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******************************* STRUCTS ***********************************
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******************************************************************************/
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/** Asynchronous mode initialization structure. */
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typedef struct {
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/** Specifies whether TX and/or RX is enabled when initialization is completed. */
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USART_Enable_TypeDef enable;
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/**
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* USART/UART reference clock assumed when configuring baud rate setup.
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* Set to 0 to use the currently configured reference clock.
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*/
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uint32_t refFreq;
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/** Desired baud rate. */
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uint32_t baudrate;
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/** Oversampling used. */
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USART_OVS_TypeDef oversampling;
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/** Number of data bits in frame. Notice that UART modules only support 8 or
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* 9 data bits. */
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USART_Databits_TypeDef databits;
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/** Parity mode to use. */
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USART_Parity_TypeDef parity;
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/** Number of stop bits to use. */
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USART_Stopbits_TypeDef stopbits;
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#if !defined(_EFM32_GECKO_FAMILY)
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/** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */
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bool mvdis;
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/** Enable USART Rx via PRS. */
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bool prsRxEnable;
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/** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */
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USART_PRS_Channel_t prsRxCh;
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#endif
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/** Auto CS enabling. */
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bool autoCsEnable;
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/** Enable CS invert. By default, chip select is active low.
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* Set to true to make chip select active high. */
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bool csInv;
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#if (_SILICON_LABS_32B_SERIES > 0)
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/** Auto CS hold time in baud cycles. */
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uint8_t autoCsHold;
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/** Auto CS setup time in baud cycles. */
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uint8_t autoCsSetup;
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/** Hardware flow control mode. */
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USART_HwFlowControl_TypeDef hwFlowControl;
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#endif
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} USART_InitAsync_TypeDef;
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/** USART PRS trigger enable. */
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typedef struct {
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#if defined(USART_TRIGCTRL_AUTOTXTEN)
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/** Enable AUTOTX. */
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bool autoTxTriggerEnable;
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#endif
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/** Trigger receive via PRS channel. */
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bool rxTriggerEnable;
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/** Trigger transmit via PRS channel. */
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bool txTriggerEnable;
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/** PRS channel to be used to trigger auto transmission. */
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USART_PRS_Channel_t prsTriggerChannel;
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} USART_PrsTriggerInit_TypeDef;
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/** Default configuration for USART asynchronous initialization structure. */
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#if defined(_EFM32_GECKO_FAMILY)
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/* Default USART Async struct for the EFM32G device */
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#define USART_INITASYNC_DEFAULT \
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{ \
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usartEnable, /* Enable RX/TX when initialization is complete. */ \
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0, /* Use current configured reference clock for configuring baud rate. */ \
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115200, /* 115200 bits/s. */ \
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usartOVS16, /* 16x oversampling. */ \
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usartDatabits8, /* 8 data bits. */ \
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usartNoParity, /* No parity. */ \
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usartStopbits1, /* 1 stop bit. */ \
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false, /* Auto CS functionality enable/disable switch. */ \
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false, /* No CS invert. */ \
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}
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#elif defined(_SILICON_LABS_32B_SERIES_0)
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/* Default USART Async struct for Series 0 devices */
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#define USART_INITASYNC_DEFAULT \
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{ \
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usartEnable, /* Enable RX/TX when initialization is complete. */ \
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0, /* Use current configured reference clock for configuring baud rate. */ \
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115200, /* 115200 bits/s. */ \
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usartOVS16, /* 16x oversampling. */ \
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usartDatabits8, /* 8 data bits. */ \
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usartNoParity, /* No parity. */ \
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usartStopbits1, /* 1 stop bit. */ \
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false, /* Do not disable majority vote. */ \
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false, /* Not USART PRS input mode. */ \
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0, /* PRS channel 0. */ \
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false, /* Auto CS functionality enable/disable switch. */ \
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false, /* No CS invert. */ \
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}
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#elif (_SILICON_LABS_32B_SERIES > 0)
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/* Default USART Async struct for Series 1 and Series 2 devices */
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#define USART_INITASYNC_DEFAULT \
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{ \
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usartEnable, /* Enable RX/TX when initialization is complete. */ \
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0, /* Use current configured reference clock for configuring baud rate. */ \
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115200, /* 115200 bits/s. */ \
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usartOVS16, /* 16x oversampling. */ \
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usartDatabits8, /* 8 data bits. */ \
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usartNoParity, /* No parity. */ \
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usartStopbits1, /* 1 stop bit. */ \
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false, /* Do not disable majority vote. */ \
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false, /* Not USART PRS input mode. */ \
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0, /* PRS channel 0. */ \
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false, /* Auto CS functionality enable/disable switch */ \
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false, /* No CS invert. */ \
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0, /* Auto CS Hold cycles. */ \
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0, /* Auto CS Setup cycles. */ \
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usartHwFlowControlNone /* No HW flow control. */ \
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}
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#endif
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/** Default configuration for USART PRS triggering structure. */
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#if defined(USART_TRIGCTRL_AUTOTXTEN)
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#define USART_INITPRSTRIGGER_DEFAULT \
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{ \
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false, /* Do not enable autoTX triggering. */ \
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false, /* Do not enable receive triggering. */ \
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false, /* Do not enable transmit triggering. */ \
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|
0 /* Set default channel to zero. */ \
|
|
}
|
|
#else
|
|
#define USART_INITPRSTRIGGER_DEFAULT \
|
|
{ \
|
|
false, /* Do not enable receive triggering. */ \
|
|
false, /* Do not enable transmit triggering. */ \
|
|
0 /* Set default channel to zero. */ \
|
|
}
|
|
#endif
|
|
|
|
/** Synchronous mode initialization structure. */
|
|
typedef struct {
|
|
/** Specifies whether TX and/or RX shall be enabled when initialization is completed. */
|
|
USART_Enable_TypeDef enable;
|
|
|
|
/**
|
|
* USART/UART reference clock assumed when configuring baud rate setup.
|
|
* Set to 0 to use the currently configured reference clock.
|
|
*/
|
|
uint32_t refFreq;
|
|
|
|
/** Desired baud rate. */
|
|
uint32_t baudrate;
|
|
|
|
/** Number of data bits in frame. */
|
|
USART_Databits_TypeDef databits;
|
|
|
|
/** Select if to operate in master or slave mode. */
|
|
bool master;
|
|
|
|
/** Select if to send most or least significant bit first. */
|
|
bool msbf;
|
|
|
|
/** Clock polarity/phase mode. */
|
|
USART_ClockMode_TypeDef clockMode;
|
|
|
|
#if !defined(_EFM32_GECKO_FAMILY)
|
|
/** Enable USART Rx via PRS. */
|
|
bool prsRxEnable;
|
|
|
|
/** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */
|
|
USART_PRS_Channel_t prsRxCh;
|
|
#endif
|
|
|
|
#if defined(USART_TRIGCTRL_AUTOTXTEN)
|
|
/** Enable AUTOTX mode. Transmits as long as RX is not full.
|
|
* Generates underflows if TX is empty. */
|
|
bool autoTx;
|
|
#endif
|
|
|
|
/** Auto CS enabling */
|
|
bool autoCsEnable;
|
|
|
|
/** Enable CS invert. By default, chip select is active low.
|
|
* Set to true to make chip select active high. */
|
|
bool csInv;
|
|
|
|
#if defined(_USART_TIMING_CSHOLD_MASK)
|
|
/** Auto CS hold time in baud cycles */
|
|
uint8_t autoCsHold;
|
|
|
|
/** Auto CS setup time in baud cycles */
|
|
uint8_t autoCsSetup;
|
|
#endif
|
|
} USART_InitSync_TypeDef;
|
|
|
|
/** Default configuration for USART sync initialization structure. */
|
|
#if defined(_EFM32_GECKO_FAMILY)
|
|
/* Default USART Sync configuration for EFM32G devices. */
|
|
#define USART_INITSYNC_DEFAULT \
|
|
{ \
|
|
usartEnable, /* Enable RX/TX when initialization is complete. */ \
|
|
0, /* Use current configured reference clock for configuring baud rate. */ \
|
|
1000000, /* 1 Mbits/s. */ \
|
|
usartDatabits8, /* 8 data bits. */ \
|
|
true, /* Master mode. */ \
|
|
false, /* Send least significant bit first. */ \
|
|
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
|
|
false, /* No AUTOCS mode. */ \
|
|
false, /* No CS invert. */ \
|
|
}
|
|
#elif defined(_SILICON_LABS_32B_SERIES_0)
|
|
/* Default USART Sync configuration for series 0 devices. */
|
|
#define USART_INITSYNC_DEFAULT \
|
|
{ \
|
|
usartEnable, /* Enable RX/TX when initialization is complete. */ \
|
|
0, /* Use current configured reference clock for configuring baud rate. */ \
|
|
1000000, /* 1 Mbits/s. */ \
|
|
usartDatabits8, /* 8 data bits. */ \
|
|
true, /* Master mode. */ \
|
|
false, /* Send least significant bit first. */ \
|
|
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
|
|
false, /* Not USART PRS input mode. */ \
|
|
0, /* PRS channel 0. */ \
|
|
false, /* No AUTOTX mode. */ \
|
|
false, /* No AUTOCS mode. */ \
|
|
false, /* No CS invert. */ \
|
|
}
|
|
#elif (_SILICON_LABS_32B_SERIES > 0)
|
|
/* Default USART Sync configuration for series 2 devices */
|
|
#define USART_INITSYNC_DEFAULT \
|
|
{ \
|
|
usartEnable, /* Enable RX/TX when initialization is complete. */ \
|
|
0, /* Use current configured reference clock for configuring baud rate. */ \
|
|
1000000, /* 1 Mbits/s. */ \
|
|
usartDatabits8, /* 8 databits. */ \
|
|
true, /* Master mode. */ \
|
|
false, /* Send least significant bit first. */ \
|
|
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
|
|
false, /* Not USART PRS input mode. */ \
|
|
0, /* PRS channel 0. */ \
|
|
false, /* No AUTOTX mode. */ \
|
|
false, /* No AUTOCS mode. */ \
|
|
false, /* No CS invert. */ \
|
|
0, /* Auto CS Hold cycles. */ \
|
|
0 /* Auto CS Setup cycles. */ \
|
|
}
|
|
#endif
|
|
|
|
/** IrDA mode initialization structure. Inherited from asynchronous mode initialization structure. */
|
|
typedef struct {
|
|
/** General Asynchronous initialization structure. */
|
|
USART_InitAsync_TypeDef async;
|
|
|
|
/** Set to invert Rx signal before IrDA demodulator. */
|
|
bool irRxInv;
|
|
|
|
/** Set to enable filter on IrDA demodulator. */
|
|
bool irFilt;
|
|
|
|
/** Configure the pulse width generated by the IrDA modulator as a fraction
|
|
* of the configured USART bit period. */
|
|
USART_IrDAPw_Typedef irPw;
|
|
|
|
#if defined(USART_IRCTRL_IRPRSEN)
|
|
/** Enable the PRS channel selected by irPrsSel as input to IrDA module
|
|
* instead of TX. */
|
|
bool irPrsEn;
|
|
|
|
/** PRS can be used as input to the pulse modulator instead of TX.
|
|
* This value selects the channel to use. */
|
|
USART_PRS_Channel_t irPrsSel;
|
|
#endif
|
|
} USART_InitIrDA_TypeDef;
|
|
|
|
/** Default configuration for IrDA mode initialization structure. */
|
|
#if defined(_EFM32_GECKO_FAMILY)
|
|
/* Default USART IrDA struct for the EFM32G device */
|
|
#define USART_INITIRDA_DEFAULT \
|
|
{ \
|
|
{ \
|
|
usartEnable, /* Enable RX/TX when initialization is complete. */ \
|
|
0, /* Use current configured reference clock for configuring baud rate. */ \
|
|
115200, /* 115200 bits/s. */ \
|
|
usartOVS16, /* 16x oversampling. */ \
|
|
usartDatabits8, /* 8 data bits. */ \
|
|
usartEvenParity, /* Even parity. */ \
|
|
usartStopbits1, /* 1 stop bit. */ \
|
|
false, /* Auto CS functionality enable/disable switch */ \
|
|
false, /* No CS invert. */ \
|
|
}, \
|
|
false, /* Rx invert disabled. */ \
|
|
false, /* Filtering disabled. */ \
|
|
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
|
|
false, /* Routing to PRS is disabled. */ \
|
|
0 /* PRS channel 0. */ \
|
|
}
|
|
#elif defined(_SILICON_LABS_32B_SERIES_0)
|
|
/* Default USART IrDA struct for Series 0 devices */
|
|
#define USART_INITIRDA_DEFAULT \
|
|
{ \
|
|
{ \
|
|
usartEnable, /* Enable RX/TX when initialization is complete. */ \
|
|
0, /* Use current configured reference clock for configuring baud rate. */ \
|
|
115200, /* 115200 bits/s. */ \
|
|
usartOVS16, /* 16x oversampling. */ \
|
|
usartDatabits8, /* 8 data bits. */ \
|
|
usartEvenParity, /* Even parity. */ \
|
|
usartStopbits1, /* 1 stop bit. */ \
|
|
false, /* Do not disable majority vote. */ \
|
|
false, /* Not USART PRS input mode. */ \
|
|
0, /* PRS channel 0. */ \
|
|
false, /* Auto CS functionality enable/disable switch */ \
|
|
false, /* No CS invert. */ \
|
|
}, \
|
|
false, /* Rx invert disabled. */ \
|
|
false, /* Filtering disabled. */ \
|
|
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
|
|
false, /* Routing to PRS is disabled. */ \
|
|
0 /* PRS channel 0. */ \
|
|
}
|
|
#elif (_SILICON_LABS_32B_SERIES > 0)
|
|
/* Default USART IrDA struct for Series 1 and Series 2 devices */
|
|
#if defined(USART_IRCTRL_IRPRSEN)
|
|
#define USART_INITIRDA_DEFAULT \
|
|
{ \
|
|
{ \
|
|
usartEnable, /* Enable RX/TX when initialization is complete. */ \
|
|
0, /* Use current configured reference clock for configuring baud rate. */ \
|
|
115200, /* 115200 bits/s. */ \
|
|
usartOVS16, /* 16x oversampling. */ \
|
|
usartDatabits8, /* 8 data bits. */ \
|
|
usartEvenParity, /* Even parity. */ \
|
|
usartStopbits1, /* 1 stop bit. */ \
|
|
false, /* Do not disable majority vote. */ \
|
|
false, /* Not USART PRS input mode. */ \
|
|
0, /* PRS channel 0. */ \
|
|
false, /* Auto CS functionality enable/disable switch */ \
|
|
false, /* No CS invert. */ \
|
|
0, /* Auto CS Hold cycles */ \
|
|
0, /* Auto CS Setup cycles */ \
|
|
usartHwFlowControlNone /* No HW flow control */ \
|
|
}, \
|
|
false, /* Rx invert disabled. */ \
|
|
false, /* Filtering disabled. */ \
|
|
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
|
|
false, /* Routing to PRS is disabled. */ \
|
|
0 /* PRS channel 0. */ \
|
|
}
|
|
#else
|
|
#define USART_INITIRDA_DEFAULT \
|
|
{ \
|
|
{ \
|
|
usartEnable, /* Enable RX/TX when initialization is complete. */ \
|
|
0, /* Use current configured reference clock for configuring baud rate. */ \
|
|
115200, /* 115200 bits/s. */ \
|
|
usartOVS16, /* 16x oversampling. */ \
|
|
usartDatabits8, /* 8 data bits. */ \
|
|
usartEvenParity, /* Even parity. */ \
|
|
usartStopbits1, /* 1 stop bit. */ \
|
|
false, /* Do not disable majority vote. */ \
|
|
false, /* Not USART PRS input mode. */ \
|
|
0, /* PRS channel 0. */ \
|
|
false, /* Auto CS functionality enable/disable switch */ \
|
|
false, /* No CS invert. */ \
|
|
0, /* Auto CS Hold cycles */ \
|
|
0, /* Auto CS Setup cycles */ \
|
|
usartHwFlowControlNone /* No HW flow control */ \
|
|
}, \
|
|
false, /* Rx invert disabled. */ \
|
|
false, /* Filtering disabled. */ \
|
|
usartIrDAPwTHREE /* Pulse width is set to ONE. */ \
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(_USART_I2SCTRL_MASK)
|
|
/** I2S mode initialization structure. Inherited from synchronous mode initialization structure. */
|
|
typedef struct {
|
|
/** General Synchronous initialization structure. */
|
|
USART_InitSync_TypeDef sync;
|
|
|
|
/** I2S mode. */
|
|
USART_I2sFormat_TypeDef format;
|
|
|
|
/** Delay on I2S data. Set to add a one-cycle delay between a transition
|
|
* on the word-clock and the start of the I2S word.
|
|
* Should be set for standard I2S format. */
|
|
bool delay;
|
|
|
|
/** Separate DMA Request For Left/Right Data. */
|
|
bool dmaSplit;
|
|
|
|
/** Justification of I2S data within the frame. */
|
|
USART_I2sJustify_TypeDef justify;
|
|
|
|
/** Stereo or Mono, set to true for mono. */
|
|
bool mono;
|
|
} USART_InitI2s_TypeDef;
|
|
|
|
/** Default configuration for I2S mode initialization structure. */
|
|
#if defined(_EFM32_GECKO_FAMILY)
|
|
/* Default USART Sync configuration for EFM32G devices. */
|
|
#define USART_INITI2S_DEFAULT \
|
|
{ \
|
|
{ \
|
|
usartEnable, /* Enable RX/TX when initialization is complete. */ \
|
|
0, /* Use current configured reference clock for configuring baud rate. */ \
|
|
1000000, /* 1 Mbits/s. */ \
|
|
usartDatabits16, /* 16 databits. */ \
|
|
true, /* Master mode. */ \
|
|
true, /* Most significant bit first. */ \
|
|
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
|
|
false, /* No AUTOCS mode */ \
|
|
false, /* No CS invert. */ \
|
|
}, \
|
|
usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
|
|
true, /* Delay on I2S data. */ \
|
|
false, /* No DMA split. */ \
|
|
usartI2sJustifyLeft,/* Data is left-justified within the frame */ \
|
|
false /* Stereo mode. */ \
|
|
}
|
|
#elif defined(_SILICON_LABS_32B_SERIES_0)
|
|
/* Default USART Sync configuration for series 0 devices. */
|
|
#define USART_INITI2S_DEFAULT \
|
|
{ \
|
|
{ \
|
|
usartEnable, /* Enable RX/TX when initialization is complete. */ \
|
|
0, /* Use current configured reference clock for configuring baud rate. */ \
|
|
1000000, /* 1 Mbits/s. */ \
|
|
usartDatabits16, /* 16 databits. */ \
|
|
true, /* Master mode. */ \
|
|
true, /* Most significant bit first. */ \
|
|
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
|
|
false, /* Not USART PRS input mode. */ \
|
|
0, /* PRS channel 0. */ \
|
|
false, /* No AUTOTX mode. */ \
|
|
false, /* No AUTOCS mode */ \
|
|
false, /* No CS invert. */ \
|
|
}, \
|
|
usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
|
|
true, /* Delay on I2S data. */ \
|
|
false, /* No DMA split. */ \
|
|
usartI2sJustifyLeft,/* Data is left-justified within the frame */ \
|
|
false /* Stereo mode. */ \
|
|
}
|
|
#elif (_SILICON_LABS_32B_SERIES > 0)
|
|
/* Default USART Sync configuration for series 2 devices */
|
|
#define USART_INITI2S_DEFAULT \
|
|
{ \
|
|
{ \
|
|
usartEnableTx, /* Enable TX when init completed. */ \
|
|
0, /* Use current configured reference clock for configuring baudrate. */ \
|
|
1000000, /* Baudrate 1M bits/s. */ \
|
|
usartDatabits16, /* 16 databits. */ \
|
|
true, /* Operate as I2S master. */ \
|
|
true, /* Most significant bit first. */ \
|
|
usartClockMode0, /* Clock idle low, sample on rising edge. */ \
|
|
false, /* Don't enable USARTRx via PRS. */ \
|
|
usartPrsRxCh0, /* PRS channel selection (dummy). */ \
|
|
false, /* Disable AUTOTX mode. */ \
|
|
false, /* No AUTOCS mode */ \
|
|
false, /* No CS invert. */ \
|
|
0, /* Auto CS Hold cycles */ \
|
|
0 /* Auto CS Setup cycles */ \
|
|
}, \
|
|
usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
|
|
true, /* Delay on I2S data. */ \
|
|
false, /* No DMA split. */ \
|
|
usartI2sJustifyLeft,/* Data is left-justified within the frame */ \
|
|
false /* Stereo mode. */ \
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
/*******************************************************************************
|
|
***************************** PROTOTYPES **********************************
|
|
******************************************************************************/
|
|
|
|
void USART_BaudrateAsyncSet(USART_TypeDef *usart,
|
|
uint32_t refFreq,
|
|
uint32_t baudrate,
|
|
USART_OVS_TypeDef ovs);
|
|
uint32_t USART_BaudrateCalc(uint32_t refFreq,
|
|
uint32_t clkdiv,
|
|
bool syncmode,
|
|
USART_OVS_TypeDef ovs);
|
|
uint32_t USART_BaudrateGet(USART_TypeDef *usart);
|
|
void USART_BaudrateSyncSet(USART_TypeDef *usart,
|
|
uint32_t refFreq,
|
|
uint32_t baudrate);
|
|
void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable);
|
|
|
|
void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init);
|
|
void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init);
|
|
void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init);
|
|
|
|
#if defined(_USART_I2SCTRL_MASK)
|
|
void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init);
|
|
#endif
|
|
void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init);
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Clear one or more pending USART interrupts.
|
|
*
|
|
* @param[in] usart
|
|
* Pointer to the USART/UART peripheral register block.
|
|
*
|
|
* @param[in] flags
|
|
* Pending USART/UART interrupt source(s) to clear. Use one or more valid
|
|
* interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
|
|
******************************************************************************/
|
|
__STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags)
|
|
{
|
|
#if defined (USART_HAS_SET_CLEAR)
|
|
usart->IF_CLR = flags;
|
|
#else
|
|
usart->IFC = flags;
|
|
#endif
|
|
}
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Disable one or more USART interrupts.
|
|
*
|
|
* @param[in] usart
|
|
* Pointer to the USART/UART peripheral register block.
|
|
*
|
|
* @param[in] flags
|
|
* USART/UART interrupt source(s) to disable. Use one or more valid
|
|
* interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
|
|
******************************************************************************/
|
|
__STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags)
|
|
{
|
|
usart->IEN &= ~flags;
|
|
}
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Enable one or more USART interrupts.
|
|
*
|
|
* @note
|
|
* Depending on the use, a pending interrupt may already be set prior to
|
|
* enabling the interrupt. To ignore a pending interrupt, consider using
|
|
* USART_IntClear() prior to enabling the interrupt.
|
|
*
|
|
* @param[in] usart
|
|
* Pointer to the USART/UART peripheral register block.
|
|
*
|
|
* @param[in] flags
|
|
* USART/UART interrupt source(s) to enable. Use one or more valid
|
|
* interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
|
|
******************************************************************************/
|
|
__STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags)
|
|
{
|
|
usart->IEN |= flags;
|
|
}
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Get pending USART interrupt flags.
|
|
*
|
|
* @note
|
|
* The event bits are not cleared by the use of this function.
|
|
*
|
|
* @param[in] usart
|
|
* Pointer to the USART/UART peripheral register block.
|
|
*
|
|
* @return
|
|
* USART/UART interrupt source(s) pending. Returns one or more valid
|
|
* interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
|
|
******************************************************************************/
|
|
__STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart)
|
|
{
|
|
return usart->IF;
|
|
}
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Get enabled and pending USART interrupt flags.
|
|
* Useful for handling more interrupt sources in the same interrupt handler.
|
|
*
|
|
* @param[in] usart
|
|
* Pointer to the USART/UART peripheral register block.
|
|
*
|
|
* @note
|
|
* Interrupt flags are not cleared by the use of this function.
|
|
*
|
|
* @return
|
|
* Pending and enabled USART interrupt sources.
|
|
* The return value is the bitwise AND combination of
|
|
* - the OR combination of enabled interrupt sources in USARTx_IEN_nnn
|
|
* register (USARTx_IEN_nnn) and
|
|
* - the OR combination of valid interrupt flags of the USART module
|
|
* (USARTx_IF_nnn).
|
|
******************************************************************************/
|
|
__STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart)
|
|
{
|
|
uint32_t ien;
|
|
|
|
/* Store USARTx->IEN in temporary variable in order to define explicit order
|
|
* of volatile accesses. */
|
|
ien = usart->IEN;
|
|
|
|
/* Bitwise AND of pending and enabled interrupts. */
|
|
return usart->IF & ien;
|
|
}
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Set one or more pending USART interrupts from SW.
|
|
*
|
|
* @param[in] usart
|
|
* Pointer to the USART/UART peripheral register block.
|
|
*
|
|
* @param[in] flags
|
|
* USART/UART interrupt source(s) to set to pending. Use one or more valid
|
|
* interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
|
|
******************************************************************************/
|
|
__STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags)
|
|
{
|
|
#if defined (USART_HAS_SET_CLEAR)
|
|
usart->IF_SET = flags;
|
|
#else
|
|
usart->IFS = flags;
|
|
#endif
|
|
}
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Get USART STATUS register.
|
|
*
|
|
* @param[in] usart
|
|
* Pointer to the USART/UART peripheral register block.
|
|
*
|
|
* @return
|
|
* STATUS register value.
|
|
*
|
|
******************************************************************************/
|
|
__STATIC_INLINE uint32_t USART_StatusGet(USART_TypeDef *usart)
|
|
{
|
|
return usart->STATUS;
|
|
}
|
|
|
|
void USART_Reset(USART_TypeDef *usart);
|
|
uint8_t USART_Rx(USART_TypeDef *usart);
|
|
uint16_t USART_RxDouble(USART_TypeDef *usart);
|
|
uint32_t USART_RxDoubleExt(USART_TypeDef *usart);
|
|
uint16_t USART_RxExt(USART_TypeDef *usart);
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Receive one 4-8 bit frame, (or part of 10-16 bit frame).
|
|
*
|
|
* @details
|
|
* This function is used to quickly receive one 4-8 bits frame by reading the
|
|
* RXDATA register directly, without checking the STATUS register for the
|
|
* RXDATAV flag. This can be useful from the RXDATAV interrupt handler,
|
|
* i.e., waiting is superfluous, in order to quickly read the received data.
|
|
* Please refer to @ref USART_RxDataXGet() for reception of 9 bit frames.
|
|
*
|
|
* @note
|
|
* Because this function does not check whether the RXDATA register actually
|
|
* holds valid data, it should only be used in situations when it is certain
|
|
* that there is valid data, ensured by some external program routine, e.g.,
|
|
* when handling an RXDATAV interrupt. The @ref USART_Rx() is normally a
|
|
* better choice if the validity of the RXDATA register is not certain.
|
|
*
|
|
* @note
|
|
* Notice that possible parity/stop bits in asynchronous mode are not
|
|
* considered part of specified frame bit length.
|
|
*
|
|
* @param[in] usart
|
|
* Pointer to USART/UART peripheral register block.
|
|
*
|
|
* @return
|
|
* Data received.
|
|
******************************************************************************/
|
|
__STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart)
|
|
{
|
|
return (uint8_t)usart->RXDATA;
|
|
}
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Receive two 4-8 bit frames, or one 10-16 bit frame.
|
|
*
|
|
* @details
|
|
* This function is used to quickly receive one 10-16 bits frame or two 4-8
|
|
* bit frames by reading the RXDOUBLE register directly, without checking
|
|
* the STATUS register for the RXDATAV flag. This can be useful from the
|
|
* RXDATAV interrupt handler, i.e., waiting is superfluous, in order to
|
|
* quickly read the received data.
|
|
* This function is normally used to receive one frame when operating with
|
|
* frame length 10-16 bits. Please refer to @ref USART_RxDoubleXGet()
|
|
* for reception of two 9 bit frames.
|
|
*
|
|
* @note
|
|
* Because this function does not check whether the RXDOUBLE register actually
|
|
* holds valid data, it should only be used in situations when it is certain
|
|
* that there is valid data, ensured by some external program routine, e.g.,
|
|
* when handling an RXDATAV interrupt. The @ref USART_RxDouble() is
|
|
* normally a better choice if the validity of the RXDOUBLE register is not
|
|
* certain.
|
|
*
|
|
* @note
|
|
* Notice that possible parity/stop bits in asynchronous mode are not
|
|
* considered part of specified frame bit length.
|
|
*
|
|
* @param[in] usart
|
|
* Pointer to USART/UART peripheral register block.
|
|
*
|
|
* @return
|
|
* Data received.
|
|
******************************************************************************/
|
|
__STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart)
|
|
{
|
|
return (uint16_t)usart->RXDOUBLE;
|
|
}
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Receive two 4-9 bit frames, or one 10-16 bit frame with extended
|
|
* information.
|
|
*
|
|
* @details
|
|
* This function is used to quickly receive one 10-16 bits frame or two 4-9
|
|
* bit frames by reading the RXDOUBLEX register directly, without checking
|
|
* the STATUS register for the RXDATAV flag. This can be useful from the
|
|
* RXDATAV interrupt handler, i.e., waiting is superfluous, in order to
|
|
* quickly read the received data.
|
|
*
|
|
* @note
|
|
* Because this function does not check whether the RXDOUBLEX register actually
|
|
* holds valid data, it should only be used in situations when it is certain
|
|
* that there is valid data, ensured by some external program routine, e.g.,
|
|
* when handling an RXDATAV interrupt. The @ref USART_RxDoubleExt() is
|
|
* normally a better choice if the validity of the RXDOUBLEX register is not
|
|
* certain.
|
|
*
|
|
* @note
|
|
* Notice that possible parity/stop bits in asynchronous mode are not
|
|
* considered part of specified frame bit length.
|
|
*
|
|
* @param[in] usart
|
|
* Pointer to USART/UART peripheral register block.
|
|
*
|
|
* @return
|
|
* Data received.
|
|
******************************************************************************/
|
|
__STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart)
|
|
{
|
|
return usart->RXDOUBLEX;
|
|
}
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended
|
|
* information.
|
|
*
|
|
* @details
|
|
* This function is used to quickly receive one 4-9 bit frame, (or part of
|
|
* 10-16 bit frame) with extended information by reading the RXDATAX register
|
|
* directly, without checking the STATUS register for the RXDATAV flag. This
|
|
* can be useful from the RXDATAV interrupt handler, i.e., waiting is
|
|
* superfluous, in order to quickly read the received data.
|
|
*
|
|
* @note
|
|
* Because this function does not check whether the RXDATAX register actually
|
|
* holds valid data, it should only be used in situations when it is certain
|
|
* that there is valid data, ensured by some external program routine, e.g.,
|
|
* when handling an RXDATAV interrupt. The @ref USART_RxExt() is normally
|
|
* a better choice if the validity of the RXDATAX register is not certain.
|
|
*
|
|
* @note
|
|
* Notice that possible parity/stop bits in asynchronous mode are not
|
|
* considered part of specified frame bit length.
|
|
*
|
|
* @param[in] usart
|
|
* Pointer to USART/UART peripheral register block.
|
|
*
|
|
* @return
|
|
* Data received.
|
|
******************************************************************************/
|
|
__STATIC_INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart)
|
|
{
|
|
return (uint16_t)usart->RXDATAX;
|
|
}
|
|
|
|
uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data);
|
|
void USART_Tx(USART_TypeDef *usart, uint8_t data);
|
|
void USART_TxDouble(USART_TypeDef *usart, uint16_t data);
|
|
void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data);
|
|
void USART_TxExt(USART_TypeDef *usart, uint16_t data);
|
|
|
|
/** @} (end addtogroup usart) */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */
|
|
#endif /* EM_USART_H */
|