484 lines
16 KiB
C
484 lines
16 KiB
C
/***************************************************************************//**
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* @file
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* @brief Chip Errata Workarounds
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*******************************************************************************
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* # License
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* <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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******************************************************************************/
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#ifndef EM_CHIP_H
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#define EM_CHIP_H
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#include "em_device.h"
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#include "sl_common.h"
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#if defined(_SILICON_LABS_32B_SERIES) && (_SILICON_LABS_32B_SERIES <= 2)
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#include "em_system.h"
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#endif
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#include "em_bus.h"
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#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
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#include "em_gpio.h"
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#endif
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#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_240)
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#include "em_cmu.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************************************************************//**
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* @addtogroup chip CHIP - Chip Errata Workarounds
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* @brief Chip errata workaround APIs
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* @details
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* API to apply chip errata workarounds at initialization and reset.
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* @{
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******************************************************************************/
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/**************************************************************************//**
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* @brief
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* Chip initialization routine for revision errata workarounds.
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*
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* @note
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* This function must be called immediately in main().
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*
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* This initialization function configures the device to a state
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* as similar to later revisions as possible to improve software compatibility
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* with newer parts. See the device-specific errata for details.
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*****************************************************************************/
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__STATIC_INLINE void CHIP_Init(void)
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{
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#if defined(MSC_CACHECMD_INVCACHE)
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MSC->CACHECMD = MSC_CACHECMD_INVCACHE;
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#elif defined(MSC_CMD_INVCACHE)
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MSC->CMD = MSC_CMD_INVCACHE;
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#endif
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#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY)
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uint32_t rev;
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SYSTEM_ChipRevision_TypeDef chipRev;
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volatile uint32_t *reg;
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rev = *(volatile uint32_t *)(0x0FE081FC);
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/* Engineering Sample calibration setup. */
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if ((rev >> 24) == 0) {
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reg = (volatile uint32_t *)0x400CA00C;
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*reg &= ~(0x70UL);
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/* DREG */
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reg = (volatile uint32_t *)0x400C6020;
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*reg &= ~(0xE0000000UL);
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*reg |= ~(7UL << 25);
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}
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if ((rev >> 24) <= 3) {
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/* DREG */
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reg = (volatile uint32_t *)0x400C6020;
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*reg &= ~(0x00001F80UL);
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/* Update CMU reset values. */
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reg = (volatile uint32_t *)0x400C8040;
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*reg = 0;
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reg = (volatile uint32_t *)0x400C8044;
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*reg = 0;
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reg = (volatile uint32_t *)0x400C8058;
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*reg = 0;
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reg = (volatile uint32_t *)0x400C8060;
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*reg = 0;
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reg = (volatile uint32_t *)0x400C8078;
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*reg = 0;
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}
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SYSTEM_ChipRevisionGet(&chipRev);
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if (chipRev.major == 0x01) {
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/* Rev A errata handling for EM2/3. Must enable DMA clock to get EM2/3 */
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/* to work. This will be fixed in later chip revisions and is only needed for rev A. */
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if (chipRev.minor == 00) {
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reg = (volatile uint32_t *)0x400C8040;
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*reg |= 0x2;
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}
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/* Rev A+B errata handling for I2C when using EM2/3. USART0 clock must be enabled */
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/* after waking up from EM2/EM3 to get I2C to work. This will be fixed in */
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/* later chip revisions and is only needed for rev A+B. */
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if (chipRev.minor <= 0x01) {
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reg = (volatile uint32_t *)0x400C8044;
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*reg |= 0x1;
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}
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}
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/* Ensure correct ADC/DAC calibration value. */
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rev = *(volatile uint32_t *)0x0FE081F0;
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if (rev < 0x4C8ABA00) {
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uint32_t cal;
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/* Enable ADC/DAC clocks. */
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reg = (volatile uint32_t *)0x400C8044UL;
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*reg |= (1 << 14 | 1 << 11);
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/* Retrive calibration values. */
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cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL)
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>> 8) << 24;
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cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL)
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>> 0) << 16;
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cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL)
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>> 8) << 8;
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cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL)
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>> 0) << 0;
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/* ADC0->CAL = 1.25 reference. */
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reg = (volatile uint32_t *)0x40002034UL;
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*reg = cal;
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/* DAC0->CAL = 1.25 reference. */
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reg = (volatile uint32_t *)(0x4000402CUL);
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cal = *(volatile uint32_t *)0x0FE081C8UL;
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*reg = cal;
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/* Turn off ADC/DAC clocks. */
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reg = (volatile uint32_t *)0x400C8044UL;
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*reg &= ~(1 << 14 | 1 << 11);
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}
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#endif
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#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY)
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/****************************/
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/* Fix for errata CMU_E113. */
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uint8_t prodRev;
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SYSTEM_ChipRevision_TypeDef chipRev;
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prodRev = SYSTEM_GetProdRev();
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SYSTEM_ChipRevisionGet(&chipRev);
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// All Giant and Leopard parts except Leopard Rev E
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if ((prodRev >= 16) && (chipRev.minor >= 3)
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&& !((chipRev.major == 2) && (chipRev.minor == 4))) {
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/* This fixes an issue with the LFXO on high temperatures. */
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*(volatile uint32_t*)0x400C80C0 =
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(*(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4);
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}
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#endif
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#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY)
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uint8_t prodRev;
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prodRev = SYSTEM_GetProdRev();
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if (prodRev <= 129) {
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/* This fixes a mistaken internal connection between PC0 and PC4. */
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/* This disables an internal pull-down on PC4. */
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*(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0);
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/* This disables an internal LDO test signal driving PC4. */
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*(volatile uint32_t*)(0x400C80E4) &= ~(1 << 24);
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}
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#endif
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#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
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/****************************
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* Fixes for errata GPIO_E201 (slewrate) and
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* HFXO high-temperature oscillator startup robustness fix. */
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uint32_t port;
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uint32_t clkEn;
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uint8_t prodRev;
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const uint32_t setVal = (0x5 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
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| (0x5 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
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const uint32_t resetVal = _GPIO_P_CTRL_RESETVALUE
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& ~(_GPIO_P_CTRL_SLEWRATE_MASK
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| _GPIO_P_CTRL_SLEWRATEALT_MASK);
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prodRev = SYSTEM_GetProdRev();
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SYSTEM_ChipRevision_TypeDef chipRev;
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SYSTEM_ChipRevisionGet(&chipRev);
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/* This errata is fixed in hardware from PRODREV 0x8F. */
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if (prodRev < 0x8F) {
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/* Fixes for errata GPIO_E201 (slewrate). */
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/* Save HFBUSCLK enable state and enable GPIO clock. */
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clkEn = CMU->HFBUSCLKEN0;
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CMU->HFBUSCLKEN0 = clkEn | CMU_HFBUSCLKEN0_GPIO;
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/* Update slewrate. */
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for (port = 0; port <= GPIO_PORT_MAX; port++) {
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GPIO->P[port].CTRL = setVal | resetVal;
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}
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/* Restore HFBUSCLK enable state. */
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CMU->HFBUSCLKEN0 = clkEn;
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}
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/* This errata is fixed in hardware from PRODREV 0x90. */
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if (prodRev < 0x90) {
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/* HFXO high-temperature oscillator startup robustness fix. */
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CMU->HFXOSTARTUPCTRL =
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(CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK)
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| (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT);
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}
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if (chipRev.major == 0x01) {
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/* Fix for errata EMU_E210 - Potential Power-Down When Entering EM2 */
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*(volatile uint32_t *)(EMU_BASE + 0x164) |= 0x4;
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}
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/****************************
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* Fix for errata DCDC_E206.
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* Disable bypass limit enabled temporarily in SystemInit() errata
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* workaround. */
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BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0);
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#endif
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#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
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uint8_t prodRev = SYSTEM_GetProdRev();
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/* EM2 current fixes for early samples. */
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if (prodRev == 0U) {
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*(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL;
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*(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 2);
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*(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0;
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}
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if (prodRev < 2U) {
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*(volatile uint32_t *)(EMU_BASE + 0x164UL) |= (0x1UL << 13);
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}
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/* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of VREF. */
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CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK)
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| CMU_LFRCOCTRL_VREFUPDATE_64CYCLES
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| CMU_LFRCOCTRL_ENVREF;
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#endif
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#if defined(_SILICON_LABS_32B_SERIES_1) \
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&& defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84)
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MSC->CTRL |= 0x1UL << 8;
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#endif
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#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
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SYSTEM_ChipRevision_TypeDef chipRev;
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SYSTEM_ChipRevisionGet(&chipRev);
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if ((chipRev.major > 1) || (chipRev.minor >= 3)) {
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/* PLFRCO trim values */
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*(volatile uint32_t *)(CMU_BASE + 0x28CUL) = 608;
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*(volatile uint32_t *)(CMU_BASE + 0x290UL) = 356250;
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*(volatile uint32_t *)(CMU_BASE + 0x2F0UL) = 0x04000118;
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*(volatile uint32_t *)(CMU_BASE + 0x2F8UL) = 0x08328400;
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}
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#endif
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/* Charge redist setup (fixed value): LCD->DBGCTRL.CHGRDSTSTR = 1 (reset: 0). */
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#if defined(_LCD_DISPCTRL_CHGRDST_MASK)
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#if defined(_SILICON_LABS_32B_SERIES_1)
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CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_LE;
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CMU->LFACLKEN0 |= CMU_LFACLKEN0_LCD;
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*(volatile uint32_t *)(LCD_BASE + 0x034) |= (0x1UL << 12);
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CMU->LFACLKEN0 &= ~CMU_LFACLKEN0_LCD;
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CMU->HFBUSCLKEN0 &= ~CMU_HFBUSCLKEN0_LE;
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#endif
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#endif
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#if defined(_SILICON_LABS_32B_SERIES_1) \
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&& !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \
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&& !defined(ERRATA_FIX_EMU_E220_DECBOD_IGNORE)
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/* First part of the EMU_E220 DECBOD Errata fix. DECBOD Reset can occur
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* during voltage scaling after EM2/3 wakeup. Second part is in em_emu.c */
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*(volatile uint32_t *)(EMU_BASE + 0x1A4) |= 0x1f << 10;
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#endif
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#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
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SYSTEM_ChipRevision_TypeDef chipRev;
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SYSTEM_ChipRevisionGet(&chipRev);
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if (chipRev.major == 0x01 && (HFXO0->STATUS & HFXO_STATUS_ENS) == 0U) {
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/* Change HFXO default peak detector settings. */
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*(volatile uint32_t*)(HFXO0_BASE + 0x34U) =
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(*(volatile uint32_t*)(HFXO0_BASE + 0x34U) & 0xFF8000FFU)
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| 0x00178500U;
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/* Change HFXO low power control settings. */
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*(volatile uint32_t*)(HFXO0_BASE + 0x30U) =
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(*(volatile uint32_t*)(HFXO0_BASE + 0x30U) & 0xFFFF0FFFU)
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| 0x0000C000U;
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/* Change default SQBUF bias current. */
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*(volatile uint32_t*)(HFXO0_BASE + 0x30U) |= 0x700;
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}
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if (chipRev.major == 0x01 && chipRev.minor == 0x0) {
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/* Trigger RAM read for each RAM instance */
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volatile uint32_t *dmem = (volatile uint32_t *) DMEM_RAM0_RAM_MEM_BASE;
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for (uint32_t i = 0U; i < DMEM_NUM_BANK; i++) {
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// Force memory read
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*dmem;
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dmem += (DMEM_BANK0_SIZE / 4U);
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}
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}
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/* Set TRACE clock to intended reset value. */
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CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK)
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| CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23;
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#endif
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#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205)
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#if defined(SL_TRUSTZONE_SECURE)
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#define HFRCO_CLK_CFG_CLR_ADDR (0x40012020UL)
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#else
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#define HFRCO_CLK_CFG_CLR_ADDR (0x50012020UL)
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#endif
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#define HFRCO_CLK_CFG_CLKOUTDIS0 (0x4UL)
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if (SYSTEM_GetProdRev() == 1) {
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bool hfrcoClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFRCO0) == 0;
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CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0;
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/* Enable HFRCO CLKOUT0. */
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*(volatile uint32_t*)(HFRCO_CLK_CFG_CLR_ADDR) = HFRCO_CLK_CFG_CLKOUTDIS0;
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if (hfrcoClkIsOff) {
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CMU->CLKEN0_CLR = CMU_CLKEN0_HFRCO0;
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}
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}
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#endif
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/* PM-3503 */
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#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_210)
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{
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bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0);
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CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG;
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bool dcdcClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) == 0);
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CMU->CLKEN0_SET = CMU_CLKEN0_DCDC;
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bool dcdcIsLock = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK_LOCKED) != 0);
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DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY;
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while (DCDC->SYNCBUSY & DCDC_SYNCBUSY_CTRL) {
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/* Wait for previous synchronization to finish */
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}
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DCDC->CTRL_CLR = DCDC_CTRL_MODE;
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while ((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) {
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/* Wait for BYPASS switch enable. */
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}
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if (dcdcIsLock) {
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DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY;
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}
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if (dcdcClkIsOff) {
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CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC;
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}
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if (syscfgClkIsOff) {
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CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG;
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}
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}
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#endif
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/* PM-5163 */
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#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_215) \
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&& defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \
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&& (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20)
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SYSTEM_ChipRevision_TypeDef chipRev;
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SYSTEM_ChipRevisionGet(&chipRev);
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if (chipRev.major == 0x01 && chipRev.minor == 0x00) {
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bool hfxo0ClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFXO0) == 0;
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CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0;
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*(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) =
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(*(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) & 0xE3FFFFFFUL)
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| 0x0C000000UL;
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if (hfxo0ClkIsOff) {
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CMU->CLKEN0_CLR = CMU_CLKEN0_HFXO0;
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}
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}
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#endif
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#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_240)
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// Enable ICache out of reset.
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CMU->CLKEN1_SET = _CMU_CLKEN1_ICACHE0_MASK;
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ICACHE0->CTRL_CLR = _ICACHE_CTRL_CACHEDIS_MASK;
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CMU->CLKEN1_CLR = _CMU_CLKEN1_ICACHE0_MASK;
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CMU->CLKEN0_SET = _CMU_CLKEN0_HFRCO0_MASK;
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if (((HFRCO0->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT) == _HFRCO_CAL_TUNING_MASK) {
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CMU_HFRCODPLLBandSet(cmuHFRCODPLLFreq_19M0Hz);
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}
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CMU->CLKEN0_CLR = _CMU_CLKEN0_HFRCO0_MASK;
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#endif
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}
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/**************************************************************************//**
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* @brief
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* Chip reset routine with errata workarounds.
|
|
*
|
|
* @note
|
|
* This function should be called to reset the chip. It does not return.
|
|
*
|
|
* This function applies any errata workarounds needed to cleanly reset the
|
|
* device and then performs a system reset. See the device-specific errata for
|
|
* details.
|
|
*****************************************************************************/
|
|
__STATIC_INLINE void CHIP_Reset(void)
|
|
{
|
|
#if defined(_EFR_DEVICE) && defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
|
|
/****************************
|
|
* Workaround for errata DCDC_E206.
|
|
* Disable radio interference minimization features when resetting */
|
|
|
|
// Ensure access to EMU registers
|
|
EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK;
|
|
EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
|
|
|
|
// No need to do anything if the DCDC is not powering DVDD
|
|
if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD) {
|
|
// Make sure radio cannot accidentally re-enable features
|
|
*(volatile uint32_t *)(0x40084040UL) = 0x1UL;
|
|
|
|
// If DCDC is in use, disable features
|
|
uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK;
|
|
if ((dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE)
|
|
|| (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER)) {
|
|
BUS_RegBitWrite((volatile uint32_t *)(0x400E3060UL), 28UL, 0);
|
|
BUS_RegBitWrite((volatile uint32_t *)(0x400E3074UL), 0, 0);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
NVIC_SystemReset();
|
|
}
|
|
|
|
/** @} (end addtogroup chip) */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* EM_CHIP_H */
|