377 lines
13 KiB
C
377 lines
13 KiB
C
/***************************************************************************//**
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* @file
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* @brief Clock Manager - Oscillators configuration file.
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*******************************************************************************
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* # License
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* <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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******************************************************************************/
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#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H
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#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H
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#if defined(SL_COMPONENT_CATALOG_PRESENT)
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#include "sl_component_catalog.h"
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#endif
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// Internal Defines: DO NOT MODIFY
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#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1
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#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0
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#if defined(SL_CATALOG_RAIL_LIB_PRESENT)
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#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE
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#else
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#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE
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#endif
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Oscillators Settings
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// <h> HFXO Settings (if High Frequency crystal is used)
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// <o SL_CLOCK_MANAGER_HFXO_EN> Enable
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// <i> Enable to configure HFXO
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// <i> AUTO enables HFXO if a radio is used
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// <SL_CLOCK_MANAGER_HFXO_EN_AUTO=> AUTO
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// <SL_CLOCK_MANAGER_HFXO_EN_ENABLE=> ENABLE
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// <SL_CLOCK_MANAGER_HFXO_EN_DISABLE=> DISABLE
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// <d> SL_CLOCK_MANAGER_HFXO_EN_AUTO
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#ifndef SL_CLOCK_MANAGER_HFXO_EN
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#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE
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#endif
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// <o SL_CLOCK_MANAGER_HFXO_MODE> Mode
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// <i>
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// <HFXO_CFG_MODE_XTAL=> XTAL
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// <HFXO_CFG_MODE_EXTCLK=> EXTCLK
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// <HFXO_CFG_MODE_EXTCLKPKDET=> EXTCLKPKDET
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// <d> HFXO_CFG_MODE_XTAL
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#ifndef SL_CLOCK_MANAGER_HFXO_MODE
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#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL
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#endif
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// <o SL_CLOCK_MANAGER_HFXO_FREQ> Frequency in Hz <38000000-40000000>
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// <d> 39000000
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#ifndef SL_CLOCK_MANAGER_HFXO_FREQ
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#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000
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#endif
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// <o SL_CLOCK_MANAGER_HFXO_CTUNE> CTUNE <0-255>
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// <d> 140
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#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE
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#define SL_CLOCK_MANAGER_HFXO_CTUNE 140
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#endif
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// <o SL_CLOCK_MANAGER_HFXO_PRECISION> Precision in PPM <0-65535>
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// <d> 50
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#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION
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#define SL_CLOCK_MANAGER_HFXO_PRECISION 50
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#endif
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// <q SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN> CTUNE HXFO manufacturing
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// <i> Enable to use CTUNE HFXO manufacturing value for calibration
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// <d> 1
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#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN
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#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1
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#endif
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// <e SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN> HFXO crystal sharing feature
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// <i> Enable to configure HFXO crystal sharing leader or follower
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#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN
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#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0
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#endif
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// <e SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN> Crystal sharing leader
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// <i> Enable to configure HFXO crystal sharing leader
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#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN
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#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0
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#endif
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// <e SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN> Crystal sharing leader minimum startup delay
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// <i> If enabled, BUFOUT does not start until timeout set in
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// <i> SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires.
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// <i> This prevents waste of power if BUFOUT is ready too early.
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// <d> 1
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#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN
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#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1
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#endif
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// <o SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP> Wait duration of oscillator startup sequence
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// <i>
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US=> T42US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US=> T83US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US=> T108US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US=> T133US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US=> T158US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US=> T183US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US=> T208US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US=> T233US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US=> T258US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US=> T283US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US=> T333US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US=> T375US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US=> T417US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US=> T458US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US=> T500US
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// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US=> T667US
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// <d> HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US
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#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP
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#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US
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#endif
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// </e>
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// </e>
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// <e SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN> Crystal sharing follower
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// <i> Enable to configure HFXO crystal sharing follower
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#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN
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#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0
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#endif
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// </e>
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// <o SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT> GPIO Port
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// <i> Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN
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// <i> is enabled, this port will be used to receive the BUFOUT request. If
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// <i> SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port
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// <i> will be used to request BUFOUT from the crystal sharing leader.
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#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT
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#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0
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#endif
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// <o SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN> GPIO Pin
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// <i> Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN
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// <i> is enabled, this pin will be used to receive the BUFOUT request. If
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// <i> SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin
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// <i> will be used to request BUFOUT from the crystal sharing leader.
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#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN
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#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10
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#endif
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// </e>
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// </h>
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// <e> LFXO Settings (if Low Frequency crystal is used)
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// <i> Enable to configure LFXO
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#ifndef SL_CLOCK_MANAGER_LFXO_EN
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#define SL_CLOCK_MANAGER_LFXO_EN 1
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#endif
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// <o SL_CLOCK_MANAGER_LFXO_MODE> Mode
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// <i>
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// <LFXO_CFG_MODE_XTAL=> XTAL
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// <LFXO_CFG_MODE_BUFEXTCLK=> BUFEXTCLK
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// <LFXO_CFG_MODE_DIGEXTCLK=> DIGEXTCLK
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// <d> LFXO_CFG_MODE_XTAL
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#ifndef SL_CLOCK_MANAGER_LFXO_MODE
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#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL
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#endif
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// <o SL_CLOCK_MANAGER_LFXO_CTUNE> CTUNE <0-127>
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// <d> 63
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#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE
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#define SL_CLOCK_MANAGER_LFXO_CTUNE 63
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#endif
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// <o SL_CLOCK_MANAGER_LFXO_PRECISION> LFXO precision in PPM <0-65535>
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// <d> 50
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#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION
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#define SL_CLOCK_MANAGER_LFXO_PRECISION 50
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#endif
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// <o SL_CLOCK_MANAGER_LFXO_TIMEOUT> Startup Timeout Delay
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// <i>
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// <LFXO_CFG_TIMEOUT_CYCLES2=> CYCLES2
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// <LFXO_CFG_TIMEOUT_CYCLES256=> CYCLES256
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// <LFXO_CFG_TIMEOUT_CYCLES1K=> CYCLES1K
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// <LFXO_CFG_TIMEOUT_CYCLES2K=> CYCLES2K
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// <LFXO_CFG_TIMEOUT_CYCLES4K=> CYCLES4K
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// <LFXO_CFG_TIMEOUT_CYCLES8K=> CYCLES8K
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// <LFXO_CFG_TIMEOUT_CYCLES16K=> CYCLES16K
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// <LFXO_CFG_TIMEOUT_CYCLES32K=> CYCLES32K
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// <d> LFXO_CFG_TIMEOUT_CYCLES4K
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#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT
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#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K
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#endif
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// <q SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN> CTUNE LXFO manufacturing
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// <i> Enable to use CTUNE LFXO manufacturing value for calibration
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// <d> 1
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#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN
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#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1
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#endif
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// </e>
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// <h> HFRCO and DPLL Settings
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// <o SL_CLOCK_MANAGER_HFRCO_BAND> Frequency Band
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// <i> RC Oscillator Frequency Band
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// <cmuHFRCODPLLFreq_1M0Hz=> 1 MHz
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// <cmuHFRCODPLLFreq_2M0Hz=> 2 MHz
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// <cmuHFRCODPLLFreq_4M0Hz=> 4 MHz
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// <cmuHFRCODPLLFreq_7M0Hz=> 7 MHz
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// <cmuHFRCODPLLFreq_13M0Hz=> 13 MHz
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// <cmuHFRCODPLLFreq_16M0Hz=> 16 MHz
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// <cmuHFRCODPLLFreq_19M0Hz=> 19 MHz
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// <cmuHFRCODPLLFreq_26M0Hz=> 26 MHz
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// <cmuHFRCODPLLFreq_32M0Hz=> 32 MHz
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// <cmuHFRCODPLLFreq_38M0Hz=> 38 MHz
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// <cmuHFRCODPLLFreq_48M0Hz=> 48 MHz
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// <cmuHFRCODPLLFreq_56M0Hz=> 56 MHz
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// <cmuHFRCODPLLFreq_64M0Hz=> 64 MHz
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// <cmuHFRCODPLLFreq_80M0Hz=> 80 MHz
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// <d> cmuHFRCODPLLFreq_80M0Hz
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#ifndef SL_CLOCK_MANAGER_HFRCO_BAND
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#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz
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#endif
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// <e> Use DPLL
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// <i> Enable to use the DPLL with HFRCO
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#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN
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#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0
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#endif
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// <o SL_CLOCK_MANAGER_DPLL_FREQ> Target Frequency in Hz <1000000-80000000>
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// <i> DPLL target frequency
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// <d> 78000000
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#ifndef SL_CLOCK_MANAGER_DPLL_FREQ
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#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000
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#endif
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// <o SL_CLOCK_MANAGER_DPLL_N> Numerator (N) <300-4095>
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// <i> Value of N for output frequency calculation fout = fref * (N+1) / (M+1)
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// <d> 3839
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#ifndef SL_CLOCK_MANAGER_DPLL_N
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#define SL_CLOCK_MANAGER_DPLL_N 3839
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#endif
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// <o SL_CLOCK_MANAGER_DPLL_M> Denominator (M) <0-4095>
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// <i> Value of M for output frequency calculation fout = fref * (N+1) / (M+1)
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// <d> 1919
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#ifndef SL_CLOCK_MANAGER_DPLL_M
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#define SL_CLOCK_MANAGER_DPLL_M 1919
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#endif
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// <o SL_CLOCK_MANAGER_DPLL_REFCLK> Reference Clock
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// <i> Reference clock source for DPLL
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// <CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED=> DISABLED
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// <CMU_DPLLREFCLKCTRL_CLKSEL_HFXO=> HFXO
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// <CMU_DPLLREFCLKCTRL_CLKSEL_LFXO=> LFXO
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// <CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0=> CLKIN0
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// <d> CMU_DPLLREFCLKCTRL_CLKSEL_HFXO
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#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK
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#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO
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#endif
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// <o SL_CLOCK_MANAGER_DPLL_EDGE> Reference Clock Edge Detect
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// <i> Edge detection for reference clock
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// <cmuDPLLEdgeSel_Fall=> Falling Edge
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// <cmuDPLLEdgeSel_Rise=> Rising Edge
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// <d> cmuDPLLEdgeSel_Fall
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#ifndef SL_CLOCK_MANAGER_DPLL_EDGE
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#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall
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#endif
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// <o SL_CLOCK_MANAGER_DPLL_LOCKMODE> DPLL Lock Mode
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// <i> Lock mode
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// <cmuDPLLLockMode_Freq=> Frequency-Lock Loop
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// <cmuDPLLLockMode_Phase=> Phase-Lock Loop
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// <d> cmuDPLLLockMode_Freq
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#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE
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#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase
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#endif
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// <q SL_CLOCK_MANAGER_DPLL_AUTORECOVER> Automatic Lock Recovery
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// <d> 1
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#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER
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#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1
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#endif
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// <q SL_CLOCK_MANAGER_DPLL_DITHER> Enable Dither
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// <d> 0
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#ifndef SL_CLOCK_MANAGER_DPLL_DITHER
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#define SL_CLOCK_MANAGER_DPLL_DITHER 0
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#endif
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// </e>
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// </h>
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// <h> HFRCOEM23 Settings
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// <o SL_CLOCK_MANAGER_HFRCOEM23_BAND> Frequency Band
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// <i> RC Oscillator Frequency Band
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// <cmuHFRCOEM23Freq_1M0Hz=> 1 MHz
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// <cmuHFRCOEM23Freq_2M0Hz=> 2 MHz
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// <cmuHFRCOEM23Freq_4M0Hz=> 4 MHz
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// <cmuHFRCOEM23Freq_13M0Hz=> 13 MHz
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// <cmuHFRCOEM23Freq_16M0Hz=> 16 MHz
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// <cmuHFRCOEM23Freq_19M0Hz=> 19 MHz
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// <cmuHFRCOEM23Freq_26M0Hz=> 26 MHz
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// <cmuHFRCOEM23Freq_32M0Hz=> 32 MHz
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// <cmuHFRCOEM23Freq_40M0Hz=> 40 MHz
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// <d> cmuHFRCOEM23Freq_19M0Hz
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#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND
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#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz
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#endif
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// </h>
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// <h> LFRCO Settings
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// <o SL_CLOCK_MANAGER_LFRCO_PRECISION> Precision Mode
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// <i> Precision mode uses hardware to automatically re-calibrate the LFRCO
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// <i> against a crystal driven by the HFXO. Hardware detects temperature
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// <i> changes and initiates a re-calibration of the LFRCO as needed when
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// <i> operating in EM0, EM1, or EM2. If a re-calibration is necessary and the
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// <i> HFXO is not active, the precision mode hardware will automatically
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// <i> enable HFXO for a short time to perform the calibration. EM4 operation is
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// <i> not allowed while precision mode is enabled.
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// <i> If high precision is selected on devices that do not support it, default
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// <i> precision will be used.
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// <cmuPrecisionDefault=> Default precision
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// <cmuPrecisionHigh=> High precision
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// <d> cmuPrecisionDefault
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#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION
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#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault
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#endif
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// </h>
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// <h> CLKIN0 Settings
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// <o SL_CLOCK_MANAGER_CLKIN0_FREQ> Frequency in Hz <1000000-38000000>
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// <d> 38000000
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#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ
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#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000
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#endif
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// </h>
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// </h>
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// <<< end of configuration section >>>
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// <<< sl:start pin_tool >>>
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// <cmu signal=CLKIN0> SL_CLOCK_MANAGER_CLKIN0
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// $[CMU_SL_CLOCK_MANAGER_CLKIN0]
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// [CMU_SL_CLOCK_MANAGER_CLKIN0]$
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// <<< sl:end pin_tool >>>
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#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */
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