Initial commit of firmware
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Libs/platform/emlib/inc/em_bus.h
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350
Libs/platform/emlib/inc/em_bus.h
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/***************************************************************************//**
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* @file
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* @brief RAM and peripheral bit-field set and clear API
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*******************************************************************************
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* # License
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* <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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******************************************************************************/
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#ifndef EM_BUS_H
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#define EM_BUS_H
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#include "sl_assert.h"
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#include "sl_core.h"
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#include "em_device.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************************************************************//**
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* @addtogroup bus BUS - Bitfield Read/Write
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* @brief BUS register and RAM bit/field read/write API
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* @details
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* API to perform bit-band and field set/clear access to RAM and peripherals.
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @brief
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* Perform a single-bit write operation on a 32-bit word in RAM.
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*
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* @details
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* This function uses Cortex-M bit-banding hardware to perform an atomic
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* read-modify-write operation on a single bit write on a 32-bit word in RAM.
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* See the reference manual for more details about bit-banding.
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*
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* @note
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* This function is atomic on Cortex-M cores with bit-banding support. Bit-
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* banding is a multi cycle read-modify-write bus operation. RAM bit-banding is
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* performed using the memory alias region at BITBAND_RAM_BASE.
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*
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* @param[in] addr An ddress of a 32-bit word in RAM.
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*
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* @param[in] bit A bit position to write, 0-31.
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*
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* @param[in] val A value to set bit to, 0 or 1.
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******************************************************************************/
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__STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr,
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unsigned int bit,
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unsigned int val)
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{
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#if defined(BITBAND_RAM_BASE)
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uint32_t aliasAddr =
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BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4);
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*(volatile uint32_t *)aliasAddr = (uint32_t)val;
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#else
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uint32_t tmp = *addr;
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/* Make sure val is not more than 1 because only one bit needs to be set. */
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*addr = (tmp & ~(1UL << bit)) | ((val & 1UL) << bit);
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform a single-bit read operation on a 32-bit word in RAM.
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*
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* @details
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* This function uses Cortex-M bit-banding hardware to perform an atomic
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* read operation on a single register bit. See the
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* reference manual for more details about bit-banding.
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*
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* @note
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* This function is atomic on Cortex-M cores with bit-banding support.
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* RAM bit-banding is performed using the memory alias region
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* at BITBAND_RAM_BASE.
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*
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* @param[in] addr RAM address.
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*
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* @param[in] bit A bit position to read, 0-31.
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*
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* @return
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* The requested bit shifted to bit position 0 in the return value.
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******************************************************************************/
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__STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr,
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unsigned int bit)
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{
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#if defined(BITBAND_RAM_BASE)
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uint32_t aliasAddr =
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BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4);
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return *(volatile uint32_t *)aliasAddr;
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#else
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return ((*addr) >> bit) & 1UL;
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform a single-bit write operation on a peripheral register.
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*
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* @details
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* This function uses Cortex-M bit-banding hardware to perform an atomic
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* read-modify-write operation on a single register bit. See the
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* reference manual for more details about bit-banding.
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*
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* @note
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* This function is atomic on Cortex-M cores with bit-banding support. Bit-
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* banding is a multi cycle read-modify-write bus operation. Peripheral register
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* bit-banding is performed using the memory alias region at BITBAND_PER_BASE.
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*
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* @param[in] addr A peripheral register address.
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*
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* @param[in] bit A bit position to write, 0-31.
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*
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* @param[in] val A value to set bit to, 0 or 1.
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******************************************************************************/
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__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr,
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unsigned int bit,
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unsigned int val)
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{
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EFM_ASSERT(bit < 32U);
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#if defined(PER_REG_BLOCK_SET_OFFSET) && defined(PER_REG_BLOCK_CLR_OFFSET)
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uint32_t aliasAddr;
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if (val != 0U) {
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aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET;
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} else {
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aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET;
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}
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*(volatile uint32_t *)aliasAddr = 1UL << bit;
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#elif defined(BITBAND_PER_BASE)
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uint32_t aliasAddr =
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BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4);
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*(volatile uint32_t *)aliasAddr = (uint32_t)val;
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#else
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uint32_t tmp = *addr;
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/* Make sure val is not more than 1 because only one bit needs to be set. */
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*addr = (tmp & ~(1 << bit)) | ((val & 1) << bit);
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform a single-bit read operation on a peripheral register.
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*
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* @details
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* This function uses Cortex-M bit-banding hardware to perform an atomic
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* read operation on a single register bit. See the
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* reference manual for more details about bit-banding.
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*
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* @note
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* This function is atomic on Cortex-M cores with bit-banding support.
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* Peripheral register bit-banding is performed using the memory alias
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* region at BITBAND_PER_BASE.
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*
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* @param[in] addr A peripheral register address.
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*
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* @param[in] bit A bit position to read, 0-31.
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*
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* @return
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* The requested bit shifted to bit position 0 in the return value.
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******************************************************************************/
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__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr,
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unsigned int bit)
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{
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#if defined(BITBAND_PER_BASE)
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uint32_t aliasAddr =
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BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t)32) + (bit * (uint32_t) 4);
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return *(volatile uint32_t *)aliasAddr;
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#else
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return ((*addr) >> bit) & 1UL;
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform a masked set operation on a peripheral register address.
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*
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* @details
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* A peripheral register masked set provides a single-cycle and atomic set
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* operation of a bit-mask in a peripheral register. All 1s in the mask are
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* set to 1 in the register. All 0s in the mask are not changed in the
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* register.
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* RAMs and special peripherals are not supported. See the
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* reference manual for more details about the peripheral register field set.
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*
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* @note
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* This function is single-cycle and atomic on cores with peripheral bit set
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* and clear support. It uses the memory alias region at PER_BITSET_MEM_BASE.
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*
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* @param[in] addr A peripheral register address.
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*
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* @param[in] mask A mask to set.
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******************************************************************************/
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__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr,
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uint32_t mask)
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{
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#if defined(PER_REG_BLOCK_SET_OFFSET)
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uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET;
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*(volatile uint32_t *)aliasAddr = mask;
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#elif defined(PER_BITSET_MEM_BASE)
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uint32_t aliasAddr = PER_BITSET_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE);
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*(volatile uint32_t *)aliasAddr = mask;
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#else
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CORE_DECLARE_IRQ_STATE;
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CORE_ENTER_CRITICAL();
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*addr |= mask;
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CORE_EXIT_CRITICAL();
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform a masked clear operation on the peripheral register address.
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*
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* @details
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* A peripheral register masked clear provides a single-cycle and atomic clear
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* operation of a bit-mask in a peripheral register. All 1s in the mask are
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* set to 0 in the register.
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* All 0s in the mask are not changed in the register.
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* RAMs and special peripherals are not supported. See the
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* reference manual for more details about the peripheral register field clear.
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*
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* @note
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* This function is single-cycle and atomic on cores with peripheral bit set
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* and clear support. It uses the memory alias region at PER_BITCLR_MEM_BASE.
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*
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* @param[in] addr A peripheral register address.
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*
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* @param[in] mask A mask to clear.
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******************************************************************************/
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__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr,
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uint32_t mask)
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{
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#if defined(PER_REG_BLOCK_CLR_OFFSET)
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uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET;
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*(volatile uint32_t *)aliasAddr = mask;
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#elif defined(PER_BITCLR_MEM_BASE)
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uint32_t aliasAddr = PER_BITCLR_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE);
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*(volatile uint32_t *)aliasAddr = mask;
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#else
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CORE_DECLARE_IRQ_STATE;
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CORE_ENTER_CRITICAL();
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*addr &= ~mask;
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CORE_EXIT_CRITICAL();
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform peripheral register masked write.
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*
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* @details
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* This function first reads the peripheral register and updates only bits
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* that are set in the mask with content of val. Typically, the mask is a
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* bit-field in the register and the value val is within the mask.
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*
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* @note
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* The read-modify-write operation is executed in a critical section to
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* guarantee atomicity. Note that atomicity can only be guaranteed if register
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* is modified only by the core, and not by other peripherals (like DMA).
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*
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* @param[in] addr A peripheral register address.
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*
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* @param[in] mask A peripheral register mask.
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*
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* @param[in] val A peripheral register value. The value must be shifted to the
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correct bit position in the register corresponding to the field
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defined by the mask parameter. The register value must be
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contained in the field defined by the mask parameter. The
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register value is masked to prevent involuntary spillage.
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******************************************************************************/
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#if defined(__GNUC__) && __GNUC__ >= 10
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wanalyzer-null-dereference"
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#endif
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__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr,
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uint32_t mask,
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uint32_t val)
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{
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CORE_DECLARE_IRQ_STATE;
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CORE_ENTER_CRITICAL();
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EFM_ASSERT(addr != 0);
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*addr = (*addr & ~mask) | (val & mask);
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CORE_EXIT_CRITICAL();
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}
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#if defined(__GNUC__) && __GNUC__ >= 10
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#pragma GCC diagnostic pop
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#endif
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/***************************************************************************//**
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* @brief
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* Perform a peripheral register masked read.
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*
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* @details
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* Read an unshifted and masked value from a peripheral register.
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*
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* @note
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* This operation is not hardware accelerated.
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*
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* @param[in] addr A peripheral register address.
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*
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* @param[in] mask A peripheral register mask.
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*
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* @return
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* An unshifted and masked register value.
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******************************************************************************/
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__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr,
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uint32_t mask)
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{
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return *addr & mask;
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}
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/** @} (end addtogroup bus) */
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#ifdef __cplusplus
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}
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#endif
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#endif /* EM_BUS_H */
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