Initial commit of firmware
This commit is contained in:
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/**************************************************************************//**
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* @file
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* @brief Device Manager Clock Definition
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******************************************************************************
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* # License
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* <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b>
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******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*****************************************************************************/
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#include "em_device.h"
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#include "sl_device_clock.h"
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/***************************************************************************//**
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* @addtogroup device_clock Device Manager Clock
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* @{
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******************************************************************************/
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#if defined(_CMU_CLKEN1_ACMP0_SHIFT)
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// Define ACMP0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_ACMP0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_ACMP0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_ACMP1_SHIFT)
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// Define ACMP1 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_ACMP1_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_ACMP1_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_AGC_SHIFT)
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// Define AGC peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_AGC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_AGC_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_AMUXCP0_SHIFT)
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// Define AMUXCP0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_AMUXCP0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_AMUXCP0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_BUFC_SHIFT)
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// Define BUFC peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_BUFC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_BUFC_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_BURAM_SHIFT)
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// Define BURAM peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_BURAM_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_BURAM_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_BURTC_SHIFT)
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// Define BURTC peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_BURTC_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_BURTC_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_DCDC_SHIFT)
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// Define DCDC peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_DCDC_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_DCDC_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_DMEM_SHIFT)
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// Define DMEM peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_DMEM_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_DMEM_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_DPLL0_SHIFT)
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// Define DPLL0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_DPLL0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_DPLL0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_ECAIFADC_SHIFT)
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// Define ECAIFADC peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_ECAIFADC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_ECAIFADC_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_EUSART0_SHIFT)
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// Define EUSART0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_EUSART0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_EUSART0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_EUSART1_SHIFT)
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// Define EUSART1 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_EUSART1_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_EUSART1_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_FRC_SHIFT)
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// Define FRC peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_FRC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_FRC_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_FSRCO_SHIFT)
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// Define FSRCO peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_FSRCO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_FSRCO_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_GPCRC_SHIFT)
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// Define GPCRC0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_GPCRC0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_GPCRC_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_GPIO_SHIFT)
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// Define GPIO peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_GPIO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_GPIO_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_HFRCO0_SHIFT)
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// Define HFRCO0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_HFRCO0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_HFRCO0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_HFRCOEM23_SHIFT)
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// Define HFRCOEM23 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_HFRCOEM23_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_HFRCOEM23_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_HFXO0_SHIFT)
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// Define HFXO0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_HFXO0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_HFXO0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_HOSTMAILBOX_SHIFT)
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// Define HOSTMAILBOX peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_HOSTMAILBOX_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_HOSTMAILBOX_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_I2C0_SHIFT)
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// Define I2C0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_I2C0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_I2C0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_I2C1_SHIFT)
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// Define I2C1 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_I2C1_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_I2C1_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_IADC0_SHIFT)
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// Define IADC0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_IADC0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_IADC0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_ICACHE0_SHIFT)
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// Define ICACHE0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_ICACHE0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_ICACHE0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_KEYSCAN_SHIFT)
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// Define KEYSCAN peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_KEYSCAN_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_KEYSCAN_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_LDMA_SHIFT)
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// Define LDMA0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_LDMA0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LDMA_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_LDMAXBAR_SHIFT)
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// Define LDMAXBAR0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_LDMAXBAR0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LDMAXBAR_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_LETIMER0_SHIFT)
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// Define LETIMER0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_LETIMER0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LETIMER0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_LFRCO_SHIFT)
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// Define LFRCO peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_LFRCO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LFRCO_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_LFXO_SHIFT)
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// Define LFXO peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_LFXO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LFXO_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_MODEM_SHIFT)
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// Define MODEM peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_MODEM_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_MODEM_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_MSC_SHIFT)
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// Define MSC peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_MSC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_MSC_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_MVP_SHIFT)
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// Define MVP peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_MVP_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_MVP_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_PCNT0_SHIFT)
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// Define PCNT0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_PCNT0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_PCNT0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_PROTIMER_SHIFT)
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// Define PROTIMER peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_PROTIMER_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_PROTIMER_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_PRS_SHIFT)
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// Define PRS peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_PRS_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_PRS_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_RAC_SHIFT)
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// Define RAC peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_RAC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RAC_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_RADIOAES_SHIFT)
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// Define RADIOAES peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_RADIOAES_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_RADIOAES_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_RFCRC_SHIFT)
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// Define RFCRC peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_RFCRC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RFCRC_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_RFECA0_SHIFT)
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// Define RFECA0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_RFECA0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RFECA0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_RFECA1_SHIFT)
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// Define RFECA1 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_RFECA1_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RFECA1_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_RFMAILBOX_SHIFT)
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// Define RFMAILBOX peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_RFMAILBOX_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RFMAILBOX_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_RFSCRATCHPAD_SHIFT)
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// Define RFSCRATCHPAD peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_RFSCRATCHPAD_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RFSCRATCHPAD_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_SEMAILBOXHOST_SHIFT)
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// Define SEMAILBOX peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_SEMAILBOX_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_SEMAILBOXHOST_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_SMU_SHIFT)
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// Define SMU peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_SMU_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_SMU_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_SYNTH_SHIFT)
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// Define SYNTH peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_SYNTH_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_SYNTH_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_SYSCFG_SHIFT)
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// Define SYSCFG peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_SYSCFG_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_SYSCFG_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_SYSRTC0_SHIFT)
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// Define SYSRTC0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_SYSRTC0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_SYSRTC0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_TIMER0_SHIFT)
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// Define TIMER0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_TIMER0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_TIMER1_SHIFT)
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// Define TIMER1 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_TIMER1_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER1_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_TIMER2_SHIFT)
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// Define TIMER2 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_TIMER2_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER2_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_TIMER3_SHIFT)
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// Define TIMER3 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_TIMER3_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER3_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_TIMER4_SHIFT)
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// Define TIMER4 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_TIMER4_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER4_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_ULFRCO_SHIFT)
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// Define ULFRCO peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_ULFRCO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_ULFRCO_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_USART0_SHIFT)
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// Define USART0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_USART0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_USART0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_VDAC0_SHIFT)
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// Define VDAC0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_VDAC0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_VDAC0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_VDAC1_SHIFT)
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// Define VDAC1 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_VDAC1_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_VDAC1_SHIFT;
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#endif
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#if defined(_CMU_CLKEN0_WDOG0_SHIFT)
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// Define WDOG0 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_WDOG0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_WDOG0_SHIFT;
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#endif
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#if defined(_CMU_CLKEN1_WDOG1_SHIFT)
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// Define WDOG1 peripheral bus clock value.
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const uint32_t SL_BUS_CLOCK_WDOG1_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_WDOG1_SHIFT;
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#endif
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/** @} (end addtogroup device_clock) */
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@@ -0,0 +1,383 @@
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/**************************************************************************//**
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||||
* @file
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||||
* @brief Device Manager Peripheral Definition
|
||||
******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "em_device.h"
|
||||
#include "sl_device_peripheral.h"
|
||||
#include "sl_device_clock.h"
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup device_peripheral Device Abstraction Peripheral
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(ACMP0_BASE)
|
||||
// Define peripheral ACMP0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = ACMP0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_ACMP0 };
|
||||
#endif
|
||||
|
||||
#if defined(ACMP1_BASE)
|
||||
// Define peripheral ACMP1.
|
||||
const sl_peripheral_val_t sl_peripheral_val_acmp1 = { .base = ACMP1_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_ACMP1 };
|
||||
#endif
|
||||
|
||||
#if defined(BURAM_BASE)
|
||||
// Define peripheral BURAM.
|
||||
const sl_peripheral_val_t sl_peripheral_val_buram = { .base = BURAM_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_BURAM };
|
||||
#endif
|
||||
|
||||
#if defined(BURTC_BASE)
|
||||
// Define peripheral BURTC.
|
||||
const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = BURTC_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_EM4GRPACLK,
|
||||
.bus_clock = SL_BUS_CLOCK_BURTC };
|
||||
#endif
|
||||
|
||||
#if defined(CMU_BASE)
|
||||
// Define peripheral CMU.
|
||||
const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = CMU_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
#endif
|
||||
|
||||
#if defined(DCDC_BASE)
|
||||
// Define peripheral DCDC.
|
||||
const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = DCDC_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_DCDC };
|
||||
#endif
|
||||
|
||||
#if defined(DMEM_BASE)
|
||||
// Define peripheral DMEM.
|
||||
const sl_peripheral_val_t sl_peripheral_val_dmem = { .base = DMEM_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_PCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_DMEM };
|
||||
#endif
|
||||
|
||||
#if defined(DPLL0_BASE)
|
||||
// Define peripheral DPLL0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = DPLL0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_DPLLREFCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_DPLL0 };
|
||||
#endif
|
||||
|
||||
#if defined(EMU_BASE)
|
||||
// Define peripheral EMU.
|
||||
const sl_peripheral_val_t sl_peripheral_val_emu = { .base = EMU_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
#endif
|
||||
|
||||
#if defined(EUSART0_BASE)
|
||||
// Define peripheral EUSART0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_eusart0 = { .base = EUSART0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_EUSART0CLK,
|
||||
.bus_clock = SL_BUS_CLOCK_EUSART0 };
|
||||
#endif
|
||||
|
||||
#if defined(EUSART1_BASE)
|
||||
// Define peripheral EUSART1.
|
||||
const sl_peripheral_val_t sl_peripheral_val_eusart1 = { .base = EUSART1_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_EM01GRPCCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_EUSART1 };
|
||||
#endif
|
||||
|
||||
#if defined(FSRCO_BASE)
|
||||
// Define peripheral FSRCO.
|
||||
const sl_peripheral_val_t sl_peripheral_val_fsrco = { .base = FSRCO_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_FSRCO };
|
||||
#endif
|
||||
|
||||
#if defined(GPCRC_BASE)
|
||||
// Define peripheral GPCRC0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_gpcrc0 = { .base = GPCRC_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_PCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_GPCRC0 };
|
||||
#endif
|
||||
|
||||
#if defined(GPIO_BASE)
|
||||
// Define peripheral GPIO.
|
||||
const sl_peripheral_val_t sl_peripheral_val_gpio = { .base = GPIO_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_PCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_GPIO };
|
||||
#endif
|
||||
|
||||
#if defined(HFRCO0_BASE)
|
||||
// Define peripheral HFRCO0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_hfrco0 = { .base = HFRCO0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_HFRCO0 };
|
||||
#endif
|
||||
|
||||
#if defined(HFRCOEM23_BASE)
|
||||
// Define peripheral HFRCOEM23.
|
||||
const sl_peripheral_val_t sl_peripheral_val_hfrcoem23 = { .base = HFRCOEM23_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_HFRCOEM23 };
|
||||
#endif
|
||||
|
||||
#if defined(HFXO0_BASE)
|
||||
// Define peripheral HFXO0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = HFXO0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_HFXO0 };
|
||||
#endif
|
||||
|
||||
#if defined(HOSTMAILBOX_BASE)
|
||||
// Define peripheral HOSTMAILBOX.
|
||||
const sl_peripheral_val_t sl_peripheral_val_hostmailbox = { .base = HOSTMAILBOX_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_PCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_HOSTMAILBOX };
|
||||
#endif
|
||||
|
||||
#if defined(I2C0_BASE)
|
||||
// Define peripheral I2C0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_i2c0 = { .base = I2C0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_LSPCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_I2C0 };
|
||||
#endif
|
||||
|
||||
#if defined(I2C1_BASE)
|
||||
// Define peripheral I2C1.
|
||||
const sl_peripheral_val_t sl_peripheral_val_i2c1 = { .base = I2C1_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_PCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_I2C1 };
|
||||
#endif
|
||||
|
||||
#if defined(IADC0_BASE)
|
||||
// Define peripheral IADC0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_iadc0 = { .base = IADC0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_IADCCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_IADC0 };
|
||||
#endif
|
||||
|
||||
#if defined(ICACHE0_BASE)
|
||||
// Define peripheral ICACHE0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = ICACHE0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_ICACHE0 };
|
||||
#endif
|
||||
|
||||
#if defined(KEYSCAN_BASE)
|
||||
// Define peripheral KEYSCAN.
|
||||
const sl_peripheral_val_t sl_peripheral_val_keyscan = { .base = KEYSCAN_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK,
|
||||
.bus_clock = SL_BUS_CLOCK_KEYSCAN };
|
||||
#endif
|
||||
|
||||
#if defined(LDMA_BASE)
|
||||
// Define peripheral LDMA0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_ldma0 = { .base = LDMA_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_HCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_LDMA0 };
|
||||
#endif
|
||||
|
||||
#if defined(LDMAXBAR_BASE)
|
||||
// Define peripheral LDMAXBAR0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_ldmaxbar0 = { .base = LDMAXBAR_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_PCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_LDMAXBAR0 };
|
||||
#endif
|
||||
|
||||
#if defined(LETIMER0_BASE)
|
||||
// Define peripheral LETIMER0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_letimer0 = { .base = LETIMER0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_EM23GRPACLK,
|
||||
.bus_clock = SL_BUS_CLOCK_LETIMER0 };
|
||||
#endif
|
||||
|
||||
#if defined(LFRCO_BASE)
|
||||
// Define peripheral LFRCO.
|
||||
const sl_peripheral_val_t sl_peripheral_val_lfrco = { .base = LFRCO_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_LFRCO };
|
||||
#endif
|
||||
|
||||
#if defined(LFXO_BASE)
|
||||
// Define peripheral LFXO.
|
||||
const sl_peripheral_val_t sl_peripheral_val_lfxo = { .base = LFXO_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_LFXO };
|
||||
#endif
|
||||
|
||||
#if defined(MSC_BASE)
|
||||
// Define peripheral MSC.
|
||||
const sl_peripheral_val_t sl_peripheral_val_msc = { .base = MSC_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_HCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_MSC };
|
||||
#endif
|
||||
|
||||
#if defined(MVP_BASE)
|
||||
// Define peripheral MVP.
|
||||
const sl_peripheral_val_t sl_peripheral_val_mvp = { .base = MVP_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_HCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_MVP };
|
||||
#endif
|
||||
|
||||
#if defined(PCNT0_BASE)
|
||||
// Define peripheral PCNT0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_pcnt0 = { .base = PCNT0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_PCNT0CLK,
|
||||
.bus_clock = SL_BUS_CLOCK_PCNT0 };
|
||||
#endif
|
||||
|
||||
#if defined(PRS_BASE)
|
||||
// Define peripheral PRS.
|
||||
const sl_peripheral_val_t sl_peripheral_val_prs = { .base = PRS_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_PCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_PRS };
|
||||
#endif
|
||||
|
||||
#if defined(RADIOAES_BASE)
|
||||
// Define peripheral RADIOAES.
|
||||
const sl_peripheral_val_t sl_peripheral_val_radioaes = { .base = RADIOAES_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_RADIOAES };
|
||||
#endif
|
||||
|
||||
#if defined(SCRATCHPAD_BASE)
|
||||
// Define peripheral SCRATCHPAD.
|
||||
const sl_peripheral_val_t sl_peripheral_val_scratchpad = { .base = SCRATCHPAD_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_PCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
#endif
|
||||
|
||||
#if defined(SEMAILBOX_HOST_BASE)
|
||||
// Define peripheral SEMAILBOX.
|
||||
const sl_peripheral_val_t sl_peripheral_val_semailbox = { .base = SEMAILBOX_HOST_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_HCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_SEMAILBOX };
|
||||
#endif
|
||||
|
||||
#if defined(SMU_BASE)
|
||||
// Define peripheral SMU.
|
||||
const sl_peripheral_val_t sl_peripheral_val_smu = { .base = SMU_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_SMU };
|
||||
#endif
|
||||
|
||||
#if defined(SYSCFG_BASE)
|
||||
// Define peripheral SYSCFG.
|
||||
const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = SYSCFG_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_SYSCFG };
|
||||
#endif
|
||||
|
||||
#if defined(SYSRTC0_BASE)
|
||||
// Define peripheral SYSRTC0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_sysrtc0 = { .base = SYSRTC0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_SYSRTCCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_SYSRTC0 };
|
||||
#endif
|
||||
|
||||
#if defined(TIMER0_BASE)
|
||||
// Define peripheral TIMER0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_timer0 = { .base = TIMER0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK,
|
||||
.bus_clock = SL_BUS_CLOCK_TIMER0 };
|
||||
#endif
|
||||
|
||||
#if defined(TIMER1_BASE)
|
||||
// Define peripheral TIMER1.
|
||||
const sl_peripheral_val_t sl_peripheral_val_timer1 = { .base = TIMER1_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK,
|
||||
.bus_clock = SL_BUS_CLOCK_TIMER1 };
|
||||
#endif
|
||||
|
||||
#if defined(TIMER2_BASE)
|
||||
// Define peripheral TIMER2.
|
||||
const sl_peripheral_val_t sl_peripheral_val_timer2 = { .base = TIMER2_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK,
|
||||
.bus_clock = SL_BUS_CLOCK_TIMER2 };
|
||||
#endif
|
||||
|
||||
#if defined(TIMER3_BASE)
|
||||
// Define peripheral TIMER3.
|
||||
const sl_peripheral_val_t sl_peripheral_val_timer3 = { .base = TIMER3_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK,
|
||||
.bus_clock = SL_BUS_CLOCK_TIMER3 };
|
||||
#endif
|
||||
|
||||
#if defined(TIMER4_BASE)
|
||||
// Define peripheral TIMER4.
|
||||
const sl_peripheral_val_t sl_peripheral_val_timer4 = { .base = TIMER4_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK,
|
||||
.bus_clock = SL_BUS_CLOCK_TIMER4 };
|
||||
#endif
|
||||
|
||||
#if defined(ULFRCO_BASE)
|
||||
// Define peripheral ULFRCO.
|
||||
const sl_peripheral_val_t sl_peripheral_val_ulfrco = { .base = ULFRCO_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_ULFRCO };
|
||||
#endif
|
||||
|
||||
#if defined(USART0_BASE)
|
||||
// Define peripheral USART0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_usart0 = { .base = USART0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_PCLK,
|
||||
.bus_clock = SL_BUS_CLOCK_USART0 };
|
||||
#endif
|
||||
|
||||
#if defined(VDAC0_BASE)
|
||||
// Define peripheral VDAC0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_vdac0 = { .base = VDAC0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_VDAC0CLK,
|
||||
.bus_clock = SL_BUS_CLOCK_VDAC0 };
|
||||
#endif
|
||||
|
||||
#if defined(VDAC1_BASE)
|
||||
// Define peripheral VDAC1.
|
||||
const sl_peripheral_val_t sl_peripheral_val_vdac1 = { .base = VDAC1_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_VDAC1CLK,
|
||||
.bus_clock = SL_BUS_CLOCK_VDAC1 };
|
||||
#endif
|
||||
|
||||
#if defined(WDOG0_BASE)
|
||||
// Define peripheral WDOG0.
|
||||
const sl_peripheral_val_t sl_peripheral_val_wdog0 = { .base = WDOG0_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_WDOG0CLK,
|
||||
.bus_clock = SL_BUS_CLOCK_WDOG0 };
|
||||
#endif
|
||||
|
||||
#if defined(WDOG1_BASE)
|
||||
// Define peripheral WDOG1.
|
||||
const sl_peripheral_val_t sl_peripheral_val_wdog1 = { .base = WDOG1_BASE,
|
||||
.clk_branch = SL_CLOCK_BRANCH_WDOG1CLK,
|
||||
.bus_clock = SL_BUS_CLOCK_WDOG1 };
|
||||
#endif
|
||||
|
||||
/** @} (end addtogroup device_peripheral) */
|
||||
806
Libs/platform/service/device_manager/inc/sl_device_clock.h
Normal file
806
Libs/platform/service/device_manager/inc/sl_device_clock.h
Normal file
@@ -0,0 +1,806 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief Device Manager Clocks.
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef SL_DEVICE_CLOCK_H
|
||||
#define SL_DEVICE_CLOCK_H
|
||||
|
||||
#include "sl_enum.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#if defined(DEVICE_CLOCK_INTERNAL_PRESENT)
|
||||
#include "sli_device_clock_internal.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup device_clock Device Manager Clock
|
||||
* @details
|
||||
* ## Overview
|
||||
*
|
||||
* The Device Manager Clock module defines the different oscillators,
|
||||
* clock branches and bus clock values that exist across all Silicon Labs
|
||||
* devices.
|
||||
*
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// ENUMS
|
||||
|
||||
/// Oscillators
|
||||
SL_ENUM(sl_oscillator_t) {
|
||||
SL_OSCILLATOR_FSRCO, ///< FSRCO Oscillator
|
||||
SL_OSCILLATOR_HFRCODPLL, ///< HFRCODPLL Oscillator
|
||||
SL_OSCILLATOR_HFXO, ///< HFXO Oscillator
|
||||
SL_OSCILLATOR_HFRCOEM23, ///< HFRCOEM23 Oscillator
|
||||
SL_OSCILLATOR_RFFPLL, ///< RFFPLL Oscillator
|
||||
SL_OSCILLATOR_USBPLL, ///< USBPLL Oscillator
|
||||
SL_OSCILLATOR_SOCPLL, ///< SOCPLL Oscillator
|
||||
SL_OSCILLATOR_LFXO, ///< LFXO Oscillator
|
||||
SL_OSCILLATOR_LFRCO, ///< LFRCO Oscillator
|
||||
SL_OSCILLATOR_ULFRCO, ///< ULFRCO Oscillator
|
||||
SL_OSCILLATOR_CLKIN0, ///< CLKIN0 Oscillator
|
||||
SL_OSCILLATOR_FLPLL ///< FLPLL Oscillator
|
||||
};
|
||||
|
||||
/// Clock Branches
|
||||
SL_ENUM(sl_clock_branch_t) {
|
||||
SL_CLOCK_BRANCH_SYSCLK, ///< SYSCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_HCLK, ///< HCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_HCLKRADIO, ///< HCLK Radio Clock Branch
|
||||
SL_CLOCK_BRANCH_PCLK, ///< PCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_LSPCLK, ///< LSPCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_TRACECLK, ///< TRACECLK Clock Branch
|
||||
SL_CLOCK_BRANCH_ADCCLK, ///< ADCCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_EXPORTCLK, ///< EXPORTCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_EM01GRPACLK, ///< EM01GRPACLK Clock Branch
|
||||
SL_CLOCK_BRANCH_EM01GRPBCLK, ///< EM01GRPBCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_EM01GRPCCLK, ///< EM01GRPCCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_EM01GRPDCLK, ///< EM01GRPDCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_EM23GRPACLK, ///< EM23GRPACLK Clock Branch
|
||||
SL_CLOCK_BRANCH_EM4GRPACLK, ///< EM4GRPACLK Clock Branch
|
||||
SL_CLOCK_BRANCH_QSPISYSCLK, ///< QSPISYSCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_IADCCLK, ///< IADCCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_WDOG0CLK, ///< WDOG0CLK Clock Branch
|
||||
SL_CLOCK_BRANCH_WDOG1CLK, ///< WDOG1CLK Clock Branch
|
||||
SL_CLOCK_BRANCH_RTCCCLK, ///< RTCCCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_SYSRTCCLK, ///< SYSRTCCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_EUART0CLK, ///< EUART0CLK Clock Branch
|
||||
SL_CLOCK_BRANCH_EUSART0CLK, ///< EUSART0CLK Clock Branch
|
||||
SL_CLOCK_BRANCH_DPLLREFCLK, ///< DPLLREFCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_I2C0CLK, ///< I2C0CLK Clock Branch
|
||||
SL_CLOCK_BRANCH_LCDCLK, ///< LCDCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_PIXELRZCLK, ///< PIXELRZCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_PCNT0CLK, ///< PCNT0CLK Clock Branch
|
||||
SL_CLOCK_BRANCH_PRORTCCLK, ///< PCNT0CLK Clock Branch
|
||||
SL_CLOCK_BRANCH_SYSTICKCLK, ///< SYSTICKCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_LESENSEHFCLK, ///< LESENSEHFCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_VDAC0CLK, ///< VDAC0CLK Clock Branch
|
||||
SL_CLOCK_BRANCH_VDAC1CLK, ///< VDAC1CLK Clock Branch
|
||||
SL_CLOCK_BRANCH_USB0CLK, ///< USB0CLK Clock Branch
|
||||
SL_CLOCK_BRANCH_FLPLLREFCLK, ///< FLPLLREFCLK Clock Branch
|
||||
SL_CLOCK_BRANCH_INVALID ///< INVALID Clock Branch
|
||||
};
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// DEFINES
|
||||
|
||||
/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
|
||||
|
||||
// CLKEN bitfield shift in bus clock value.
|
||||
#define _BUS_CLOCK_CLKEN_BIT_SHIFT 0
|
||||
|
||||
// CLKEN bitfield mask in bus clock value.
|
||||
#define _BUS_CLOCK_CLKEN_BIT_MASK 0x3FUL
|
||||
|
||||
// CLKENx register number shift in bus clock value.
|
||||
#define _BUS_CLOCK_CLKENX_SHIFT 6
|
||||
|
||||
// CLKENx register number mask in bus clock value.
|
||||
#define _BUS_CLOCK_CLKENX_MASK 0x1C0UL
|
||||
|
||||
// CLKEN0 value in bus clock.
|
||||
#define BUS_CLOCK_CLKEN0 0x0UL
|
||||
|
||||
// CLKEN1 value in bus clock.
|
||||
#define BUS_CLOCK_CLKEN1 0x1UL
|
||||
|
||||
// CLKEN2 value in bus clock.
|
||||
#define BUS_CLOCK_CLKEN2 0x2UL
|
||||
|
||||
// CLKENHV value in bus clock.
|
||||
#define BUS_CLOCK_CLKENHV 0x3UL
|
||||
|
||||
/// @endcond
|
||||
|
||||
/***************************************************************************//**
|
||||
* @name Bus Clock Defines
|
||||
* Those defines can be used as constant of type sl_bus_clock_t and thus can
|
||||
* be used as argument for function sl_clock_manager_enable_bus_clock() and
|
||||
* sl_clock_manager_disable_bus_clock() in @ref clock_manager.
|
||||
* The values of those defines are device specific.
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/// Define for INVALID peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_INVALID (0)
|
||||
|
||||
/// Define for ACMP0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_ACMP0 (&SL_BUS_CLOCK_ACMP0_VALUE)
|
||||
|
||||
/// Define for ACMP1 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_ACMP1 (&SL_BUS_CLOCK_ACMP1_VALUE)
|
||||
|
||||
/// Define for ADC0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_ADC0 (&SL_BUS_CLOCK_ADC0_VALUE)
|
||||
|
||||
/// Define for AGC peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_AGC (&SL_BUS_CLOCK_AGC_VALUE)
|
||||
|
||||
/// Define for AMUXCP0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_AMUXCP0 (&SL_BUS_CLOCK_AMUXCP0_VALUE)
|
||||
|
||||
/// Define for BUFC peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_BUFC (&SL_BUS_CLOCK_BUFC_VALUE)
|
||||
|
||||
/// Define for BURAM peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_BURAM (&SL_BUS_CLOCK_BURAM_VALUE)
|
||||
|
||||
/// Define for BURTC peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_BURTC (&SL_BUS_CLOCK_BURTC_VALUE)
|
||||
|
||||
/// Define for CRYPTOACC peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_CRYPTOACC (&SL_BUS_CLOCK_CRYPTOACC_VALUE)
|
||||
|
||||
/// Define for DCDC peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_DCDC (&SL_BUS_CLOCK_DCDC_VALUE)
|
||||
|
||||
/// Define for DEVINFO peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_DEVINFO (&SL_BUS_CLOCK_DEVINFO_VALUE)
|
||||
|
||||
/// Define for DMEM peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_DMEM (&SL_BUS_CLOCK_DMEM_VALUE)
|
||||
|
||||
/// Define for DPLL0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_DPLL0 (&SL_BUS_CLOCK_DPLL0_VALUE)
|
||||
|
||||
/// Define for ECAIFADC peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_ECAIFADC (&SL_BUS_CLOCK_ECAIFADC_VALUE)
|
||||
|
||||
/// Define for ETAMPDET peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_ETAMPDET (&SL_BUS_CLOCK_ETAMPDET_VALUE)
|
||||
|
||||
/// Define for EUART0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_EUART0 (&SL_BUS_CLOCK_EUART0_VALUE)
|
||||
|
||||
/// Define for EUSART0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_EUSART0 (&SL_BUS_CLOCK_EUSART0_VALUE)
|
||||
|
||||
/// Define for EUSART1 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_EUSART1 (&SL_BUS_CLOCK_EUSART1_VALUE)
|
||||
|
||||
/// Define for EUSART2 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_EUSART2 (&SL_BUS_CLOCK_EUSART2_VALUE)
|
||||
|
||||
/// Define for EUSART3 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_EUSART3 (&SL_BUS_CLOCK_EUSART3_VALUE)
|
||||
|
||||
/// Define for EUSART4 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_EUSART4 (&SL_BUS_CLOCK_EUSART4_VALUE)
|
||||
|
||||
/// Define for FRC peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_FRC (&SL_BUS_CLOCK_FRC_VALUE)
|
||||
|
||||
/// Define for FSRCO peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_FSRCO (&SL_BUS_CLOCK_FSRCO_VALUE)
|
||||
|
||||
/// Define for GPCRC0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_GPCRC0 (&SL_BUS_CLOCK_GPCRC0_VALUE)
|
||||
|
||||
/// Define for GPIO peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_GPIO (&SL_BUS_CLOCK_GPIO_VALUE)
|
||||
|
||||
/// Define for HFRCO0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_HFRCO0 (&SL_BUS_CLOCK_HFRCO0_VALUE)
|
||||
|
||||
/// Define for HFRCOEM23 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_HFRCOEM23 (&SL_BUS_CLOCK_HFRCOEM23_VALUE)
|
||||
|
||||
/// Define for HFXO0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_HFXO0 (&SL_BUS_CLOCK_HFXO0_VALUE)
|
||||
|
||||
/// Define for HOSTMAILBOX peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_HOSTMAILBOX (&SL_BUS_CLOCK_HOSTMAILBOX_VALUE)
|
||||
|
||||
/// Define for HOSTPORTAL peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_HOSTPORTAL (&SL_BUS_CLOCK_HOSTPORTAL_VALUE)
|
||||
|
||||
/// Define for I2C0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_I2C0 (&SL_BUS_CLOCK_I2C0_VALUE)
|
||||
|
||||
/// Define for I2C1 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_I2C1 (&SL_BUS_CLOCK_I2C1_VALUE)
|
||||
|
||||
/// Define for I2C2 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_I2C2 (&SL_BUS_CLOCK_I2C2_VALUE)
|
||||
|
||||
/// Define for I2C3 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_I2C3 (&SL_BUS_CLOCK_I2C3_VALUE)
|
||||
|
||||
/// Define for IADC0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_IADC0 (&SL_BUS_CLOCK_IADC0_VALUE)
|
||||
|
||||
/// Define for ICACHE0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_ICACHE0 (&SL_BUS_CLOCK_ICACHE0_VALUE)
|
||||
|
||||
/// Define for IFADCDEBUG peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_IFADCDEBUG (&SL_BUS_CLOCK_IFADCDEBUG_VALUE)
|
||||
|
||||
/// Define for KEYSCAN peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_KEYSCAN (&SL_BUS_CLOCK_KEYSCAN_VALUE)
|
||||
|
||||
/// Define for KSU peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_KSU (&SL_BUS_CLOCK_KSU_VALUE)
|
||||
|
||||
/// Define for L2ICACHE0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_L2ICACHE0 (&SL_BUS_CLOCK_L2ICACHE0_VALUE)
|
||||
|
||||
/// Define for LCD peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_LCD (&SL_BUS_CLOCK_LCD_VALUE)
|
||||
|
||||
/// Define for LDMA0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_LDMA0 (&SL_BUS_CLOCK_LDMA0_VALUE)
|
||||
|
||||
/// Define for LDMAXBAR0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_LDMAXBAR0 (&SL_BUS_CLOCK_LDMAXBAR0_VALUE)
|
||||
|
||||
/// Define for LEDDRV0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_LEDDRV0 (&SL_BUS_CLOCK_LEDDRV0_VALUE)
|
||||
|
||||
/// Define for LESENSE peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_LESENSE (&SL_BUS_CLOCK_LESENSE_VALUE)
|
||||
|
||||
/// Define for LETIMER0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_LETIMER0 (&SL_BUS_CLOCK_LETIMER0_VALUE)
|
||||
|
||||
/// Define for LFRCO peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_LFRCO (&SL_BUS_CLOCK_LFRCO_VALUE)
|
||||
|
||||
/// Define for LFXO peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_LFXO (&SL_BUS_CLOCK_LFXO_VALUE)
|
||||
|
||||
/// Define for LPWAES peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_LPWAES (&SL_BUS_CLOCK_LPWAES_VALUE)
|
||||
|
||||
/// Define for LPW0PORTAL peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_LPW0PORTAL (&SL_BUS_CLOCK_LPW0PORTAL_VALUE)
|
||||
|
||||
/// Define for MODEM peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_MODEM (&SL_BUS_CLOCK_MODEM_VALUE)
|
||||
|
||||
/// Define for MSC peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_MSC (&SL_BUS_CLOCK_MSC_VALUE)
|
||||
|
||||
/// Define for MVP peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_MVP (&SL_BUS_CLOCK_MVP_VALUE)
|
||||
|
||||
/// Define for PCNT0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_PCNT0 (&SL_BUS_CLOCK_PCNT0_VALUE)
|
||||
|
||||
/// Define for PDM peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_PDM (&SL_BUS_CLOCK_PDM_VALUE)
|
||||
|
||||
/// Define for PIXELRZ0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_PIXELRZ0 (&SL_BUS_CLOCK_PIXELRZ0_VALUE)
|
||||
|
||||
/// Define for PIXELRZ1 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_PIXELRZ1 (&SL_BUS_CLOCK_PIXELRZ1_VALUE)
|
||||
|
||||
/// Define for PRORTC peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_PRORTC (&SL_BUS_CLOCK_PRORTC_VALUE)
|
||||
|
||||
/// Define for PROTIMER peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_PROTIMER (&SL_BUS_CLOCK_PROTIMER_VALUE)
|
||||
|
||||
/// Define for PRS peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_PRS (&SL_BUS_CLOCK_PRS_VALUE)
|
||||
|
||||
/// Define for RAC peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RAC (&SL_BUS_CLOCK_RAC_VALUE)
|
||||
|
||||
/// Define for RADIOAES peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RADIOAES (&SL_BUS_CLOCK_RADIOAES_VALUE)
|
||||
|
||||
/// Define for RDMAILBOX0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RDMAILBOX0 (&SL_BUS_CLOCK_RDMAILBOX0_VALUE)
|
||||
|
||||
/// Define for RDMAILBOX1 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RDMAILBOX1 (&SL_BUS_CLOCK_RDMAILBOX1_VALUE)
|
||||
|
||||
/// Define for RDSCRATCHPAD peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RDSCRATCHPAD (&SL_BUS_CLOCK_RDSCRATCHPAD_VALUE)
|
||||
|
||||
/// Define for RFCRC peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RFCRC (&SL_BUS_CLOCK_RFCRC_VALUE)
|
||||
|
||||
/// Define for RFECA0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RFECA0 (&SL_BUS_CLOCK_RFECA0_VALUE)
|
||||
|
||||
/// Define for RFECA1 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RFECA1 (&SL_BUS_CLOCK_RFECA1_VALUE)
|
||||
|
||||
/// Define for RFFPLL0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RFFPLL0 (&SL_BUS_CLOCK_RFFPLL0_VALUE)
|
||||
|
||||
/// Define for RFMAILBOX peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RFMAILBOX (&SL_BUS_CLOCK_RFMAILBOX_VALUE)
|
||||
|
||||
/// Define for RFSCRATCHPAD peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RFSCRATCHPAD (&SL_BUS_CLOCK_RFSCRATCHPAD_VALUE)
|
||||
|
||||
/// Define for RFSENSE peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RFSENSE (&SL_BUS_CLOCK_RFSENSE_VALUE)
|
||||
|
||||
/// Define for RPA peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RPA (&SL_BUS_CLOCK_RPA_VALUE)
|
||||
|
||||
/// Define for RTCC peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_RTCC (&SL_BUS_CLOCK_RTCC_VALUE)
|
||||
|
||||
/// Define for SCRATCHPAD peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_SCRATCHPAD (&SL_BUS_CLOCK_SCRATCHPAD_VALUE)
|
||||
|
||||
/// Define for SEMAILBOX peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_SEMAILBOX (&SL_BUS_CLOCK_SEMAILBOX_VALUE)
|
||||
|
||||
/// Define for SEMAPHORE0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_SEMAPHORE0 (&SL_BUS_CLOCK_SEMAPHORE0_VALUE)
|
||||
|
||||
/// Define for SEMAPHORE1 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_SEMAPHORE1 (&SL_BUS_CLOCK_SEMAPHORE1_VALUE)
|
||||
|
||||
/// Define for SEPORTAL peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_SEPORTAL (&SL_BUS_CLOCK_SEPORTAL_VALUE)
|
||||
|
||||
/// Define for SMU peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_SMU (&SL_BUS_CLOCK_SMU_VALUE)
|
||||
|
||||
/// Define for SOCPLL0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_SOCPLL0 (&SL_BUS_CLOCK_SOCPLL0_VALUE)
|
||||
|
||||
/// Define for SYMCRYPTO peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_SYMCRYPTO (&SL_BUS_CLOCK_SYMCRYPTO_VALUE)
|
||||
|
||||
/// Define for SYNTH peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_SYNTH (&SL_BUS_CLOCK_SYNTH_VALUE)
|
||||
|
||||
/// Define for SYSCFG peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_SYSCFG (&SL_BUS_CLOCK_SYSCFG_VALUE)
|
||||
|
||||
/// Define for SYSRTC0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_SYSRTC0 (&SL_BUS_CLOCK_SYSRTC0_VALUE)
|
||||
|
||||
/// Define for TIMER0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_TIMER0 (&SL_BUS_CLOCK_TIMER0_VALUE)
|
||||
|
||||
/// Define for TIMER1 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_TIMER1 (&SL_BUS_CLOCK_TIMER1_VALUE)
|
||||
|
||||
/// Define for TIMER2 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_TIMER2 (&SL_BUS_CLOCK_TIMER2_VALUE)
|
||||
|
||||
/// Define for TIMER3 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_TIMER3 (&SL_BUS_CLOCK_TIMER3_VALUE)
|
||||
|
||||
/// Define for TIMER4 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_TIMER4 (&SL_BUS_CLOCK_TIMER4_VALUE)
|
||||
|
||||
/// Define for TIMER5 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_TIMER5 (&SL_BUS_CLOCK_TIMER5_VALUE)
|
||||
|
||||
/// Define for TIMER6 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_TIMER6 (&SL_BUS_CLOCK_TIMER6_VALUE)
|
||||
|
||||
/// Define for TIMER7 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_TIMER7 (&SL_BUS_CLOCK_TIMER7_VALUE)
|
||||
|
||||
/// Define for TIMER8 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_TIMER8 (&SL_BUS_CLOCK_TIMER8_VALUE)
|
||||
|
||||
/// Define for TIMER9 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_TIMER9 (&SL_BUS_CLOCK_TIMER9_VALUE)
|
||||
|
||||
/// Define for ULFRCO peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_ULFRCO (&SL_BUS_CLOCK_ULFRCO_VALUE)
|
||||
|
||||
/// Define for USART0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_USART0 (&SL_BUS_CLOCK_USART0_VALUE)
|
||||
|
||||
/// Define for USART1 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_USART1 (&SL_BUS_CLOCK_USART1_VALUE)
|
||||
|
||||
/// Define for USART2 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_USART2 (&SL_BUS_CLOCK_USART2_VALUE)
|
||||
|
||||
/// Define for USB peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_USB (&SL_BUS_CLOCK_USB_VALUE)
|
||||
|
||||
/// Define for VDAC0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_VDAC0 (&SL_BUS_CLOCK_VDAC0_VALUE)
|
||||
|
||||
/// Define for VDAC1 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_VDAC1 (&SL_BUS_CLOCK_VDAC1_VALUE)
|
||||
|
||||
/// Define for WDOG0 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_WDOG0 (&SL_BUS_CLOCK_WDOG0_VALUE)
|
||||
|
||||
/// Define for WDOG1 peripheral bus clock pointer.
|
||||
#define SL_BUS_CLOCK_WDOG1 (&SL_BUS_CLOCK_WDOG1_VALUE)
|
||||
|
||||
/// @} (end bus_clock_defines)
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// TYPEDEFS
|
||||
|
||||
/// The bus clock typedef.
|
||||
typedef const uint32_t* sl_bus_clock_t;
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// EXTERNS
|
||||
|
||||
/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
|
||||
|
||||
// External declaration for invalid peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_INVALID_VALUE;
|
||||
|
||||
// External declaration for ACMP0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_ACMP0_VALUE;
|
||||
|
||||
// External declaration for ACMP1 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_ACMP1_VALUE;
|
||||
|
||||
// External declaration for ADC0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_ADC0_VALUE;
|
||||
|
||||
// External declaration for AGC peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_AGC_VALUE;
|
||||
|
||||
// External declaration for AMUXCP0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_AMUXCP0_VALUE;
|
||||
|
||||
// External declaration for BUFC peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_BUFC_VALUE;
|
||||
|
||||
// External declaration for BURAM peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_BURAM_VALUE;
|
||||
|
||||
// External declaration for BURTC peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_BURTC_VALUE;
|
||||
|
||||
// External declaration for CRYPTOACC peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_CRYPTOACC_VALUE;
|
||||
|
||||
// External declaration for DCDC peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_DCDC_VALUE;
|
||||
|
||||
// External declaration for DEVINFO peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_DEVINFO_VALUE;
|
||||
|
||||
// External declaration for DMEM peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_DMEM_VALUE;
|
||||
|
||||
// External declaration for DPLL0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_DPLL0_VALUE;
|
||||
|
||||
// External declaration for ECAIFADC peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_ECAIFADC_VALUE;
|
||||
|
||||
// External declaration for ETAMPDET peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_ETAMPDET_VALUE;
|
||||
|
||||
// External declaration for EUART0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_EUART0_VALUE;
|
||||
|
||||
// External declaration for EUSART0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_EUSART0_VALUE;
|
||||
|
||||
// External declaration for EUSART1 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_EUSART1_VALUE;
|
||||
|
||||
// External declaration for EUSART2 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_EUSART2_VALUE;
|
||||
|
||||
// External declaration for EUSART3 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_EUSART3_VALUE;
|
||||
|
||||
// External declaration for EUSART4 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_EUSART4_VALUE;
|
||||
|
||||
// External declaration for FRC peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_FRC_VALUE;
|
||||
|
||||
// External declaration for FSRCO peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_FSRCO_VALUE;
|
||||
|
||||
// External declaration for GPCRC0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_GPCRC0_VALUE;
|
||||
|
||||
// External declaration for GPIO peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_GPIO_VALUE;
|
||||
|
||||
// External declaration for HFRCO0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_HFRCO0_VALUE;
|
||||
|
||||
// External declaration for HFRCOEM23 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_HFRCOEM23_VALUE;
|
||||
|
||||
// External declaration for HFXO0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_HFXO0_VALUE;
|
||||
|
||||
// External declaration for HOSTMAILBOX peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_HOSTMAILBOX_VALUE;
|
||||
|
||||
// External declaration for HOSTPORTAL peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_HOSTPORTAL_VALUE;
|
||||
|
||||
// External declaration for I2C0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_I2C0_VALUE;
|
||||
|
||||
// External declaration for I2C1 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_I2C1_VALUE;
|
||||
|
||||
// External declaration for I2C2 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_I2C2_VALUE;
|
||||
|
||||
// External declaration for I2C3 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_I2C3_VALUE;
|
||||
|
||||
// External declaration for IADC0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_IADC0_VALUE;
|
||||
|
||||
// External declaration for ICACHE0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_ICACHE0_VALUE;
|
||||
|
||||
// External declaration for IFADCDEBUG peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_IFADCDEBUG_VALUE;
|
||||
|
||||
// External declaration for KEYSCAN peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_KEYSCAN_VALUE;
|
||||
|
||||
// External declaration for KSU peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_KSU_VALUE;
|
||||
|
||||
// External declaration for L2ICACHE0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_L2ICACHE0_VALUE;
|
||||
|
||||
// External declaration for LCD peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_LCD_VALUE;
|
||||
|
||||
// External declaration for LDMA0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_LDMA0_VALUE;
|
||||
|
||||
// External declaration for LDMAXBAR0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_LDMAXBAR0_VALUE;
|
||||
|
||||
// External declaration for LEDDRV0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_LEDDRV0_VALUE;
|
||||
|
||||
// External declaration for LESENSE peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_LESENSE_VALUE;
|
||||
|
||||
// External declaration for LETIMER0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_LETIMER0_VALUE;
|
||||
|
||||
// External declaration for LFRCO peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_LFRCO_VALUE;
|
||||
|
||||
// External declaration for LFXO peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_LFXO_VALUE;
|
||||
|
||||
// External declaration for LPWAES peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_LPWAES_VALUE;
|
||||
|
||||
// External declaration for LPW0PORTAL peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_LPW0PORTAL_VALUE;
|
||||
|
||||
// External declaration for MODEM peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_MODEM_VALUE;
|
||||
|
||||
// External declaration for MSC peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_MSC_VALUE;
|
||||
|
||||
// External declaration for MVP peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_MVP_VALUE;
|
||||
|
||||
// External declaration for PCNT0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_PCNT0_VALUE;
|
||||
|
||||
// External declaration for PDM peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_PDM_VALUE;
|
||||
|
||||
// External declaration for PIXELRZ0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_PIXELRZ0_VALUE;
|
||||
|
||||
// External declaration for PIXELRZ1 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_PIXELRZ1_VALUE;
|
||||
|
||||
// External declaration for PRORTC peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_PRORTC_VALUE;
|
||||
|
||||
// External declaration for PROTIMER peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_PROTIMER_VALUE;
|
||||
|
||||
// External declaration for PRS peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_PRS_VALUE;
|
||||
|
||||
// External declaration for RAC peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RAC_VALUE;
|
||||
|
||||
// External declaration for RADIOAES peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RADIOAES_VALUE;
|
||||
|
||||
// External declaration for RDMAILBOX0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RDMAILBOX0_VALUE;
|
||||
|
||||
// External declaration for RDMAILBOX1 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RDMAILBOX1_VALUE;
|
||||
|
||||
// External declaration for RDSCRATCHPAD peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RDSCRATCHPAD_VALUE;
|
||||
|
||||
// External declaration for RFCRC peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RFCRC_VALUE;
|
||||
|
||||
// External declaration for RFECA0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RFECA0_VALUE;
|
||||
|
||||
// External declaration for RFECA1 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RFECA1_VALUE;
|
||||
|
||||
// External declaration for RFFPLL0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RFFPLL0_VALUE;
|
||||
|
||||
// External declaration for RFMAILBOX peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RFMAILBOX_VALUE;
|
||||
|
||||
// External declaration for RFSCRATCHPAD peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RFSCRATCHPAD_VALUE;
|
||||
|
||||
// External declaration for RFSENSE peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RFSENSE_VALUE;
|
||||
|
||||
// External declaration for RPA peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RPA_VALUE;
|
||||
|
||||
// External declaration for RTCC peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_RTCC_VALUE;
|
||||
|
||||
// External declaration for SCRATCHPAD peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_SCRATCHPAD_VALUE;
|
||||
|
||||
// External declaration for SEMAILBOX peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_SEMAILBOX_VALUE;
|
||||
|
||||
// External declaration for SEMAPHORE0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_SEMAPHORE0_VALUE;
|
||||
|
||||
// External declaration for SEMAPHORE1 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_SEMAPHORE1_VALUE;
|
||||
|
||||
// External declaration for SEPORTAL peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_SEPORTAL_VALUE;
|
||||
|
||||
// External declaration for SMU peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_SMU_VALUE;
|
||||
|
||||
// External declaration for SOCPLL0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_SOCPLL0_VALUE;
|
||||
|
||||
// External declaration for SYMCRYPTO peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_SYMCRYPTO_VALUE;
|
||||
|
||||
// External declaration for SYNTH peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_SYNTH_VALUE;
|
||||
|
||||
// External declaration for SYSCFG peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_SYSCFG_VALUE;
|
||||
|
||||
// External declaration for SYSRTC0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_SYSRTC0_VALUE;
|
||||
|
||||
// External declaration for TIMER0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_TIMER0_VALUE;
|
||||
|
||||
// External declaration for TIMER1 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_TIMER1_VALUE;
|
||||
|
||||
// External declaration for TIMER2 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_TIMER2_VALUE;
|
||||
|
||||
// External declaration for TIMER3 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_TIMER3_VALUE;
|
||||
|
||||
// External declaration for TIMER4 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_TIMER4_VALUE;
|
||||
|
||||
// External declaration for TIMER5 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_TIMER5_VALUE;
|
||||
|
||||
// External declaration for TIMER6 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_TIMER6_VALUE;
|
||||
|
||||
// External declaration for TIMER7 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_TIMER7_VALUE;
|
||||
|
||||
// External declaration for TIMER8 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_TIMER8_VALUE;
|
||||
|
||||
// External declaration for TIMER9 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_TIMER9_VALUE;
|
||||
|
||||
// External declaration for ULFRCO peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_ULFRCO_VALUE;
|
||||
|
||||
// External declaration for USART0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_USART0_VALUE;
|
||||
|
||||
// External declaration for USART1 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_USART1_VALUE;
|
||||
|
||||
// External declaration for USART2 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_USART2_VALUE;
|
||||
|
||||
// External declaration for USB peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_USB_VALUE;
|
||||
|
||||
// External declaration for VDAC0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_VDAC0_VALUE;
|
||||
|
||||
// External declaration for VDAC1 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_VDAC1_VALUE;
|
||||
|
||||
// External declaration for WDOG0 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_WDOG0_VALUE;
|
||||
|
||||
// External declaration for WDOG1 peripheral bus clock value.
|
||||
extern const uint32_t SL_BUS_CLOCK_WDOG1_VALUE;
|
||||
|
||||
/// @endcond
|
||||
|
||||
/** @} (end addtogroup device_clock) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // SL_DEVICE_CLOCK_H
|
||||
670
Libs/platform/service/device_manager/inc/sl_device_gpio.h
Normal file
670
Libs/platform/service/device_manager/inc/sl_device_gpio.h
Normal file
@@ -0,0 +1,670 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief Device Manager GPIO.
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef SL_DEVICE_GPIO_H
|
||||
#define SL_DEVICE_GPIO_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "sl_enum.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup device_gpio Device Manager GPIO
|
||||
* @details
|
||||
* ## Overview
|
||||
*
|
||||
* The Device Manager GPIO component defines the macros,
|
||||
* structures, and enums that are used common across GPIO driver and
|
||||
* peripheral.
|
||||
*
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// ENUMS
|
||||
|
||||
/// GPIO ports IDs.
|
||||
SL_ENUM(sl_gpio_port_t) {
|
||||
SL_GPIO_PORT_A = 0,
|
||||
SL_GPIO_PORT_B = 1,
|
||||
SL_GPIO_PORT_C = 2,
|
||||
SL_GPIO_PORT_D = 3,
|
||||
SL_GPIO_PORT_E = 4,
|
||||
SL_GPIO_PORT_F = 5,
|
||||
SL_GPIO_PORT_G = 6,
|
||||
SL_GPIO_PORT_H = 7,
|
||||
SL_GPIO_PORT_I = 8,
|
||||
SL_GPIO_PORT_J = 9,
|
||||
SL_GPIO_PORT_K = 10,
|
||||
};
|
||||
|
||||
/// GPIO Pin Modes.
|
||||
SL_ENUM(sl_gpio_mode_t) {
|
||||
/// Input disabled. Pull-up if DOUT is set.
|
||||
SL_GPIO_MODE_DISABLED,
|
||||
|
||||
/// Input enabled. Filter if DOUT is set.
|
||||
SL_GPIO_MODE_INPUT,
|
||||
|
||||
/// Input enabled. DOUT determines pull direction.
|
||||
SL_GPIO_MODE_INPUT_PULL,
|
||||
|
||||
/// Input enabled with filter. DOUT determines pull direction.
|
||||
SL_GPIO_MODE_INPUT_PULL_FILTER,
|
||||
|
||||
/// Push-pull output.
|
||||
SL_GPIO_MODE_PUSH_PULL,
|
||||
|
||||
/// Push-pull using alternate control.
|
||||
SL_GPIO_MODE_PUSH_PULL_ALTERNATE,
|
||||
|
||||
/// Wired-or output.
|
||||
SL_GPIO_MODE_WIRED_OR,
|
||||
|
||||
/// Wired-or output with pull-down.
|
||||
SL_GPIO_MODE_WIRED_OR_PULL_DOWN,
|
||||
|
||||
/// Open-drain output.
|
||||
SL_GPIO_MODE_WIRED_AND,
|
||||
|
||||
/// Open-drain output with filter.
|
||||
SL_GPIO_MODE_WIRED_AND_FILTER,
|
||||
|
||||
/// Open-drain output with pull-up.
|
||||
SL_GPIO_MODE_WIRED_AND_PULLUP,
|
||||
|
||||
/// Open-drain output with filter and pull-up.
|
||||
SL_GPIO_MODE_WIRED_AND_PULLUP_FILTER,
|
||||
|
||||
/// Open-drain output using alternate control.
|
||||
SL_GPIO_MODE_WIRED_AND_ALTERNATE,
|
||||
|
||||
/// Open-drain output using alternate control with filter.
|
||||
SL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER,
|
||||
|
||||
/// Open-drain output using alternate control with pull-up.
|
||||
SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP,
|
||||
|
||||
/// Open-drain output using alternate control with filter and pull-up.
|
||||
SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER,
|
||||
};
|
||||
|
||||
/// GPIO Interrupt Configuration flags.
|
||||
SL_ENUM(sl_gpio_interrupt_flag_t) {
|
||||
/// No edge configured.
|
||||
SL_GPIO_INTERRUPT_NO_EDGE = 0,
|
||||
|
||||
/// Interrupt on rising edge.
|
||||
SL_GPIO_INTERRUPT_RISING_EDGE = (1 << 0),
|
||||
|
||||
/// Interrupt on falling edge.
|
||||
SL_GPIO_INTERRUPT_FALLING_EDGE = (1 << 1),
|
||||
|
||||
/// Interrupt on both rising and falling edge.
|
||||
SL_GPIO_INTERRUPT_RISING_FALLING_EDGE = (1 << 2)
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
******************************** DEFINES **********************************
|
||||
******************************************************************************/
|
||||
|
||||
#define SL_GPIO_INTERRUPT_UNAVAILABLE (-1)
|
||||
|
||||
/// Validation of flag.
|
||||
#define SL_GPIO_FLAG_IS_VALID(flag) ((flag == SL_GPIO_INTERRUPT_NO_EDGE) || (flag == SL_GPIO_INTERRUPT_RISING_EDGE) || (flag == SL_GPIO_INTERRUPT_FALLING_EDGE) || (flag == SL_GPIO_INTERRUPT_RISING_FALLING_EDGE))
|
||||
|
||||
/// Define for available ports and pins
|
||||
#define PA0 (&pa0)
|
||||
#define PA1 (&pa1)
|
||||
#define PA2 (&pa2)
|
||||
#define PA3 (&pa3)
|
||||
#define PA4 (&pa4)
|
||||
#define PA5 (&pa5)
|
||||
#define PA6 (&pa6)
|
||||
#define PA7 (&pa7)
|
||||
#define PA8 (&pa8)
|
||||
#define PA9 (&pa9)
|
||||
#define PA10 (&pa10)
|
||||
#define PA11 (&pa11)
|
||||
#define PA12 (&pa12)
|
||||
#define PA13 (&pa13)
|
||||
#define PA14 (&pa14)
|
||||
#define PA15 (&pa15)
|
||||
#define PA16 (&pa16)
|
||||
#define PA17 (&pa17)
|
||||
#define PA18 (&pa18)
|
||||
#define PA19 (&pa19)
|
||||
#define PA20 (&pa20)
|
||||
#define PA21 (&pa21)
|
||||
#define PA22 (&pa22)
|
||||
#define PA23 (&pa23)
|
||||
#define PA24 (&pa24)
|
||||
#define PA25 (&pa25)
|
||||
#define PA26 (&pa26)
|
||||
#define PA27 (&pa27)
|
||||
#define PA28 (&pa28)
|
||||
#define PA29 (&pa29)
|
||||
#define PA30 (&pa30)
|
||||
#define PA31 (&pa31)
|
||||
|
||||
#define PB0 (&pb0)
|
||||
#define PB1 (&pb1)
|
||||
#define PB2 (&pb2)
|
||||
#define PB3 (&pb3)
|
||||
#define PB4 (&pb4)
|
||||
#define PB5 (&pb5)
|
||||
#define PB6 (&pb6)
|
||||
#define PB7 (&pb7)
|
||||
#define PB8 (&pb8)
|
||||
#define PB9 (&pb9)
|
||||
#define PB10 (&pb10)
|
||||
#define PB11 (&pb11)
|
||||
#define PB12 (&pb12)
|
||||
#define PB13 (&pb13)
|
||||
#define PB14 (&pb14)
|
||||
#define PB15 (&pb15)
|
||||
#define PB16 (&pb16)
|
||||
#define PB17 (&pb17)
|
||||
#define PB18 (&pb18)
|
||||
#define PB19 (&pb19)
|
||||
#define PB20 (&pb20)
|
||||
#define PB21 (&pb21)
|
||||
#define PB22 (&pb22)
|
||||
#define PB23 (&pb23)
|
||||
#define PB24 (&pb24)
|
||||
#define PB25 (&pb25)
|
||||
#define PB26 (&pb26)
|
||||
#define PB27 (&pb27)
|
||||
#define PB28 (&pb28)
|
||||
#define PB29 (&pb29)
|
||||
#define PB30 (&pb30)
|
||||
#define PB31 (&pb31)
|
||||
|
||||
#define PC0 (&pc0)
|
||||
#define PC1 (&pc1)
|
||||
#define PC2 (&pc2)
|
||||
#define PC3 (&pc3)
|
||||
#define PC4 (&pc4)
|
||||
#define PC5 (&pc5)
|
||||
#define PC6 (&pc6)
|
||||
#define PC7 (&pc7)
|
||||
#define PC8 (&pc8)
|
||||
#define PC9 (&pc9)
|
||||
#define PC10 (&pc10)
|
||||
#define PC11 (&pc11)
|
||||
#define PC12 (&pc12)
|
||||
#define PC13 (&pc13)
|
||||
#define PC14 (&pc14)
|
||||
#define PC15 (&pc15)
|
||||
#define PC16 (&pc16)
|
||||
#define PC17 (&pc17)
|
||||
#define PC18 (&pc18)
|
||||
#define PC19 (&pc19)
|
||||
#define PC20 (&pc20)
|
||||
#define PC21 (&pc21)
|
||||
#define PC22 (&pc22)
|
||||
#define PC23 (&pc23)
|
||||
#define PC24 (&pc24)
|
||||
#define PC25 (&pc25)
|
||||
#define PC26 (&pc26)
|
||||
#define PC27 (&pc27)
|
||||
#define PC28 (&pc28)
|
||||
#define PC29 (&pc29)
|
||||
#define PC30 (&pc30)
|
||||
#define PC31 (&pc31)
|
||||
|
||||
#define PD0 (&pd0)
|
||||
#define PD1 (&pd1)
|
||||
#define PD2 (&pd2)
|
||||
#define PD3 (&pd3)
|
||||
#define PD4 (&pd4)
|
||||
#define PD5 (&pd5)
|
||||
#define PD6 (&pd6)
|
||||
#define PD7 (&pd7)
|
||||
#define PD8 (&pd8)
|
||||
#define PD9 (&pd9)
|
||||
#define PD10 (&pd10)
|
||||
#define PD11 (&pd11)
|
||||
#define PD12 (&pd12)
|
||||
#define PD13 (&pd13)
|
||||
#define PD14 (&pd14)
|
||||
#define PD15 (&pd15)
|
||||
#define PD16 (&pd16)
|
||||
#define PD17 (&pd17)
|
||||
#define PD18 (&pd18)
|
||||
#define PD19 (&pd19)
|
||||
#define PD20 (&pd20)
|
||||
#define PD21 (&pd21)
|
||||
#define PD22 (&pd22)
|
||||
#define PD23 (&pd23)
|
||||
#define PD24 (&pd24)
|
||||
#define PD25 (&pd25)
|
||||
#define PD26 (&pd26)
|
||||
#define PD27 (&pd27)
|
||||
#define PD28 (&pd28)
|
||||
#define PD29 (&pd29)
|
||||
#define PD30 (&pd30)
|
||||
#define PD31 (&pd31)
|
||||
|
||||
#define PE0 (&pe0)
|
||||
#define PE1 (&pe1)
|
||||
#define PE2 (&pe2)
|
||||
#define PE3 (&pe3)
|
||||
#define PE4 (&pe4)
|
||||
#define PE5 (&pe5)
|
||||
#define PE6 (&pe6)
|
||||
#define PE7 (&pe7)
|
||||
#define PE8 (&pe8)
|
||||
#define PE9 (&pe9)
|
||||
#define PE10 (&pe10)
|
||||
#define PE11 (&pe11)
|
||||
#define PE12 (&pe12)
|
||||
#define PE13 (&pe13)
|
||||
#define PE14 (&pe14)
|
||||
#define PE15 (&pe15)
|
||||
#define PE16 (&pe16)
|
||||
#define PE17 (&pe17)
|
||||
#define PE18 (&pe18)
|
||||
#define PE19 (&pe19)
|
||||
#define PE20 (&pe20)
|
||||
#define PE21 (&pe21)
|
||||
#define PE22 (&pe22)
|
||||
#define PE23 (&pe23)
|
||||
#define PE24 (&pe24)
|
||||
#define PE25 (&pe25)
|
||||
#define PE26 (&pe26)
|
||||
#define PE27 (&pe27)
|
||||
#define PE28 (&pe28)
|
||||
#define PE29 (&pe29)
|
||||
#define PE30 (&pe30)
|
||||
#define PE31 (&pe31)
|
||||
|
||||
#define PF0 (&pf0)
|
||||
#define PF1 (&pf1)
|
||||
#define PF2 (&pf2)
|
||||
#define PF3 (&pf3)
|
||||
#define PF4 (&pf4)
|
||||
#define PF5 (&pf5)
|
||||
#define PF6 (&pf6)
|
||||
#define PF7 (&pf7)
|
||||
#define PF8 (&pf8)
|
||||
#define PF9 (&pf9)
|
||||
#define PF10 (&pf10)
|
||||
#define PF11 (&pf11)
|
||||
#define PF12 (&pf12)
|
||||
#define PF13 (&pf13)
|
||||
#define PF14 (&pf14)
|
||||
#define PF15 (&pf15)
|
||||
#define PF16 (&pf16)
|
||||
#define PF17 (&pf17)
|
||||
#define PF18 (&pf18)
|
||||
#define PF19 (&pf19)
|
||||
#define PF20 (&pf20)
|
||||
#define PF21 (&pf21)
|
||||
#define PF22 (&pf22)
|
||||
#define PF23 (&pf23)
|
||||
#define PF24 (&pf24)
|
||||
#define PF25 (&pf25)
|
||||
#define PF26 (&pf26)
|
||||
#define PF27 (&pf27)
|
||||
#define PF28 (&pf28)
|
||||
#define PF29 (&pf29)
|
||||
#define PF30 (&pf30)
|
||||
#define PF31 (&pf31)
|
||||
|
||||
#define PG0 (&pg0)
|
||||
#define PG1 (&pg1)
|
||||
#define PG2 (&pg2)
|
||||
#define PG3 (&pg3)
|
||||
#define PG4 (&pg4)
|
||||
#define PG5 (&pg5)
|
||||
#define PG6 (&pg6)
|
||||
#define PG7 (&pg7)
|
||||
#define PG8 (&pg8)
|
||||
#define PG9 (&pg9)
|
||||
#define PG10 (&pg10)
|
||||
#define PG11 (&pg11)
|
||||
#define PG12 (&pg12)
|
||||
#define PG13 (&pg13)
|
||||
#define PG14 (&pg14)
|
||||
#define PG15 (&pg15)
|
||||
#define PG16 (&pg16)
|
||||
#define PG17 (&pg17)
|
||||
#define PG18 (&pg18)
|
||||
#define PG19 (&pg19)
|
||||
#define PG20 (&pg20)
|
||||
#define PG21 (&pg21)
|
||||
#define PG22 (&pg22)
|
||||
#define PG23 (&pg23)
|
||||
#define PG24 (&pg24)
|
||||
#define PG25 (&pg25)
|
||||
#define PG26 (&pg26)
|
||||
#define PG27 (&pg27)
|
||||
#define PG28 (&pg28)
|
||||
#define PG29 (&pg29)
|
||||
#define PG30 (&pg30)
|
||||
#define PG31 (&pg31)
|
||||
|
||||
#define PH0 (&ph0)
|
||||
#define PH1 (&ph1)
|
||||
#define PH2 (&ph2)
|
||||
#define PH3 (&ph3)
|
||||
#define PH4 (&ph4)
|
||||
#define PH5 (&ph5)
|
||||
#define PH6 (&ph6)
|
||||
#define PH7 (&ph7)
|
||||
#define PH8 (&ph8)
|
||||
#define PH9 (&ph9)
|
||||
#define PH10 (&ph10)
|
||||
#define PH11 (&ph11)
|
||||
#define PH12 (&ph12)
|
||||
#define PH13 (&ph13)
|
||||
#define PH14 (&ph14)
|
||||
#define PH15 (&ph15)
|
||||
#define PH16 (&ph16)
|
||||
#define PH17 (&ph17)
|
||||
#define PH18 (&ph18)
|
||||
#define PH19 (&ph19)
|
||||
#define PH20 (&ph20)
|
||||
#define PH21 (&ph21)
|
||||
#define PH22 (&ph22)
|
||||
#define PH23 (&ph23)
|
||||
#define PH24 (&ph24)
|
||||
#define PH25 (&ph25)
|
||||
#define PH26 (&ph26)
|
||||
#define PH27 (&ph27)
|
||||
#define PH28 (&ph28)
|
||||
#define PH29 (&ph29)
|
||||
#define PH30 (&ph30)
|
||||
#define PH31 (&ph31)
|
||||
|
||||
#define PI0 (&pi0)
|
||||
#define PI1 (&pi1)
|
||||
#define PI2 (&pi2)
|
||||
#define PI3 (&pi3)
|
||||
#define PI4 (&pi4)
|
||||
#define PI5 (&pi5)
|
||||
#define PI6 (&pi6)
|
||||
#define PI7 (&pi7)
|
||||
#define PI8 (&pi8)
|
||||
#define PI9 (&pi9)
|
||||
#define PI10 (&pi10)
|
||||
#define PI11 (&pi11)
|
||||
#define PI12 (&pi12)
|
||||
#define PI13 (&pi13)
|
||||
#define PI14 (&pi14)
|
||||
#define PI15 (&pi15)
|
||||
#define PI16 (&pi16)
|
||||
#define PI17 (&pi17)
|
||||
#define PI18 (&pi18)
|
||||
#define PI19 (&pi19)
|
||||
#define PI20 (&pi20)
|
||||
#define PI21 (&pi21)
|
||||
#define PI22 (&pi22)
|
||||
#define PI23 (&pi23)
|
||||
#define PI24 (&pi24)
|
||||
#define PI25 (&pi25)
|
||||
#define PI26 (&pi26)
|
||||
#define PI27 (&pi27)
|
||||
#define PI28 (&pi28)
|
||||
#define PI29 (&pi29)
|
||||
#define PI30 (&pi30)
|
||||
#define PI31 (&pi31)
|
||||
|
||||
#define PJ0 (&pj0)
|
||||
#define PJ1 (&pj1)
|
||||
#define PJ2 (&pj2)
|
||||
#define PJ3 (&pj3)
|
||||
#define PJ4 (&pj4)
|
||||
#define PJ5 (&pj5)
|
||||
#define PJ6 (&pj6)
|
||||
#define PJ7 (&pj7)
|
||||
#define PJ8 (&pj8)
|
||||
#define PJ9 (&pj9)
|
||||
#define PJ10 (&pj10)
|
||||
#define PJ11 (&pj11)
|
||||
#define PJ12 (&pj12)
|
||||
#define PJ13 (&pj13)
|
||||
#define PJ14 (&pj14)
|
||||
#define PJ15 (&pj15)
|
||||
#define PJ16 (&pj16)
|
||||
#define PJ17 (&pj17)
|
||||
#define PJ18 (&pj18)
|
||||
#define PJ19 (&pj19)
|
||||
#define PJ20 (&pj20)
|
||||
#define PJ21 (&pj21)
|
||||
#define PJ22 (&pj22)
|
||||
#define PJ23 (&pj23)
|
||||
#define PJ24 (&pj24)
|
||||
#define PJ25 (&pj25)
|
||||
#define PJ26 (&pj26)
|
||||
#define PJ27 (&pj27)
|
||||
#define PJ28 (&pj28)
|
||||
#define PJ29 (&pj29)
|
||||
#define PJ30 (&pj30)
|
||||
#define PJ31 (&pj31)
|
||||
|
||||
#define PK0 (&pk0)
|
||||
#define PK1 (&pk1)
|
||||
#define PK2 (&pk2)
|
||||
#define PK3 (&pk3)
|
||||
#define PK4 (&pk4)
|
||||
#define PK5 (&pk5)
|
||||
#define PK6 (&pk6)
|
||||
#define PK7 (&pk7)
|
||||
#define PK8 (&pk8)
|
||||
#define PK9 (&pk9)
|
||||
#define PK10 (&pk10)
|
||||
#define PK11 (&pk11)
|
||||
#define PK12 (&pk12)
|
||||
#define PK13 (&pk13)
|
||||
#define PK14 (&pk14)
|
||||
#define PK15 (&pk15)
|
||||
#define PK16 (&pk16)
|
||||
#define PK17 (&pk17)
|
||||
#define PK18 (&pk18)
|
||||
#define PK19 (&pk19)
|
||||
#define PK20 (&pk20)
|
||||
#define PK21 (&pk21)
|
||||
#define PK22 (&pk22)
|
||||
#define PK23 (&pk23)
|
||||
#define PK24 (&pk24)
|
||||
#define PK25 (&pk25)
|
||||
#define PK26 (&pk26)
|
||||
#define PK27 (&pk27)
|
||||
#define PK28 (&pk28)
|
||||
#define PK29 (&pk29)
|
||||
#define PK30 (&pk30)
|
||||
#define PK31 (&pk31)
|
||||
|
||||
/*******************************************************************************
|
||||
******************************* STRUCTS ***********************************
|
||||
******************************************************************************/
|
||||
|
||||
/// Structure for GPIO Port and Pin.
|
||||
typedef struct {
|
||||
uint8_t port;
|
||||
uint8_t pin;
|
||||
} sl_gpio_t;
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// EXTERNS
|
||||
|
||||
/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN
|
||||
|
||||
extern const sl_gpio_t pa0;
|
||||
extern const sl_gpio_t pa1;
|
||||
extern const sl_gpio_t pa2;
|
||||
extern const sl_gpio_t pa3;
|
||||
extern const sl_gpio_t pa4;
|
||||
extern const sl_gpio_t pa5;
|
||||
extern const sl_gpio_t pa6;
|
||||
extern const sl_gpio_t pa7;
|
||||
extern const sl_gpio_t pa8;
|
||||
extern const sl_gpio_t pa9;
|
||||
extern const sl_gpio_t pa10;
|
||||
extern const sl_gpio_t pa11;
|
||||
extern const sl_gpio_t pa12;
|
||||
extern const sl_gpio_t pa13;
|
||||
extern const sl_gpio_t pa14;
|
||||
extern const sl_gpio_t pa15;
|
||||
extern const sl_gpio_t pa16;
|
||||
extern const sl_gpio_t pa17;
|
||||
extern const sl_gpio_t pa18;
|
||||
extern const sl_gpio_t pa19;
|
||||
extern const sl_gpio_t pa20;
|
||||
extern const sl_gpio_t pa21;
|
||||
extern const sl_gpio_t pa22;
|
||||
extern const sl_gpio_t pa23;
|
||||
extern const sl_gpio_t pa24;
|
||||
extern const sl_gpio_t pa25;
|
||||
extern const sl_gpio_t pa26;
|
||||
extern const sl_gpio_t pa27;
|
||||
extern const sl_gpio_t pa28;
|
||||
extern const sl_gpio_t pa29;
|
||||
extern const sl_gpio_t pa30;
|
||||
extern const sl_gpio_t pa31;
|
||||
extern const sl_gpio_t pa32;
|
||||
|
||||
extern const sl_gpio_t pb0;
|
||||
extern const sl_gpio_t pb1;
|
||||
extern const sl_gpio_t pb2;
|
||||
extern const sl_gpio_t pb3;
|
||||
extern const sl_gpio_t pb4;
|
||||
extern const sl_gpio_t pb5;
|
||||
extern const sl_gpio_t pb6;
|
||||
extern const sl_gpio_t pb7;
|
||||
extern const sl_gpio_t pb8;
|
||||
extern const sl_gpio_t pb9;
|
||||
extern const sl_gpio_t pb10;
|
||||
extern const sl_gpio_t pb11;
|
||||
extern const sl_gpio_t pb12;
|
||||
extern const sl_gpio_t pb13;
|
||||
extern const sl_gpio_t pb14;
|
||||
extern const sl_gpio_t pb15;
|
||||
extern const sl_gpio_t pb16;
|
||||
extern const sl_gpio_t pb17;
|
||||
extern const sl_gpio_t pb18;
|
||||
extern const sl_gpio_t pb19;
|
||||
extern const sl_gpio_t pb20;
|
||||
extern const sl_gpio_t pb21;
|
||||
extern const sl_gpio_t pb22;
|
||||
extern const sl_gpio_t pb23;
|
||||
extern const sl_gpio_t pb24;
|
||||
extern const sl_gpio_t pb25;
|
||||
extern const sl_gpio_t pb26;
|
||||
extern const sl_gpio_t pb27;
|
||||
extern const sl_gpio_t pb28;
|
||||
extern const sl_gpio_t pb29;
|
||||
extern const sl_gpio_t pb30;
|
||||
extern const sl_gpio_t pb31;
|
||||
extern const sl_gpio_t pb32;
|
||||
|
||||
extern const sl_gpio_t pc0;
|
||||
extern const sl_gpio_t pc1;
|
||||
extern const sl_gpio_t pc2;
|
||||
extern const sl_gpio_t pc3;
|
||||
extern const sl_gpio_t pc4;
|
||||
extern const sl_gpio_t pc5;
|
||||
extern const sl_gpio_t pc6;
|
||||
extern const sl_gpio_t pc7;
|
||||
extern const sl_gpio_t pc8;
|
||||
extern const sl_gpio_t pc9;
|
||||
extern const sl_gpio_t pc10;
|
||||
extern const sl_gpio_t pc11;
|
||||
extern const sl_gpio_t pc12;
|
||||
extern const sl_gpio_t pc13;
|
||||
extern const sl_gpio_t pc14;
|
||||
extern const sl_gpio_t pc15;
|
||||
extern const sl_gpio_t pc16;
|
||||
extern const sl_gpio_t pc17;
|
||||
extern const sl_gpio_t pc18;
|
||||
extern const sl_gpio_t pc19;
|
||||
extern const sl_gpio_t pc20;
|
||||
extern const sl_gpio_t pc21;
|
||||
extern const sl_gpio_t pc22;
|
||||
extern const sl_gpio_t pc23;
|
||||
extern const sl_gpio_t pc24;
|
||||
extern const sl_gpio_t pc25;
|
||||
extern const sl_gpio_t pc26;
|
||||
extern const sl_gpio_t pc27;
|
||||
extern const sl_gpio_t pc28;
|
||||
extern const sl_gpio_t pc29;
|
||||
extern const sl_gpio_t pc30;
|
||||
extern const sl_gpio_t pc31;
|
||||
extern const sl_gpio_t pc32;
|
||||
|
||||
extern const sl_gpio_t pd0;
|
||||
extern const sl_gpio_t pd1;
|
||||
extern const sl_gpio_t pd2;
|
||||
extern const sl_gpio_t pd3;
|
||||
extern const sl_gpio_t pd4;
|
||||
extern const sl_gpio_t pd5;
|
||||
extern const sl_gpio_t pd6;
|
||||
extern const sl_gpio_t pd7;
|
||||
extern const sl_gpio_t pd8;
|
||||
extern const sl_gpio_t pd9;
|
||||
extern const sl_gpio_t pd10;
|
||||
extern const sl_gpio_t pd11;
|
||||
extern const sl_gpio_t pd12;
|
||||
extern const sl_gpio_t pd13;
|
||||
extern const sl_gpio_t pd14;
|
||||
extern const sl_gpio_t pd15;
|
||||
extern const sl_gpio_t pd16;
|
||||
extern const sl_gpio_t pd17;
|
||||
extern const sl_gpio_t pd18;
|
||||
extern const sl_gpio_t pd19;
|
||||
extern const sl_gpio_t pd20;
|
||||
extern const sl_gpio_t pd21;
|
||||
extern const sl_gpio_t pd22;
|
||||
extern const sl_gpio_t pd23;
|
||||
extern const sl_gpio_t pd24;
|
||||
extern const sl_gpio_t pd25;
|
||||
extern const sl_gpio_t pd26;
|
||||
extern const sl_gpio_t pd27;
|
||||
extern const sl_gpio_t pd28;
|
||||
extern const sl_gpio_t pd29;
|
||||
extern const sl_gpio_t pd30;
|
||||
extern const sl_gpio_t pd31;
|
||||
extern const sl_gpio_t pd32;
|
||||
|
||||
/// @endcond
|
||||
|
||||
/** @} (end addtogroup device_gpio) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // SL_DEVICE_GPIO_H
|
||||
2821
Libs/platform/service/device_manager/inc/sl_device_peripheral.h
Normal file
2821
Libs/platform/service/device_manager/inc/sl_device_peripheral.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,65 @@
|
||||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief Device Manager API Definition
|
||||
******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef SL_DEVICE_PERIPHERAL_TYPES_H
|
||||
#define SL_DEVICE_PERIPHERAL_TYPES_H
|
||||
|
||||
#include "sl_device_clock.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup device_peripheral Device Abstraction Peripheral
|
||||
*
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// TYPEDEFS
|
||||
|
||||
/// Define peripheral structure.
|
||||
typedef struct sl_peripheral {
|
||||
uint32_t base; ///< Peripheral base address.
|
||||
sl_clock_branch_t clk_branch; ///< Peripheral clock branch.
|
||||
sl_bus_clock_t bus_clock; ///< Peripheral bus clock.
|
||||
} sl_peripheral_val_t;
|
||||
|
||||
/// Define peripheral typedef.
|
||||
typedef const sl_peripheral_val_t* sl_peripheral_t;
|
||||
|
||||
/** @} (end addtogroup device_peripheral) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // SL_DEVICE_PERIPHERAL_TYPES_H
|
||||
351
Libs/platform/service/device_manager/src/sl_device_clock.c
Normal file
351
Libs/platform/service/device_manager/src/sl_device_clock.c
Normal file
@@ -0,0 +1,351 @@
|
||||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief Device Manager Clock API Definition
|
||||
******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "sl_device_clock.h"
|
||||
#include "cmsis_compiler.h"
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup device_clock Device Manager Clock
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
// External declaration for ACMP0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_ACMP0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for ACMP1 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_ACMP1_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for ADC0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_ADC0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for AGC peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_AGC_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for AMUXCP0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_AMUXCP0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for BUFC peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_BUFC_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for BURAM peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_BURAM_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for BURTC peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_BURTC_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for CRYPTOACC peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_CRYPTOACC_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for DCDC peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_DCDC_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for DEVINFO peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_DEVINFO_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for DMEM peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_DMEM_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for DPLL0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_DPLL0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for ECAIFADC peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_ECAIFADC_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for ETAMPDET peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_ETAMPDET_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for EUART0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_EUART0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for EUSART0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_EUSART0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for EUSART1 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_EUSART1_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for EUSART2 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_EUSART2_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for EUSART3 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_EUSART3_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for EUSART4 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_EUSART4_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for FRC peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_FRC_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for FSRCO peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_FSRCO_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for GPCRC0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_GPCRC0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for GPIO peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_GPIO_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for HFRCO0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_HFRCO0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for HFRCOEM23 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_HFRCOEM23_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for HFXO0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_HFXO0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for HOSTMAILBOX peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_HOSTMAILBOX_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for HOSTPORTAL peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_HOSTPORTAL_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for I2C0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_I2C0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for I2C1 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_I2C1_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for I2C2 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_I2C2_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for I2C3 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_I2C3_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for IADC0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_IADC0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for ICACHE0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_ICACHE0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for IFADCDEBUG peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_IFADCDEBUG_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for KEYSCAN peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_KEYSCAN_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for KSU peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_KSU_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for L2ICACHE0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_L2ICACHE0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for LCD peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_LCD_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for LDMA0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_LDMA0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for LDMAXBAR0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_LDMAXBAR0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for LEDDRV0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_LEDDRV0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for LESENSE peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_LESENSE_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for LETIMER0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_LETIMER0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for LFRCO peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_LFRCO_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for LFXO peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_LFXO_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for LPWAES peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_LPWAES_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for LPW0PORTAL peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_LPW0PORTAL_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for MODEM peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_MODEM_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for MSC peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_MSC_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for MVP peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_MVP_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for PCNT0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_PCNT0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for PDM peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_PDM_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for PIXELRZ0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_PIXELRZ0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for PIXELRZ1 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_PIXELRZ1_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for PRORTC peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_PRORTC_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for PROTIMER peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_PROTIMER_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for PRS peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_PRS_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RAC peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RAC_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RADIOAES peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RADIOAES_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RDMAILBOX0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RDMAILBOX0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RDMAILBOX1 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RDMAILBOX1_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RDSCRATCHPAD peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RDSCRATCHPAD_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RFCRC peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RFCRC_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RFECA0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RFECA0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RFECA1 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RFECA1_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RFFPLL0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RFFPLL0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RFMAILBOX peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RFMAILBOX_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RFSCRATCHPAD peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RFSCRATCHPAD_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RFSENSE peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RFSENSE_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RPA peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RPA_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for RTCC peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_RTCC_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for SCRATCHPAD peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_SCRATCHPAD_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for SEMAILBOX peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_SEMAILBOX_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for SEMAPHORE0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_SEMAPHORE0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for SEMAPHORE1 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_SEMAPHORE1_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for SEPORTAL peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_SEPORTAL_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for SMU peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_SMU_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for SOCPLL0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_SOCPLL0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for SYMCRYPTO peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_SYMCRYPTO_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for SYNTH peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_SYNTH_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for SYSCFG peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_SYSCFG_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for SYSRTC0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_SYSRTC0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for TIMER0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_TIMER0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for TIMER1 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_TIMER1_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for TIMER2 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_TIMER2_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for TIMER3 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_TIMER3_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for TIMER4 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_TIMER4_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for TIMER5 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_TIMER5_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for TIMER6 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_TIMER6_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for TIMER7 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_TIMER7_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for TIMER8 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_TIMER8_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for TIMER9 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_TIMER9_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for ULFRCO peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_ULFRCO_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for USART0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_USART0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for USART1 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_USART1_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for USART2 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_USART2_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for USB peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_USB_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for VDAC0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_VDAC0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for VDAC1 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_VDAC1_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for WDOG0 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_WDOG0_VALUE = 0xFFFFFFFF;
|
||||
|
||||
// External declaration for WDOG1 peripheral bus clock value.
|
||||
__WEAK const uint32_t SL_BUS_CLOCK_WDOG1_VALUE = 0xFFFFFFFF;
|
||||
|
||||
/** @} (end addtogroup device_clock) */
|
||||
403
Libs/platform/service/device_manager/src/sl_device_gpio.c
Normal file
403
Libs/platform/service/device_manager/src/sl_device_gpio.c
Normal file
@@ -0,0 +1,403 @@
|
||||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief Device Manager Clock API Definition
|
||||
******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "sl_device_gpio.h"
|
||||
#include "cmsis_compiler.h"
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup device_gpio Device Manager GPIO
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/// Declarations for port and pins
|
||||
const sl_gpio_t pa0 = { .port = SL_GPIO_PORT_A, .pin = 0 };
|
||||
const sl_gpio_t pa1 = { .port = SL_GPIO_PORT_A, .pin = 1 };
|
||||
const sl_gpio_t pa2 = { .port = SL_GPIO_PORT_A, .pin = 2 };
|
||||
const sl_gpio_t pa3 = { .port = SL_GPIO_PORT_A, .pin = 3 };
|
||||
const sl_gpio_t pa4 = { .port = SL_GPIO_PORT_A, .pin = 4 };
|
||||
const sl_gpio_t pa5 = { .port = SL_GPIO_PORT_A, .pin = 5 };
|
||||
const sl_gpio_t pa6 = { .port = SL_GPIO_PORT_A, .pin = 6 };
|
||||
const sl_gpio_t pa7 = { .port = SL_GPIO_PORT_A, .pin = 7 };
|
||||
const sl_gpio_t pa8 = { .port = SL_GPIO_PORT_A, .pin = 8 };
|
||||
const sl_gpio_t pa9 = { .port = SL_GPIO_PORT_A, .pin = 9 };
|
||||
const sl_gpio_t pa10 = { .port = SL_GPIO_PORT_A, .pin = 10 };
|
||||
const sl_gpio_t pa11 = { .port = SL_GPIO_PORT_A, .pin = 11 };
|
||||
const sl_gpio_t pa12 = { .port = SL_GPIO_PORT_A, .pin = 12 };
|
||||
const sl_gpio_t pa13 = { .port = SL_GPIO_PORT_A, .pin = 13 };
|
||||
const sl_gpio_t pa14 = { .port = SL_GPIO_PORT_A, .pin = 14 };
|
||||
const sl_gpio_t pa15 = { .port = SL_GPIO_PORT_A, .pin = 15 };
|
||||
const sl_gpio_t pa16 = { .port = SL_GPIO_PORT_A, .pin = 16 };
|
||||
const sl_gpio_t pa17 = { .port = SL_GPIO_PORT_A, .pin = 17 };
|
||||
const sl_gpio_t pa18 = { .port = SL_GPIO_PORT_A, .pin = 18 };
|
||||
const sl_gpio_t pa19 = { .port = SL_GPIO_PORT_A, .pin = 19 };
|
||||
const sl_gpio_t pa20 = { .port = SL_GPIO_PORT_A, .pin = 20 };
|
||||
const sl_gpio_t pa21 = { .port = SL_GPIO_PORT_A, .pin = 21 };
|
||||
const sl_gpio_t pa22 = { .port = SL_GPIO_PORT_A, .pin = 22 };
|
||||
const sl_gpio_t pa23 = { .port = SL_GPIO_PORT_A, .pin = 23 };
|
||||
const sl_gpio_t pa24 = { .port = SL_GPIO_PORT_A, .pin = 24 };
|
||||
const sl_gpio_t pa25 = { .port = SL_GPIO_PORT_A, .pin = 25 };
|
||||
const sl_gpio_t pa26 = { .port = SL_GPIO_PORT_A, .pin = 26 };
|
||||
const sl_gpio_t pa27 = { .port = SL_GPIO_PORT_A, .pin = 27 };
|
||||
const sl_gpio_t pa28 = { .port = SL_GPIO_PORT_A, .pin = 28 };
|
||||
const sl_gpio_t pa29 = { .port = SL_GPIO_PORT_A, .pin = 29 };
|
||||
const sl_gpio_t pa30 = { .port = SL_GPIO_PORT_A, .pin = 30 };
|
||||
const sl_gpio_t pa31 = { .port = SL_GPIO_PORT_A, .pin = 31 };
|
||||
|
||||
const sl_gpio_t pb0 = { .port = SL_GPIO_PORT_B, .pin = 0 };
|
||||
const sl_gpio_t pb1 = { .port = SL_GPIO_PORT_B, .pin = 1 };
|
||||
const sl_gpio_t pb2 = { .port = SL_GPIO_PORT_B, .pin = 2 };
|
||||
const sl_gpio_t pb3 = { .port = SL_GPIO_PORT_B, .pin = 3 };
|
||||
const sl_gpio_t pb4 = { .port = SL_GPIO_PORT_B, .pin = 4 };
|
||||
const sl_gpio_t pb5 = { .port = SL_GPIO_PORT_B, .pin = 5 };
|
||||
const sl_gpio_t pb6 = { .port = SL_GPIO_PORT_B, .pin = 6 };
|
||||
const sl_gpio_t pb7 = { .port = SL_GPIO_PORT_B, .pin = 7 };
|
||||
const sl_gpio_t pb8 = { .port = SL_GPIO_PORT_B, .pin = 8 };
|
||||
const sl_gpio_t pb9 = { .port = SL_GPIO_PORT_B, .pin = 9 };
|
||||
const sl_gpio_t pb10 = { .port = SL_GPIO_PORT_B, .pin = 10 };
|
||||
const sl_gpio_t pb11 = { .port = SL_GPIO_PORT_B, .pin = 11 };
|
||||
const sl_gpio_t pb12 = { .port = SL_GPIO_PORT_B, .pin = 12 };
|
||||
const sl_gpio_t pb13 = { .port = SL_GPIO_PORT_B, .pin = 13 };
|
||||
const sl_gpio_t pb14 = { .port = SL_GPIO_PORT_B, .pin = 14 };
|
||||
const sl_gpio_t pb15 = { .port = SL_GPIO_PORT_B, .pin = 15 };
|
||||
const sl_gpio_t pb16 = { .port = SL_GPIO_PORT_B, .pin = 16 };
|
||||
const sl_gpio_t pb17 = { .port = SL_GPIO_PORT_B, .pin = 17 };
|
||||
const sl_gpio_t pb18 = { .port = SL_GPIO_PORT_B, .pin = 18 };
|
||||
const sl_gpio_t pb19 = { .port = SL_GPIO_PORT_B, .pin = 19 };
|
||||
const sl_gpio_t pb20 = { .port = SL_GPIO_PORT_B, .pin = 20 };
|
||||
const sl_gpio_t pb21 = { .port = SL_GPIO_PORT_B, .pin = 21 };
|
||||
const sl_gpio_t pb22 = { .port = SL_GPIO_PORT_B, .pin = 22 };
|
||||
const sl_gpio_t pb23 = { .port = SL_GPIO_PORT_B, .pin = 23 };
|
||||
const sl_gpio_t pb24 = { .port = SL_GPIO_PORT_B, .pin = 24 };
|
||||
const sl_gpio_t pb25 = { .port = SL_GPIO_PORT_B, .pin = 25 };
|
||||
const sl_gpio_t pb26 = { .port = SL_GPIO_PORT_B, .pin = 26 };
|
||||
const sl_gpio_t pb27 = { .port = SL_GPIO_PORT_B, .pin = 27 };
|
||||
const sl_gpio_t pb28 = { .port = SL_GPIO_PORT_B, .pin = 28 };
|
||||
const sl_gpio_t pb29 = { .port = SL_GPIO_PORT_B, .pin = 29 };
|
||||
const sl_gpio_t pb30 = { .port = SL_GPIO_PORT_B, .pin = 30 };
|
||||
const sl_gpio_t pb31 = { .port = SL_GPIO_PORT_B, .pin = 31 };
|
||||
|
||||
const sl_gpio_t pc0 = { .port = SL_GPIO_PORT_C, .pin = 0 };
|
||||
const sl_gpio_t pc1 = { .port = SL_GPIO_PORT_C, .pin = 1 };
|
||||
const sl_gpio_t pc2 = { .port = SL_GPIO_PORT_C, .pin = 2 };
|
||||
const sl_gpio_t pc3 = { .port = SL_GPIO_PORT_C, .pin = 3 };
|
||||
const sl_gpio_t pc4 = { .port = SL_GPIO_PORT_C, .pin = 4 };
|
||||
const sl_gpio_t pc5 = { .port = SL_GPIO_PORT_C, .pin = 5 };
|
||||
const sl_gpio_t pc6 = { .port = SL_GPIO_PORT_C, .pin = 6 };
|
||||
const sl_gpio_t pc7 = { .port = SL_GPIO_PORT_C, .pin = 7 };
|
||||
const sl_gpio_t pc8 = { .port = SL_GPIO_PORT_C, .pin = 8 };
|
||||
const sl_gpio_t pc9 = { .port = SL_GPIO_PORT_C, .pin = 9 };
|
||||
const sl_gpio_t pc10 = { .port = SL_GPIO_PORT_C, .pin = 10 };
|
||||
const sl_gpio_t pc11 = { .port = SL_GPIO_PORT_C, .pin = 11 };
|
||||
const sl_gpio_t pc12 = { .port = SL_GPIO_PORT_C, .pin = 12 };
|
||||
const sl_gpio_t pc13 = { .port = SL_GPIO_PORT_C, .pin = 13 };
|
||||
const sl_gpio_t pc14 = { .port = SL_GPIO_PORT_C, .pin = 14 };
|
||||
const sl_gpio_t pc15 = { .port = SL_GPIO_PORT_C, .pin = 15 };
|
||||
const sl_gpio_t pc16 = { .port = SL_GPIO_PORT_C, .pin = 16 };
|
||||
const sl_gpio_t pc17 = { .port = SL_GPIO_PORT_C, .pin = 17 };
|
||||
const sl_gpio_t pc18 = { .port = SL_GPIO_PORT_C, .pin = 18 };
|
||||
const sl_gpio_t pc19 = { .port = SL_GPIO_PORT_C, .pin = 19 };
|
||||
const sl_gpio_t pc20 = { .port = SL_GPIO_PORT_C, .pin = 20 };
|
||||
const sl_gpio_t pc21 = { .port = SL_GPIO_PORT_C, .pin = 21 };
|
||||
const sl_gpio_t pc22 = { .port = SL_GPIO_PORT_C, .pin = 22 };
|
||||
const sl_gpio_t pc23 = { .port = SL_GPIO_PORT_C, .pin = 23 };
|
||||
const sl_gpio_t pc24 = { .port = SL_GPIO_PORT_C, .pin = 24 };
|
||||
const sl_gpio_t pc25 = { .port = SL_GPIO_PORT_C, .pin = 25 };
|
||||
const sl_gpio_t pc26 = { .port = SL_GPIO_PORT_C, .pin = 26 };
|
||||
const sl_gpio_t pc27 = { .port = SL_GPIO_PORT_C, .pin = 27 };
|
||||
const sl_gpio_t pc28 = { .port = SL_GPIO_PORT_C, .pin = 28 };
|
||||
const sl_gpio_t pc29 = { .port = SL_GPIO_PORT_C, .pin = 29 };
|
||||
const sl_gpio_t pc30 = { .port = SL_GPIO_PORT_C, .pin = 30 };
|
||||
const sl_gpio_t pc31 = { .port = SL_GPIO_PORT_C, .pin = 31 };
|
||||
|
||||
const sl_gpio_t pd0 = { .port = SL_GPIO_PORT_D, .pin = 0 };
|
||||
const sl_gpio_t pd1 = { .port = SL_GPIO_PORT_D, .pin = 1 };
|
||||
const sl_gpio_t pd2 = { .port = SL_GPIO_PORT_D, .pin = 2 };
|
||||
const sl_gpio_t pd3 = { .port = SL_GPIO_PORT_D, .pin = 3 };
|
||||
const sl_gpio_t pd4 = { .port = SL_GPIO_PORT_D, .pin = 4 };
|
||||
const sl_gpio_t pd5 = { .port = SL_GPIO_PORT_D, .pin = 5 };
|
||||
const sl_gpio_t pd6 = { .port = SL_GPIO_PORT_D, .pin = 6 };
|
||||
const sl_gpio_t pd7 = { .port = SL_GPIO_PORT_D, .pin = 7 };
|
||||
const sl_gpio_t pd8 = { .port = SL_GPIO_PORT_D, .pin = 8 };
|
||||
const sl_gpio_t pd9 = { .port = SL_GPIO_PORT_D, .pin = 9 };
|
||||
const sl_gpio_t pd10 = { .port = SL_GPIO_PORT_D, .pin = 10 };
|
||||
const sl_gpio_t pd11 = { .port = SL_GPIO_PORT_D, .pin = 11 };
|
||||
const sl_gpio_t pd12 = { .port = SL_GPIO_PORT_D, .pin = 12 };
|
||||
const sl_gpio_t pd13 = { .port = SL_GPIO_PORT_D, .pin = 13 };
|
||||
const sl_gpio_t pd14 = { .port = SL_GPIO_PORT_D, .pin = 14 };
|
||||
const sl_gpio_t pd15 = { .port = SL_GPIO_PORT_D, .pin = 15 };
|
||||
const sl_gpio_t pd16 = { .port = SL_GPIO_PORT_D, .pin = 16 };
|
||||
const sl_gpio_t pd17 = { .port = SL_GPIO_PORT_D, .pin = 17 };
|
||||
const sl_gpio_t pd18 = { .port = SL_GPIO_PORT_D, .pin = 18 };
|
||||
const sl_gpio_t pd19 = { .port = SL_GPIO_PORT_D, .pin = 19 };
|
||||
const sl_gpio_t pd20 = { .port = SL_GPIO_PORT_D, .pin = 20 };
|
||||
const sl_gpio_t pd21 = { .port = SL_GPIO_PORT_D, .pin = 21 };
|
||||
const sl_gpio_t pd22 = { .port = SL_GPIO_PORT_D, .pin = 22 };
|
||||
const sl_gpio_t pd23 = { .port = SL_GPIO_PORT_D, .pin = 23 };
|
||||
const sl_gpio_t pd24 = { .port = SL_GPIO_PORT_D, .pin = 24 };
|
||||
const sl_gpio_t pd25 = { .port = SL_GPIO_PORT_D, .pin = 25 };
|
||||
const sl_gpio_t pd26 = { .port = SL_GPIO_PORT_D, .pin = 26 };
|
||||
const sl_gpio_t pd27 = { .port = SL_GPIO_PORT_D, .pin = 27 };
|
||||
const sl_gpio_t pd28 = { .port = SL_GPIO_PORT_D, .pin = 28 };
|
||||
const sl_gpio_t pd29 = { .port = SL_GPIO_PORT_D, .pin = 29 };
|
||||
const sl_gpio_t pd30 = { .port = SL_GPIO_PORT_D, .pin = 30 };
|
||||
const sl_gpio_t pd31 = { .port = SL_GPIO_PORT_D, .pin = 31 };
|
||||
|
||||
const sl_gpio_t pe0 = { .port = SL_GPIO_PORT_E, .pin = 0 };
|
||||
const sl_gpio_t pe1 = { .port = SL_GPIO_PORT_E, .pin = 1 };
|
||||
const sl_gpio_t pe2 = { .port = SL_GPIO_PORT_E, .pin = 2 };
|
||||
const sl_gpio_t pe3 = { .port = SL_GPIO_PORT_E, .pin = 3 };
|
||||
const sl_gpio_t pe4 = { .port = SL_GPIO_PORT_E, .pin = 4 };
|
||||
const sl_gpio_t pe5 = { .port = SL_GPIO_PORT_E, .pin = 5 };
|
||||
const sl_gpio_t pe6 = { .port = SL_GPIO_PORT_E, .pin = 6 };
|
||||
const sl_gpio_t pe7 = { .port = SL_GPIO_PORT_E, .pin = 7 };
|
||||
const sl_gpio_t pe8 = { .port = SL_GPIO_PORT_E, .pin = 8 };
|
||||
const sl_gpio_t pe9 = { .port = SL_GPIO_PORT_E, .pin = 9 };
|
||||
const sl_gpio_t pe10 = { .port = SL_GPIO_PORT_E, .pin = 10 };
|
||||
const sl_gpio_t pe11 = { .port = SL_GPIO_PORT_E, .pin = 11 };
|
||||
const sl_gpio_t pe12 = { .port = SL_GPIO_PORT_E, .pin = 12 };
|
||||
const sl_gpio_t pe13 = { .port = SL_GPIO_PORT_E, .pin = 13 };
|
||||
const sl_gpio_t pe14 = { .port = SL_GPIO_PORT_E, .pin = 14 };
|
||||
const sl_gpio_t pe15 = { .port = SL_GPIO_PORT_E, .pin = 15 };
|
||||
const sl_gpio_t pe16 = { .port = SL_GPIO_PORT_E, .pin = 16 };
|
||||
const sl_gpio_t pe17 = { .port = SL_GPIO_PORT_E, .pin = 17 };
|
||||
const sl_gpio_t pe18 = { .port = SL_GPIO_PORT_E, .pin = 18 };
|
||||
const sl_gpio_t pe19 = { .port = SL_GPIO_PORT_E, .pin = 19 };
|
||||
const sl_gpio_t pe20 = { .port = SL_GPIO_PORT_E, .pin = 20 };
|
||||
const sl_gpio_t pe21 = { .port = SL_GPIO_PORT_E, .pin = 21 };
|
||||
const sl_gpio_t pe22 = { .port = SL_GPIO_PORT_E, .pin = 22 };
|
||||
const sl_gpio_t pe23 = { .port = SL_GPIO_PORT_E, .pin = 23 };
|
||||
const sl_gpio_t pe24 = { .port = SL_GPIO_PORT_E, .pin = 24 };
|
||||
const sl_gpio_t pe25 = { .port = SL_GPIO_PORT_E, .pin = 25 };
|
||||
const sl_gpio_t pe26 = { .port = SL_GPIO_PORT_E, .pin = 26 };
|
||||
const sl_gpio_t pe27 = { .port = SL_GPIO_PORT_E, .pin = 27 };
|
||||
const sl_gpio_t pe28 = { .port = SL_GPIO_PORT_E, .pin = 28 };
|
||||
const sl_gpio_t pe29 = { .port = SL_GPIO_PORT_E, .pin = 29 };
|
||||
const sl_gpio_t pe30 = { .port = SL_GPIO_PORT_E, .pin = 30 };
|
||||
const sl_gpio_t pe31 = { .port = SL_GPIO_PORT_E, .pin = 31 };
|
||||
|
||||
const sl_gpio_t pf0 = { .port = SL_GPIO_PORT_F, .pin = 0 };
|
||||
const sl_gpio_t pf1 = { .port = SL_GPIO_PORT_F, .pin = 1 };
|
||||
const sl_gpio_t pf2 = { .port = SL_GPIO_PORT_F, .pin = 2 };
|
||||
const sl_gpio_t pf3 = { .port = SL_GPIO_PORT_F, .pin = 3 };
|
||||
const sl_gpio_t pf4 = { .port = SL_GPIO_PORT_F, .pin = 4 };
|
||||
const sl_gpio_t pf5 = { .port = SL_GPIO_PORT_F, .pin = 5 };
|
||||
const sl_gpio_t pf6 = { .port = SL_GPIO_PORT_F, .pin = 6 };
|
||||
const sl_gpio_t pf7 = { .port = SL_GPIO_PORT_F, .pin = 7 };
|
||||
const sl_gpio_t pf8 = { .port = SL_GPIO_PORT_F, .pin = 8 };
|
||||
const sl_gpio_t pf9 = { .port = SL_GPIO_PORT_F, .pin = 9 };
|
||||
const sl_gpio_t pf10 = { .port = SL_GPIO_PORT_F, .pin = 10 };
|
||||
const sl_gpio_t pf11 = { .port = SL_GPIO_PORT_F, .pin = 11 };
|
||||
const sl_gpio_t pf12 = { .port = SL_GPIO_PORT_F, .pin = 12 };
|
||||
const sl_gpio_t pf13 = { .port = SL_GPIO_PORT_F, .pin = 13 };
|
||||
const sl_gpio_t pf14 = { .port = SL_GPIO_PORT_F, .pin = 14 };
|
||||
const sl_gpio_t pf15 = { .port = SL_GPIO_PORT_F, .pin = 15 };
|
||||
const sl_gpio_t pf16 = { .port = SL_GPIO_PORT_F, .pin = 16 };
|
||||
const sl_gpio_t pf17 = { .port = SL_GPIO_PORT_F, .pin = 17 };
|
||||
const sl_gpio_t pf18 = { .port = SL_GPIO_PORT_F, .pin = 18 };
|
||||
const sl_gpio_t pf19 = { .port = SL_GPIO_PORT_F, .pin = 19 };
|
||||
const sl_gpio_t pf20 = { .port = SL_GPIO_PORT_F, .pin = 20 };
|
||||
const sl_gpio_t pf21 = { .port = SL_GPIO_PORT_F, .pin = 21 };
|
||||
const sl_gpio_t pf22 = { .port = SL_GPIO_PORT_F, .pin = 22 };
|
||||
const sl_gpio_t pf23 = { .port = SL_GPIO_PORT_F, .pin = 23 };
|
||||
const sl_gpio_t pf24 = { .port = SL_GPIO_PORT_F, .pin = 24 };
|
||||
const sl_gpio_t pf25 = { .port = SL_GPIO_PORT_F, .pin = 25 };
|
||||
const sl_gpio_t pf26 = { .port = SL_GPIO_PORT_F, .pin = 26 };
|
||||
const sl_gpio_t pf27 = { .port = SL_GPIO_PORT_F, .pin = 27 };
|
||||
const sl_gpio_t pf28 = { .port = SL_GPIO_PORT_F, .pin = 28 };
|
||||
const sl_gpio_t pf29 = { .port = SL_GPIO_PORT_F, .pin = 29 };
|
||||
const sl_gpio_t pf30 = { .port = SL_GPIO_PORT_F, .pin = 30 };
|
||||
const sl_gpio_t pf31 = { .port = SL_GPIO_PORT_F, .pin = 31 };
|
||||
|
||||
const sl_gpio_t pg0 = { .port = SL_GPIO_PORT_G, .pin = 0 };
|
||||
const sl_gpio_t pg1 = { .port = SL_GPIO_PORT_G, .pin = 1 };
|
||||
const sl_gpio_t pg2 = { .port = SL_GPIO_PORT_G, .pin = 2 };
|
||||
const sl_gpio_t pg3 = { .port = SL_GPIO_PORT_G, .pin = 3 };
|
||||
const sl_gpio_t pg4 = { .port = SL_GPIO_PORT_G, .pin = 4 };
|
||||
const sl_gpio_t pg5 = { .port = SL_GPIO_PORT_G, .pin = 5 };
|
||||
const sl_gpio_t pg6 = { .port = SL_GPIO_PORT_G, .pin = 6 };
|
||||
const sl_gpio_t pg7 = { .port = SL_GPIO_PORT_G, .pin = 7 };
|
||||
const sl_gpio_t pg8 = { .port = SL_GPIO_PORT_G, .pin = 8 };
|
||||
const sl_gpio_t pg9 = { .port = SL_GPIO_PORT_G, .pin = 9 };
|
||||
const sl_gpio_t pg10 = { .port = SL_GPIO_PORT_G, .pin = 10 };
|
||||
const sl_gpio_t pg11 = { .port = SL_GPIO_PORT_G, .pin = 11 };
|
||||
const sl_gpio_t pg12 = { .port = SL_GPIO_PORT_G, .pin = 12 };
|
||||
const sl_gpio_t pg13 = { .port = SL_GPIO_PORT_G, .pin = 13 };
|
||||
const sl_gpio_t pg14 = { .port = SL_GPIO_PORT_G, .pin = 14 };
|
||||
const sl_gpio_t pg15 = { .port = SL_GPIO_PORT_G, .pin = 15 };
|
||||
const sl_gpio_t pg16 = { .port = SL_GPIO_PORT_G, .pin = 16 };
|
||||
const sl_gpio_t pg17 = { .port = SL_GPIO_PORT_G, .pin = 17 };
|
||||
const sl_gpio_t pg18 = { .port = SL_GPIO_PORT_G, .pin = 18 };
|
||||
const sl_gpio_t pg19 = { .port = SL_GPIO_PORT_G, .pin = 19 };
|
||||
const sl_gpio_t pg20 = { .port = SL_GPIO_PORT_G, .pin = 20 };
|
||||
const sl_gpio_t pg21 = { .port = SL_GPIO_PORT_G, .pin = 21 };
|
||||
const sl_gpio_t pg22 = { .port = SL_GPIO_PORT_G, .pin = 22 };
|
||||
const sl_gpio_t pg23 = { .port = SL_GPIO_PORT_G, .pin = 23 };
|
||||
const sl_gpio_t pg24 = { .port = SL_GPIO_PORT_G, .pin = 24 };
|
||||
const sl_gpio_t pg25 = { .port = SL_GPIO_PORT_G, .pin = 25 };
|
||||
const sl_gpio_t pg26 = { .port = SL_GPIO_PORT_G, .pin = 26 };
|
||||
const sl_gpio_t pg27 = { .port = SL_GPIO_PORT_G, .pin = 27 };
|
||||
const sl_gpio_t pg28 = { .port = SL_GPIO_PORT_G, .pin = 28 };
|
||||
const sl_gpio_t pg29 = { .port = SL_GPIO_PORT_G, .pin = 29 };
|
||||
const sl_gpio_t pg30 = { .port = SL_GPIO_PORT_G, .pin = 30 };
|
||||
const sl_gpio_t pg31 = { .port = SL_GPIO_PORT_G, .pin = 31 };
|
||||
|
||||
const sl_gpio_t ph0 = { .port = SL_GPIO_PORT_H, .pin = 0 };
|
||||
const sl_gpio_t ph1 = { .port = SL_GPIO_PORT_H, .pin = 1 };
|
||||
const sl_gpio_t ph2 = { .port = SL_GPIO_PORT_H, .pin = 2 };
|
||||
const sl_gpio_t ph3 = { .port = SL_GPIO_PORT_H, .pin = 3 };
|
||||
const sl_gpio_t ph4 = { .port = SL_GPIO_PORT_H, .pin = 4 };
|
||||
const sl_gpio_t ph5 = { .port = SL_GPIO_PORT_H, .pin = 5 };
|
||||
const sl_gpio_t ph6 = { .port = SL_GPIO_PORT_H, .pin = 6 };
|
||||
const sl_gpio_t ph7 = { .port = SL_GPIO_PORT_H, .pin = 7 };
|
||||
const sl_gpio_t ph8 = { .port = SL_GPIO_PORT_H, .pin = 8 };
|
||||
const sl_gpio_t ph9 = { .port = SL_GPIO_PORT_H, .pin = 9 };
|
||||
const sl_gpio_t ph10 = { .port = SL_GPIO_PORT_H, .pin = 10 };
|
||||
const sl_gpio_t ph11 = { .port = SL_GPIO_PORT_H, .pin = 11 };
|
||||
const sl_gpio_t ph12 = { .port = SL_GPIO_PORT_H, .pin = 12 };
|
||||
const sl_gpio_t ph13 = { .port = SL_GPIO_PORT_H, .pin = 13 };
|
||||
const sl_gpio_t ph14 = { .port = SL_GPIO_PORT_H, .pin = 14 };
|
||||
const sl_gpio_t ph15 = { .port = SL_GPIO_PORT_H, .pin = 15 };
|
||||
const sl_gpio_t ph16 = { .port = SL_GPIO_PORT_H, .pin = 16 };
|
||||
const sl_gpio_t ph17 = { .port = SL_GPIO_PORT_H, .pin = 17 };
|
||||
const sl_gpio_t ph18 = { .port = SL_GPIO_PORT_H, .pin = 18 };
|
||||
const sl_gpio_t ph19 = { .port = SL_GPIO_PORT_H, .pin = 19 };
|
||||
const sl_gpio_t ph20 = { .port = SL_GPIO_PORT_H, .pin = 20 };
|
||||
const sl_gpio_t ph21 = { .port = SL_GPIO_PORT_H, .pin = 21 };
|
||||
const sl_gpio_t ph22 = { .port = SL_GPIO_PORT_H, .pin = 22 };
|
||||
const sl_gpio_t ph23 = { .port = SL_GPIO_PORT_H, .pin = 23 };
|
||||
const sl_gpio_t ph24 = { .port = SL_GPIO_PORT_H, .pin = 24 };
|
||||
const sl_gpio_t ph25 = { .port = SL_GPIO_PORT_H, .pin = 25 };
|
||||
const sl_gpio_t ph26 = { .port = SL_GPIO_PORT_H, .pin = 26 };
|
||||
const sl_gpio_t ph27 = { .port = SL_GPIO_PORT_H, .pin = 27 };
|
||||
const sl_gpio_t ph28 = { .port = SL_GPIO_PORT_H, .pin = 28 };
|
||||
const sl_gpio_t ph29 = { .port = SL_GPIO_PORT_H, .pin = 29 };
|
||||
const sl_gpio_t ph30 = { .port = SL_GPIO_PORT_H, .pin = 30 };
|
||||
const sl_gpio_t ph31 = { .port = SL_GPIO_PORT_H, .pin = 31 };
|
||||
|
||||
const sl_gpio_t pi0 = { .port = SL_GPIO_PORT_I, .pin = 0 };
|
||||
const sl_gpio_t pi1 = { .port = SL_GPIO_PORT_I, .pin = 1 };
|
||||
const sl_gpio_t pi2 = { .port = SL_GPIO_PORT_I, .pin = 2 };
|
||||
const sl_gpio_t pi3 = { .port = SL_GPIO_PORT_I, .pin = 3 };
|
||||
const sl_gpio_t pi4 = { .port = SL_GPIO_PORT_I, .pin = 4 };
|
||||
const sl_gpio_t pi5 = { .port = SL_GPIO_PORT_I, .pin = 5 };
|
||||
const sl_gpio_t pi6 = { .port = SL_GPIO_PORT_I, .pin = 6 };
|
||||
const sl_gpio_t pi7 = { .port = SL_GPIO_PORT_I, .pin = 7 };
|
||||
const sl_gpio_t pi8 = { .port = SL_GPIO_PORT_I, .pin = 8 };
|
||||
const sl_gpio_t pi9 = { .port = SL_GPIO_PORT_I, .pin = 9 };
|
||||
const sl_gpio_t pi10 = { .port = SL_GPIO_PORT_I, .pin = 10 };
|
||||
const sl_gpio_t pi11 = { .port = SL_GPIO_PORT_I, .pin = 11 };
|
||||
const sl_gpio_t pi12 = { .port = SL_GPIO_PORT_I, .pin = 12 };
|
||||
const sl_gpio_t pi13 = { .port = SL_GPIO_PORT_I, .pin = 13 };
|
||||
const sl_gpio_t pi14 = { .port = SL_GPIO_PORT_I, .pin = 14 };
|
||||
const sl_gpio_t pi15 = { .port = SL_GPIO_PORT_I, .pin = 15 };
|
||||
const sl_gpio_t pi16 = { .port = SL_GPIO_PORT_I, .pin = 16 };
|
||||
const sl_gpio_t pi17 = { .port = SL_GPIO_PORT_I, .pin = 17 };
|
||||
const sl_gpio_t pi18 = { .port = SL_GPIO_PORT_I, .pin = 18 };
|
||||
const sl_gpio_t pi19 = { .port = SL_GPIO_PORT_I, .pin = 19 };
|
||||
const sl_gpio_t pi20 = { .port = SL_GPIO_PORT_I, .pin = 20 };
|
||||
const sl_gpio_t pi21 = { .port = SL_GPIO_PORT_I, .pin = 21 };
|
||||
const sl_gpio_t pi22 = { .port = SL_GPIO_PORT_I, .pin = 22 };
|
||||
const sl_gpio_t pi23 = { .port = SL_GPIO_PORT_I, .pin = 23 };
|
||||
const sl_gpio_t pi24 = { .port = SL_GPIO_PORT_I, .pin = 24 };
|
||||
const sl_gpio_t pi25 = { .port = SL_GPIO_PORT_I, .pin = 25 };
|
||||
const sl_gpio_t pi26 = { .port = SL_GPIO_PORT_I, .pin = 26 };
|
||||
const sl_gpio_t pi27 = { .port = SL_GPIO_PORT_I, .pin = 27 };
|
||||
const sl_gpio_t pi28 = { .port = SL_GPIO_PORT_I, .pin = 28 };
|
||||
const sl_gpio_t pi29 = { .port = SL_GPIO_PORT_I, .pin = 29 };
|
||||
const sl_gpio_t pi30 = { .port = SL_GPIO_PORT_I, .pin = 30 };
|
||||
const sl_gpio_t pi31 = { .port = SL_GPIO_PORT_I, .pin = 31 };
|
||||
|
||||
const sl_gpio_t pj0 = { .port = SL_GPIO_PORT_J, .pin = 0 };
|
||||
const sl_gpio_t pj1 = { .port = SL_GPIO_PORT_J, .pin = 1 };
|
||||
const sl_gpio_t pj2 = { .port = SL_GPIO_PORT_J, .pin = 2 };
|
||||
const sl_gpio_t pj3 = { .port = SL_GPIO_PORT_J, .pin = 3 };
|
||||
const sl_gpio_t pj4 = { .port = SL_GPIO_PORT_J, .pin = 4 };
|
||||
const sl_gpio_t pj5 = { .port = SL_GPIO_PORT_J, .pin = 5 };
|
||||
const sl_gpio_t pj6 = { .port = SL_GPIO_PORT_J, .pin = 6 };
|
||||
const sl_gpio_t pj7 = { .port = SL_GPIO_PORT_J, .pin = 7 };
|
||||
const sl_gpio_t pj8 = { .port = SL_GPIO_PORT_J, .pin = 8 };
|
||||
const sl_gpio_t pj9 = { .port = SL_GPIO_PORT_J, .pin = 9 };
|
||||
const sl_gpio_t pj10 = { .port = SL_GPIO_PORT_J, .pin = 10 };
|
||||
const sl_gpio_t pj11 = { .port = SL_GPIO_PORT_J, .pin = 11 };
|
||||
const sl_gpio_t pj12 = { .port = SL_GPIO_PORT_J, .pin = 12 };
|
||||
const sl_gpio_t pj13 = { .port = SL_GPIO_PORT_J, .pin = 13 };
|
||||
const sl_gpio_t pj14 = { .port = SL_GPIO_PORT_J, .pin = 14 };
|
||||
const sl_gpio_t pj15 = { .port = SL_GPIO_PORT_J, .pin = 15 };
|
||||
const sl_gpio_t pj16 = { .port = SL_GPIO_PORT_J, .pin = 16 };
|
||||
const sl_gpio_t pj17 = { .port = SL_GPIO_PORT_J, .pin = 17 };
|
||||
const sl_gpio_t pj18 = { .port = SL_GPIO_PORT_J, .pin = 18 };
|
||||
const sl_gpio_t pj19 = { .port = SL_GPIO_PORT_J, .pin = 19 };
|
||||
const sl_gpio_t pj20 = { .port = SL_GPIO_PORT_J, .pin = 20 };
|
||||
const sl_gpio_t pj21 = { .port = SL_GPIO_PORT_J, .pin = 21 };
|
||||
const sl_gpio_t pj22 = { .port = SL_GPIO_PORT_J, .pin = 22 };
|
||||
const sl_gpio_t pj23 = { .port = SL_GPIO_PORT_J, .pin = 23 };
|
||||
const sl_gpio_t pj24 = { .port = SL_GPIO_PORT_J, .pin = 24 };
|
||||
const sl_gpio_t pj25 = { .port = SL_GPIO_PORT_J, .pin = 25 };
|
||||
const sl_gpio_t pj26 = { .port = SL_GPIO_PORT_J, .pin = 26 };
|
||||
const sl_gpio_t pj27 = { .port = SL_GPIO_PORT_J, .pin = 27 };
|
||||
const sl_gpio_t pj28 = { .port = SL_GPIO_PORT_J, .pin = 28 };
|
||||
const sl_gpio_t pj29 = { .port = SL_GPIO_PORT_J, .pin = 29 };
|
||||
const sl_gpio_t pj30 = { .port = SL_GPIO_PORT_J, .pin = 30 };
|
||||
const sl_gpio_t pj31 = { .port = SL_GPIO_PORT_J, .pin = 31 };
|
||||
|
||||
const sl_gpio_t pk0 = { .port = SL_GPIO_PORT_K, .pin = 0 };
|
||||
const sl_gpio_t pk1 = { .port = SL_GPIO_PORT_K, .pin = 1 };
|
||||
const sl_gpio_t pk2 = { .port = SL_GPIO_PORT_K, .pin = 2 };
|
||||
const sl_gpio_t pk3 = { .port = SL_GPIO_PORT_K, .pin = 3 };
|
||||
const sl_gpio_t pk4 = { .port = SL_GPIO_PORT_K, .pin = 4 };
|
||||
const sl_gpio_t pk5 = { .port = SL_GPIO_PORT_K, .pin = 5 };
|
||||
const sl_gpio_t pk6 = { .port = SL_GPIO_PORT_K, .pin = 6 };
|
||||
const sl_gpio_t pk7 = { .port = SL_GPIO_PORT_K, .pin = 7 };
|
||||
const sl_gpio_t pk8 = { .port = SL_GPIO_PORT_K, .pin = 8 };
|
||||
const sl_gpio_t pk9 = { .port = SL_GPIO_PORT_K, .pin = 9 };
|
||||
const sl_gpio_t pk10 = { .port = SL_GPIO_PORT_K, .pin = 10 };
|
||||
const sl_gpio_t pk11 = { .port = SL_GPIO_PORT_K, .pin = 11 };
|
||||
const sl_gpio_t pk12 = { .port = SL_GPIO_PORT_K, .pin = 12 };
|
||||
const sl_gpio_t pk13 = { .port = SL_GPIO_PORT_K, .pin = 13 };
|
||||
const sl_gpio_t pk14 = { .port = SL_GPIO_PORT_K, .pin = 14 };
|
||||
const sl_gpio_t pk15 = { .port = SL_GPIO_PORT_K, .pin = 15 };
|
||||
const sl_gpio_t pk16 = { .port = SL_GPIO_PORT_K, .pin = 16 };
|
||||
const sl_gpio_t pk17 = { .port = SL_GPIO_PORT_K, .pin = 17 };
|
||||
const sl_gpio_t pk18 = { .port = SL_GPIO_PORT_K, .pin = 18 };
|
||||
const sl_gpio_t pk19 = { .port = SL_GPIO_PORT_K, .pin = 19 };
|
||||
const sl_gpio_t pk20 = { .port = SL_GPIO_PORT_K, .pin = 20 };
|
||||
const sl_gpio_t pk21 = { .port = SL_GPIO_PORT_K, .pin = 21 };
|
||||
const sl_gpio_t pk22 = { .port = SL_GPIO_PORT_K, .pin = 22 };
|
||||
const sl_gpio_t pk23 = { .port = SL_GPIO_PORT_K, .pin = 23 };
|
||||
const sl_gpio_t pk24 = { .port = SL_GPIO_PORT_K, .pin = 24 };
|
||||
const sl_gpio_t pk25 = { .port = SL_GPIO_PORT_K, .pin = 25 };
|
||||
const sl_gpio_t pk26 = { .port = SL_GPIO_PORT_K, .pin = 26 };
|
||||
const sl_gpio_t pk27 = { .port = SL_GPIO_PORT_K, .pin = 27 };
|
||||
const sl_gpio_t pk28 = { .port = SL_GPIO_PORT_K, .pin = 28 };
|
||||
const sl_gpio_t pk29 = { .port = SL_GPIO_PORT_K, .pin = 29 };
|
||||
const sl_gpio_t pk30 = { .port = SL_GPIO_PORT_K, .pin = 30 };
|
||||
const sl_gpio_t pk31 = { .port = SL_GPIO_PORT_K, .pin = 31 };
|
||||
|
||||
/** @} (end addtogroup device_gpio) */
|
||||
769
Libs/platform/service/device_manager/src/sl_device_peripheral.c
Normal file
769
Libs/platform/service/device_manager/src/sl_device_peripheral.c
Normal file
@@ -0,0 +1,769 @@
|
||||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief Device Manager API Definition
|
||||
******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "sl_device_peripheral.h"
|
||||
#include "sl_device_clock.h"
|
||||
#include "cmsis_compiler.h"
|
||||
#include "em_device.h"
|
||||
/***************************************************************************//**
|
||||
* Device Abstraction Peripheral default values.
|
||||
******************************************************************************/
|
||||
// Weak definition of peripheral ACMP0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral ACMP1.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_acmp1 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral ADC0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_adc0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral AES.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_aes = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral AMUXCP0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_amuxcp0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral BUFC.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_bufc = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral BURAM.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_buram = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral BURTC.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral CMU.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral CRYPTOACC.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_cryptoacc = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral DCDC.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral DEVINFO.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_devinfo = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral DMEM.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_dmem = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral DMEM0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_dmem0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral DMEM1.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_dmem1 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral DPLL0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral EMU.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_emu = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral ETAMPDET.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_etampdet = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral EUART0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_euart0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral EUSART0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_eusart0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral EUSART1.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_eusart1 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral EUSART2.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_eusart2 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral EUSART3.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_eusart3 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral EUSART4.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_eusart4 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral FSRCO.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_fsrco = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral GPCRC0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_gpcrc0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral GPIO.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_gpio = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral HFRCO0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_hfrco0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral HFRCOEM23.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_hfrcoem23 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral HFXO0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral HOSTMAILBOX.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_hostmailbox = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral HOSTPORTAL.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_hostportal = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral I2C0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_i2c0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral I2C1.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_i2c1 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral I2C2.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_i2c2 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral I2C3.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_i2c3 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral IADC0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_iadc0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral ICACHE0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral KEYSCAN.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_keyscan = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral L1ICACHE0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_l1icache0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral L2ICACHE0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_l2icache0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral LCD.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_lcd = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral LCDRF.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_lcdrf = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral LDMA0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_ldma0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral LDMAXBAR0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_ldmaxbar0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral LEDDRV0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_leddrv0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral LESENSE.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_lesense = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral LETIMER0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_letimer0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral LFRCO.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_lfrco = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral LFXO.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_lfxo = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral LPWAES.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_lpwaes = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral LPW0PORTAL.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_lpw0portal = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral LVGD.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_lvgd = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral MPAHBRAM.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_mpahbram = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral MSC.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_msc = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral MVP.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_mvp = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral PCNT0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_pcnt0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral PDM.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_pdm = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral PFMXPPRF.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_pfmxpprf = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral PIXELRZ0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_pixelrz0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral PIXELRZ1.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_pixelrz1 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral PRORTC.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_prortc = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral PRS.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_prs = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral RADIOAES.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_radioaes = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral RFFPLL0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_rffpll0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral RPA.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_rpa = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral RTCC.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_rtcc = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral SCRATCHPAD.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_scratchpad = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral SEMAILBOX.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_semailbox = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral SEMAPHORE0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_semaphore0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral SEMAPHORE1.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_semaphore1 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral SEPORTAL.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_seportal = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral SEPUF.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_sepuf = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral SMU.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_smu = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral SOCPLL0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_socpll0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral SYMCRYPTO.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_symcrypto = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral SYSCFG.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral SYSRTC0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_sysrtc0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral TIMER0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_timer0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral TIMER1.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_timer1 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral TIMER2.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_timer2 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral TIMER3.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_timer3 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral TIMER4.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_timer4 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral TIMER5.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_timer5 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral TIMER6.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_timer6 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral TIMER7.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_timer7 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral TIMER8.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_timer8 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral TIMER9.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_timer9 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral ULFRCO.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_ulfrco = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral USART0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_usart0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral USART1.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_usart1 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral USART2.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_usart2 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral USB.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_usb = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral USBAHB.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_usbahb = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral USBPLL0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_usbpll0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral VDAC0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_vdac0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral VDAC1.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_vdac1 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral WDOG0.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_wdog0 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
// Weak definition of peripheral WDOG1.
|
||||
__WEAK const sl_peripheral_val_t sl_peripheral_val_wdog1 = { .base = 0xFFFFFFFF,
|
||||
.clk_branch = SL_CLOCK_BRANCH_INVALID,
|
||||
.bus_clock = SL_BUS_CLOCK_INVALID };
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
// Disable IAR multiple typedefs declaration warning.
|
||||
#pragma diag_suppress=Pe301
|
||||
#endif
|
||||
|
||||
// External base address getter declaration for ACMP.
|
||||
extern ACMP_TypeDef *sl_device_peripheral_acmp_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for ADC.
|
||||
extern ADC_TypeDef *sl_device_peripheral_adc_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for AES.
|
||||
extern AES_TypeDef *sl_device_peripheral_aes_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for AMUXCP.
|
||||
extern AMUXCP_TypeDef *sl_device_peripheral_amuxcp_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for BUFC.
|
||||
extern BUFC_TypeDef *sl_device_peripheral_bufc_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for BURAM.
|
||||
extern BURAM_TypeDef *sl_device_peripheral_buram_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for BURTC.
|
||||
extern BURTC_TypeDef *sl_device_peripheral_burtc_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for CMU.
|
||||
extern CMU_TypeDef *sl_device_peripheral_cmu_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for CRYPTOACC.
|
||||
extern CRYPTOACC_TypeDef *sl_device_peripheral_cryptoacc_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for CRYPTOACC_PKCTRL.
|
||||
extern CRYPTOACC_PKCTRL_TypeDef *sl_device_peripheral_cryptoacc_pkctrl_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for CRYPTOACC_RNGCTRL.
|
||||
extern CRYPTOACC_RNGCTRL_TypeDef *sl_device_peripheral_cryptoacc_rngctrl_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for DCDC.
|
||||
extern DCDC_TypeDef *sl_device_peripheral_dcdc_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for DEVINFO.
|
||||
extern DEVINFO_TypeDef *sl_device_peripheral_devinfo_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for DPLL.
|
||||
extern DPLL_TypeDef *sl_device_peripheral_dpll_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for EMU.
|
||||
extern EMU_TypeDef *sl_device_peripheral_emu_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for EMU_CFGNS.
|
||||
extern EMU_CFGNS_TypeDef *sl_device_peripheral_emu_cfgns_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for ETAMPDET.
|
||||
extern ETAMPDET_TypeDef *sl_device_peripheral_etampdet_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for EUSART.
|
||||
extern EUSART_TypeDef *sl_device_peripheral_eusart_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for FSRCO.
|
||||
extern FSRCO_TypeDef *sl_device_peripheral_fsrco_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for GPCRC.
|
||||
extern GPCRC_TypeDef *sl_device_peripheral_gpcrc_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for GPIO.
|
||||
extern GPIO_TypeDef *sl_device_peripheral_gpio_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for HFRCO.
|
||||
extern HFRCO_TypeDef *sl_device_peripheral_hfrco_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for HFXO.
|
||||
extern HFXO_TypeDef *sl_device_peripheral_hfxo_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for HOSTPORTAL.
|
||||
extern HOSTPORTAL_TypeDef *sl_device_peripheral_hostportal_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for HYDRARAM.
|
||||
extern HYDRARAM_TypeDef *sl_device_peripheral_hydraram_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for I2C.
|
||||
extern I2C_TypeDef *sl_device_peripheral_i2c_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for IADC.
|
||||
extern IADC_TypeDef *sl_device_peripheral_iadc_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for ICACHE.
|
||||
extern ICACHE_TypeDef *sl_device_peripheral_icache_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for KEYSCAN.
|
||||
extern KEYSCAN_TypeDef *sl_device_peripheral_keyscan_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for L2CACHE.
|
||||
extern L2CACHE_TypeDef *sl_device_peripheral_l2cache_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for LCD.
|
||||
extern LCD_TypeDef *sl_device_peripheral_lcd_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for LCDRF.
|
||||
extern LCDRF_TypeDef *sl_device_peripheral_lcdrf_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for LDMA.
|
||||
extern LDMA_TypeDef *sl_device_peripheral_ldma_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for LDMAXBAR.
|
||||
extern LDMAXBAR_TypeDef *sl_device_peripheral_ldmaxbar_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for LEDDRV.
|
||||
extern LEDDRV_TypeDef *sl_device_peripheral_leddrv_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for LESENSE.
|
||||
extern LESENSE_TypeDef *sl_device_peripheral_lesense_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for LETIMER.
|
||||
extern LETIMER_TypeDef *sl_device_peripheral_letimer_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for LFRCO.
|
||||
extern LFRCO_TypeDef *sl_device_peripheral_lfrco_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for LFXO.
|
||||
extern LFXO_TypeDef *sl_device_peripheral_lfxo_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for LPWAES.
|
||||
extern LPWAES_TypeDef *sl_device_peripheral_lpwaes_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for LPW0PORTAL.
|
||||
extern LPW0PORTAL_TypeDef *sl_device_peripheral_lpw0portal_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for LVGD.
|
||||
extern LVGD_TypeDef *sl_device_peripheral_lvgd_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for MAILBOX.
|
||||
extern MAILBOX_TypeDef *sl_device_peripheral_mailbox_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for MPAHBRAM.
|
||||
extern MPAHBRAM_TypeDef *sl_device_peripheral_mpahbram_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for MSC.
|
||||
extern MSC_TypeDef *sl_device_peripheral_msc_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for MVP.
|
||||
extern MVP_TypeDef *sl_device_peripheral_mvp_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for PCNT.
|
||||
extern PCNT_TypeDef *sl_device_peripheral_pcnt_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for PDM.
|
||||
extern PDM_TypeDef *sl_device_peripheral_pdm_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for PFMXPPRF.
|
||||
extern PFMXPPRF_TypeDef *sl_device_peripheral_pfmxpprf_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for PIXELRZ.
|
||||
extern PIXELRZ_TypeDef *sl_device_peripheral_pixelrz_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for PRS.
|
||||
extern PRS_TypeDef *sl_device_peripheral_prs_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for RFFPLL.
|
||||
extern RFFPLL_TypeDef *sl_device_peripheral_rffpll_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for RPA.
|
||||
extern RPA_TypeDef *sl_device_peripheral_rpa_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for RTCC.
|
||||
extern RTCC_TypeDef *sl_device_peripheral_rtcc_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for SCRATCHPAD.
|
||||
extern SCRATCHPAD_TypeDef *sl_device_peripheral_scratchpad_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for SEMAILBOX_AHBHOST.
|
||||
extern SEMAILBOX_AHBHOST_TypeDef *sl_device_peripheral_semailbox_ahbhost_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for SEMAILBOX_HOST.
|
||||
extern SEMAILBOX_HOST_TypeDef *sl_device_peripheral_semailbox_host_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for SEMAPHORE.
|
||||
extern SEMAPHORE_TypeDef *sl_device_peripheral_semaphore_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for SEPORTAL.
|
||||
extern SEPORTAL_TypeDef *sl_device_peripheral_seportal_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for SEPUF_APBCFG.
|
||||
extern SEPUF_APBCFG_TypeDef *sl_device_peripheral_sepuf_apbcfg_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for SMU.
|
||||
extern SMU_TypeDef *sl_device_peripheral_smu_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for SOCPLL.
|
||||
extern SOCPLL_TypeDef *sl_device_peripheral_socpll_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for SYMCRYPTO.
|
||||
extern SYMCRYPTO_TypeDef *sl_device_peripheral_symcrypto_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for SYSCFG.
|
||||
extern SYSCFG_TypeDef *sl_device_peripheral_syscfg_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for SYSCFG_CFGNS.
|
||||
extern SYSCFG_CFGNS_TypeDef *sl_device_peripheral_syscfg_cfgns_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for SYSRTC.
|
||||
extern SYSRTC_TypeDef *sl_device_peripheral_sysrtc_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for TIMER.
|
||||
extern TIMER_TypeDef *sl_device_peripheral_timer_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for ULFRCO.
|
||||
extern ULFRCO_TypeDef *sl_device_peripheral_ulfrco_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for USART.
|
||||
extern USART_TypeDef *sl_device_peripheral_usart_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for USBAHB_AHBS.
|
||||
extern USBAHB_AHBS_TypeDef *sl_device_peripheral_usbahb_ahbs_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for USBPLL.
|
||||
extern USBPLL_TypeDef *sl_device_peripheral_usbpll_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for USB_APBS.
|
||||
extern USB_APBS_TypeDef *sl_device_peripheral_usb_apbs_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for VDAC.
|
||||
extern VDAC_TypeDef *sl_device_peripheral_vdac_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External base address getter declaration for WDOG.
|
||||
extern WDOG_TypeDef *sl_device_peripheral_wdog_get_base_addr(const sl_peripheral_t peripheral);
|
||||
|
||||
// External clock branch getter declaration.
|
||||
extern sl_clock_branch_t sl_device_peripheral_get_clock_branch(const sl_peripheral_t peripheral);
|
||||
|
||||
// External bus clock getter declaration.
|
||||
extern sl_bus_clock_t sl_device_peripheral_get_bus_clock(const sl_peripheral_t peripheral);
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
// Disable IAR multiple typedefs declaration warning.
|
||||
#pragma diag_default=Pe301
|
||||
#endif
|
||||
Reference in New Issue
Block a user