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Initial commit of firmware

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GClarkson
2025-04-12 13:30:57 +01:00
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/*
*
* Copyright (c) 2020 Project CHIP Authors
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/***************************************************************************
* # License
*
* The licensor of this software is Silicon Laboratories Inc. Your use of this
* software is governed by the terms of Silicon Labs Master Software License
* Agreement (MSLA) available at
* www.silabs.com/about-us/legal/master-software-license-agreement. This
* software is Third Party Software licensed by Silicon Labs from a third party
* and is governed by the sections of the MSLA applicable to Third Party
* Software and the additional terms set forth below.
*
******************************************************************************/
/*
FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdio.h>
#ifdef SLI_SI91X_MCU_INTERFACE
#include "si91x_device.h"
extern uint32_t SystemCoreClock;
#if SL_ICD_ENABLED
#include "sl_si91x_m4_ps.h"
#endif // SL_ICD_ENABLED
#else // For EFR32
#include "RTE_Components.h"
#include CMSIS_device_header
#include "em_device.h"
//#include "sl_assert.h"
#endif
#if defined(SL_COMPONENT_CATALOG_PRESENT)
#include "sl_component_catalog.h"
#endif
#ifdef SL_CATALOG_SYSTEMVIEW_TRACE_PRESENT
#include "SEGGER_SYSVIEW_FreeRTOS.h"
#endif
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
/* Energy saving modes. */
#if defined(SL_CATALOG_POWER_MANAGER_PRESENT)
#define configUSE_TICKLESS_IDLE 1
#elif (SLI_SI91X_MCU_INTERFACE && SL_ICD_ENABLED)
#define configUSE_TICKLESS_IDLE 1
#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 70
#define configPRE_SLEEP_PROCESSING(x)
#define configPOST_SLEEP_PROCESSING(x)
#define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING(x)
#else
#define configUSE_TICKLESS_IDLE 0
#endif // SL_CATALOG_POWER_MANAGER_PRESENT
#define configTICK_RATE_HZ (1024)
/* Definition used by Keil to replace default system clock source. */
#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 1
/* Hook function related definitions. */
#define configUSE_TICK_HOOK (1)
#define configCHECK_FOR_STACK_OVERFLOW (2)
#define configUSE_MALLOC_FAILED_HOOK (1)
#define configUSE_IDLE_HOOK (1)
/* Main functions*/
/* Run time stats gathering related definitions. */
#define configGENERATE_RUN_TIME_STATS (0)
/* Co-routine related definitions. */
#define configUSE_CO_ROUTINES (0)
#define configMAX_CO_ROUTINE_PRIORITIES (1)
/* Software timer related definitions. */
#define configUSE_TIMERS (1)
// Keep the timerTask at the highest prio as some of our stacks tasks leverage eventing with timers.
#define configTIMER_TASK_PRIORITY (55) /* Highest priority */
#define configTIMER_QUEUE_LENGTH (10)
#define configTIMER_TASK_STACK_DEPTH (1024)
#ifdef SLI_SI91X_MCU_INTERFACE
#ifdef __NVIC_PRIO_BITS
#undef __NVIC_PRIO_BITS
#endif
#define configPRIO_BITS 6 /* 6 priority levels. */
#endif // SLI_SI91X_MCU_INTERFACE
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY (255)
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#ifdef SLI_SI91X_MCU_INTERFACE
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 20
#else
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 48
#endif // SLI_SI91X_MCU_INTERFACE
#define configENABLE_FPU 1
#define configENABLE_MPU 0
/* FreeRTOS Secure Side Only and TrustZone Security Extension */
#ifndef configRUN_FREERTOS_SECURE_ONLY
// prevent redefinition with Series 3
#define configRUN_FREERTOS_SECURE_ONLY 1
#endif
#define configENABLE_TRUSTZONE 0
/* FreeRTOS MPU specific definitions. */
#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0)
#define configCPU_CLOCK_HZ (SystemCoreClock)
#define configUSE_PREEMPTION (1)
#define configUSE_TIME_SLICING (1)
#define configUSE_PORT_OPTIMISED_TASK_SELECTION (0)
#define configUSE_TICKLESS_IDLE_SIMPLE_DEBUG (1) /* See into vPortSuppressTicksAndSleep source code for explanation */
#define configMAX_PRIORITIES (56)
#define configMINIMAL_STACK_SIZE (320) /* Number of words to use for Idle and Timer stacks */
#ifdef HEAP_MONITORING
#define configMAX_TASK_NAME_LEN (24)
#else
#define configMAX_TASK_NAME_LEN (10)
#endif // HEAP_MONITORING
#define configUSE_16_BIT_TICKS (0)
#define configIDLE_SHOULD_YIELD (1)
#define configUSE_MUTEXES (1)
#define configUSE_RECURSIVE_MUTEXES (1)
#define configUSE_COUNTING_SEMAPHORES (1)
#define configUSE_TASK_NOTIFICATIONS 1
#define configUSE_TRACE_FACILITY 1
#define configQUEUE_REGISTRY_SIZE (10)
#define configUSE_QUEUE_SETS (0)
#define configUSE_NEWLIB_REENTRANT (0)
#define configENABLE_BACKWARD_COMPATIBILITY (1)
#define configSUPPORT_STATIC_ALLOCATION (1)
#define configSUPPORT_DYNAMIC_ALLOCATION (1)
#ifdef PW_RPC_ENABLED
#define EXTRA_HEAP_k 10
#else
#define EXTRA_HEAP_k 0
#endif
#ifndef configTOTAL_HEAP_SIZE
#ifdef SL_WIFI
#ifdef DIC_ENABLE
#ifdef SLI_SI91X_MCU_INTERFACE
#define configTOTAL_HEAP_SIZE ((size_t) ((75 + EXTRA_HEAP_k) * 1024))
#else
#define configTOTAL_HEAP_SIZE ((size_t) ((68 + EXTRA_HEAP_k) * 1024))
#endif // SLI_SI91X_MCU_INTERFACE
#else
#define configTOTAL_HEAP_SIZE ((size_t) ((42 + EXTRA_HEAP_k) * 1024))
#endif // DIC
#else // SL_WIFI
#if SL_CONFIG_OPENTHREAD_LIB == 1
#define configTOTAL_HEAP_SIZE ((size_t) ((40 + EXTRA_HEAP_k) * 1024))
#else
#define configTOTAL_HEAP_SIZE ((size_t) ((38 + EXTRA_HEAP_k) * 1024))
#endif // SL_CONFIG_OPENTHREAD_LIB
#endif // configTOTAL_HEAP_SIZE
#endif // configTOTAL_HEAP_SIZE
/* Optional functions - most linkers will remove unused functions anyway. */
#define INCLUDE_vTaskPrioritySet (1)
#define INCLUDE_uxTaskPriorityGet (1)
#define INCLUDE_vTaskDelete (1)
#define INCLUDE_vTaskSuspend (1)
#define INCLUDE_xResumeFromISR (1)
#define INCLUDE_vTaskDelayUntil (1)
#define INCLUDE_vTaskDelay (1)
#define INCLUDE_xTaskGetSchedulerState (1)
#define INCLUDE_xTaskGetCurrentTaskHandle (1)
#define INCLUDE_uxTaskGetStackHighWaterMark (1)
#define INCLUDE_xTaskGetIdleTaskHandle (1)
#define INCLUDE_xTimerGetTimerDaemonTaskHandle (1)
#define INCLUDE_pcTaskGetTaskName (1)
#define INCLUDE_eTaskGetState (1)
#define INCLUDE_xEventGroupSetBitFromISR (1)
#define INCLUDE_xEventGroupSetBitsFromISR (1)
#define INCLUDE_xSemaphoreGetMutexHolder (1)
#define INCLUDE_xTimerPendFunctionCall (1)
#define INCLUDE_xTaskGetHandle (1)
/* Stop if an assertion fails. */
#define configASSERT(x) \
if ((x) == 0) \
{ \
taskDISABLE_INTERRUPTS(); \
printf("\nFREERTOS ASSERT ( %s )\n", #x); \
for (;;) \
; \
}
#define configASSERTNULL(x) \
if ((x) == NULL) \
{ \
taskDISABLE_INTERRUPTS(); \
for (;;) \
; \
}
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
/* Ensure Cortex-M port compatibility. */
#define SysTick_Handler xPortSysTickHandler
/* Thread local storage pointers used by the SDK */
#ifndef configNUM_USER_THREAD_LOCAL_STORAGE_POINTERS
#define configNUM_USER_THREAD_LOCAL_STORAGE_POINTERS 0
#endif
#ifndef configNUM_SDK_THREAD_LOCAL_STORAGE_POINTERS
#define configNUM_SDK_THREAD_LOCAL_STORAGE_POINTERS 2
#endif
#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS
#define configNUM_THREAD_LOCAL_STORAGE_POINTERS \
(configNUM_USER_THREAD_LOCAL_STORAGE_POINTERS + configNUM_SDK_THREAD_LOCAL_STORAGE_POINTERS + 1)
#endif
#if defined(__GNUC__)
/* For the linker. */
#define fabs __builtin_fabs
#endif
#ifndef configNUM_USER_THREAD_LOCAL_STORAGE_POINTERS
#error RC-FRTOS
#endif
#ifdef __cplusplus
}
#endif

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/***************************************************************************//**
* @file
* @brief emlib_core Configuration
*******************************************************************************
* # License
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#ifndef EM_CORE_DEBUG_CONFIG_H
#define EM_CORE_DEBUG_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Core Configuration
// <q SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING> Enables measuring of interrupt disable time for debugging purposes.
// <i> Default: 0
#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0
// </h>
// <<< end of configuration section >>>
#endif // EM_CORE_CONFIG_H

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/***************************************************************************//**
* @file
* @brief Clock Manager - Oscillators configuration file.
*******************************************************************************
* # License
* <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H
#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H
#if defined(SL_COMPONENT_CATALOG_PRESENT)
#include "sl_component_catalog.h"
#endif
// Internal Defines: DO NOT MODIFY
#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1
#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0
#if defined(SL_CATALOG_RAIL_LIB_PRESENT)
#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE
#else
#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE
#endif
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Oscillators Settings
// <h> HFXO Settings (if High Frequency crystal is used)
// <o SL_CLOCK_MANAGER_HFXO_EN> Enable
// <i> Enable to configure HFXO
// <i> AUTO enables HFXO if a radio is used
// <SL_CLOCK_MANAGER_HFXO_EN_AUTO=> AUTO
// <SL_CLOCK_MANAGER_HFXO_EN_ENABLE=> ENABLE
// <SL_CLOCK_MANAGER_HFXO_EN_DISABLE=> DISABLE
// <d> SL_CLOCK_MANAGER_HFXO_EN_AUTO
#ifndef SL_CLOCK_MANAGER_HFXO_EN
#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE
#endif
// <o SL_CLOCK_MANAGER_HFXO_MODE> Mode
// <i>
// <HFXO_CFG_MODE_XTAL=> XTAL
// <HFXO_CFG_MODE_EXTCLK=> EXTCLK
// <HFXO_CFG_MODE_EXTCLKPKDET=> EXTCLKPKDET
// <d> HFXO_CFG_MODE_XTAL
#ifndef SL_CLOCK_MANAGER_HFXO_MODE
#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL
#endif
// <o SL_CLOCK_MANAGER_HFXO_FREQ> Frequency in Hz <38000000-40000000>
// <d> 39000000
#ifndef SL_CLOCK_MANAGER_HFXO_FREQ
#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000
#endif
// <o SL_CLOCK_MANAGER_HFXO_CTUNE> CTUNE <0-255>
// <d> 140
#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE
#define SL_CLOCK_MANAGER_HFXO_CTUNE 140
#endif
// <o SL_CLOCK_MANAGER_HFXO_PRECISION> Precision in PPM <0-65535>
// <d> 50
#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION
#define SL_CLOCK_MANAGER_HFXO_PRECISION 50
#endif
// <q SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN> CTUNE HXFO manufacturing
// <i> Enable to use CTUNE HFXO manufacturing value for calibration
// <d> 1
#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN
#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1
#endif
// <e SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN> HFXO crystal sharing feature
// <i> Enable to configure HFXO crystal sharing leader or follower
#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN
#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0
#endif
// <e SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN> Crystal sharing leader
// <i> Enable to configure HFXO crystal sharing leader
#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN
#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0
#endif
// <e SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN> Crystal sharing leader minimum startup delay
// <i> If enabled, BUFOUT does not start until timeout set in
// <i> SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires.
// <i> This prevents waste of power if BUFOUT is ready too early.
// <d> 1
#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN
#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1
#endif
// <o SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP> Wait duration of oscillator startup sequence
// <i>
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US=> T42US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US=> T83US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US=> T108US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US=> T133US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US=> T158US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US=> T183US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US=> T208US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US=> T233US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US=> T258US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US=> T283US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US=> T333US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US=> T375US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US=> T417US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US=> T458US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US=> T500US
// <HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US=> T667US
// <d> HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US
#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP
#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US
#endif
// </e>
// </e>
// <e SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN> Crystal sharing follower
// <i> Enable to configure HFXO crystal sharing follower
#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN
#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0
#endif
// </e>
// <o SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT> GPIO Port
// <i> Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN
// <i> is enabled, this port will be used to receive the BUFOUT request. If
// <i> SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port
// <i> will be used to request BUFOUT from the crystal sharing leader.
#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT
#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0
#endif
// <o SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN> GPIO Pin
// <i> Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN
// <i> is enabled, this pin will be used to receive the BUFOUT request. If
// <i> SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin
// <i> will be used to request BUFOUT from the crystal sharing leader.
#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN
#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10
#endif
// </e>
// </h>
// <e> LFXO Settings (if Low Frequency crystal is used)
// <i> Enable to configure LFXO
#ifndef SL_CLOCK_MANAGER_LFXO_EN
#define SL_CLOCK_MANAGER_LFXO_EN 1
#endif
// <o SL_CLOCK_MANAGER_LFXO_MODE> Mode
// <i>
// <LFXO_CFG_MODE_XTAL=> XTAL
// <LFXO_CFG_MODE_BUFEXTCLK=> BUFEXTCLK
// <LFXO_CFG_MODE_DIGEXTCLK=> DIGEXTCLK
// <d> LFXO_CFG_MODE_XTAL
#ifndef SL_CLOCK_MANAGER_LFXO_MODE
#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL
#endif
// <o SL_CLOCK_MANAGER_LFXO_CTUNE> CTUNE <0-127>
// <d> 63
#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE
#define SL_CLOCK_MANAGER_LFXO_CTUNE 63
#endif
// <o SL_CLOCK_MANAGER_LFXO_PRECISION> LFXO precision in PPM <0-65535>
// <d> 50
#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION
#define SL_CLOCK_MANAGER_LFXO_PRECISION 50
#endif
// <o SL_CLOCK_MANAGER_LFXO_TIMEOUT> Startup Timeout Delay
// <i>
// <LFXO_CFG_TIMEOUT_CYCLES2=> CYCLES2
// <LFXO_CFG_TIMEOUT_CYCLES256=> CYCLES256
// <LFXO_CFG_TIMEOUT_CYCLES1K=> CYCLES1K
// <LFXO_CFG_TIMEOUT_CYCLES2K=> CYCLES2K
// <LFXO_CFG_TIMEOUT_CYCLES4K=> CYCLES4K
// <LFXO_CFG_TIMEOUT_CYCLES8K=> CYCLES8K
// <LFXO_CFG_TIMEOUT_CYCLES16K=> CYCLES16K
// <LFXO_CFG_TIMEOUT_CYCLES32K=> CYCLES32K
// <d> LFXO_CFG_TIMEOUT_CYCLES4K
#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT
#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K
#endif
// <q SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN> CTUNE LXFO manufacturing
// <i> Enable to use CTUNE LFXO manufacturing value for calibration
// <d> 1
#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN
#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1
#endif
// </e>
// <h> HFRCO and DPLL Settings
// <o SL_CLOCK_MANAGER_HFRCO_BAND> Frequency Band
// <i> RC Oscillator Frequency Band
// <cmuHFRCODPLLFreq_1M0Hz=> 1 MHz
// <cmuHFRCODPLLFreq_2M0Hz=> 2 MHz
// <cmuHFRCODPLLFreq_4M0Hz=> 4 MHz
// <cmuHFRCODPLLFreq_7M0Hz=> 7 MHz
// <cmuHFRCODPLLFreq_13M0Hz=> 13 MHz
// <cmuHFRCODPLLFreq_16M0Hz=> 16 MHz
// <cmuHFRCODPLLFreq_19M0Hz=> 19 MHz
// <cmuHFRCODPLLFreq_26M0Hz=> 26 MHz
// <cmuHFRCODPLLFreq_32M0Hz=> 32 MHz
// <cmuHFRCODPLLFreq_38M0Hz=> 38 MHz
// <cmuHFRCODPLLFreq_48M0Hz=> 48 MHz
// <cmuHFRCODPLLFreq_56M0Hz=> 56 MHz
// <cmuHFRCODPLLFreq_64M0Hz=> 64 MHz
// <cmuHFRCODPLLFreq_80M0Hz=> 80 MHz
// <d> cmuHFRCODPLLFreq_80M0Hz
#ifndef SL_CLOCK_MANAGER_HFRCO_BAND
#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz
#endif
// <e> Use DPLL
// <i> Enable to use the DPLL with HFRCO
#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN
#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0
#endif
// <o SL_CLOCK_MANAGER_DPLL_FREQ> Target Frequency in Hz <1000000-80000000>
// <i> DPLL target frequency
// <d> 78000000
#ifndef SL_CLOCK_MANAGER_DPLL_FREQ
#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000
#endif
// <o SL_CLOCK_MANAGER_DPLL_N> Numerator (N) <300-4095>
// <i> Value of N for output frequency calculation fout = fref * (N+1) / (M+1)
// <d> 3839
#ifndef SL_CLOCK_MANAGER_DPLL_N
#define SL_CLOCK_MANAGER_DPLL_N 3839
#endif
// <o SL_CLOCK_MANAGER_DPLL_M> Denominator (M) <0-4095>
// <i> Value of M for output frequency calculation fout = fref * (N+1) / (M+1)
// <d> 1919
#ifndef SL_CLOCK_MANAGER_DPLL_M
#define SL_CLOCK_MANAGER_DPLL_M 1919
#endif
// <o SL_CLOCK_MANAGER_DPLL_REFCLK> Reference Clock
// <i> Reference clock source for DPLL
// <CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED=> DISABLED
// <CMU_DPLLREFCLKCTRL_CLKSEL_HFXO=> HFXO
// <CMU_DPLLREFCLKCTRL_CLKSEL_LFXO=> LFXO
// <CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0=> CLKIN0
// <d> CMU_DPLLREFCLKCTRL_CLKSEL_HFXO
#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK
#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO
#endif
// <o SL_CLOCK_MANAGER_DPLL_EDGE> Reference Clock Edge Detect
// <i> Edge detection for reference clock
// <cmuDPLLEdgeSel_Fall=> Falling Edge
// <cmuDPLLEdgeSel_Rise=> Rising Edge
// <d> cmuDPLLEdgeSel_Fall
#ifndef SL_CLOCK_MANAGER_DPLL_EDGE
#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall
#endif
// <o SL_CLOCK_MANAGER_DPLL_LOCKMODE> DPLL Lock Mode
// <i> Lock mode
// <cmuDPLLLockMode_Freq=> Frequency-Lock Loop
// <cmuDPLLLockMode_Phase=> Phase-Lock Loop
// <d> cmuDPLLLockMode_Freq
#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE
#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase
#endif
// <q SL_CLOCK_MANAGER_DPLL_AUTORECOVER> Automatic Lock Recovery
// <d> 1
#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER
#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1
#endif
// <q SL_CLOCK_MANAGER_DPLL_DITHER> Enable Dither
// <d> 0
#ifndef SL_CLOCK_MANAGER_DPLL_DITHER
#define SL_CLOCK_MANAGER_DPLL_DITHER 0
#endif
// </e>
// </h>
// <h> HFRCOEM23 Settings
// <o SL_CLOCK_MANAGER_HFRCOEM23_BAND> Frequency Band
// <i> RC Oscillator Frequency Band
// <cmuHFRCOEM23Freq_1M0Hz=> 1 MHz
// <cmuHFRCOEM23Freq_2M0Hz=> 2 MHz
// <cmuHFRCOEM23Freq_4M0Hz=> 4 MHz
// <cmuHFRCOEM23Freq_13M0Hz=> 13 MHz
// <cmuHFRCOEM23Freq_16M0Hz=> 16 MHz
// <cmuHFRCOEM23Freq_19M0Hz=> 19 MHz
// <cmuHFRCOEM23Freq_26M0Hz=> 26 MHz
// <cmuHFRCOEM23Freq_32M0Hz=> 32 MHz
// <cmuHFRCOEM23Freq_40M0Hz=> 40 MHz
// <d> cmuHFRCOEM23Freq_19M0Hz
#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND
#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz
#endif
// </h>
// <h> LFRCO Settings
// <o SL_CLOCK_MANAGER_LFRCO_PRECISION> Precision Mode
// <i> Precision mode uses hardware to automatically re-calibrate the LFRCO
// <i> against a crystal driven by the HFXO. Hardware detects temperature
// <i> changes and initiates a re-calibration of the LFRCO as needed when
// <i> operating in EM0, EM1, or EM2. If a re-calibration is necessary and the
// <i> HFXO is not active, the precision mode hardware will automatically
// <i> enable HFXO for a short time to perform the calibration. EM4 operation is
// <i> not allowed while precision mode is enabled.
// <i> If high precision is selected on devices that do not support it, default
// <i> precision will be used.
// <cmuPrecisionDefault=> Default precision
// <cmuPrecisionHigh=> High precision
// <d> cmuPrecisionDefault
#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION
#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault
#endif
// </h>
// <h> CLKIN0 Settings
// <o SL_CLOCK_MANAGER_CLKIN0_FREQ> Frequency in Hz <1000000-38000000>
// <d> 38000000
#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ
#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000
#endif
// </h>
// </h>
// <<< end of configuration section >>>
// <<< sl:start pin_tool >>>
// <cmu signal=CLKIN0> SL_CLOCK_MANAGER_CLKIN0
// $[CMU_SL_CLOCK_MANAGER_CLKIN0]
// [CMU_SL_CLOCK_MANAGER_CLKIN0]$
// <<< sl:end pin_tool >>>
#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */

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/***************************************************************************//**
* @file
* @brief Clock Manager - Clock Tree configuration file.
*******************************************************************************
* # License
* <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H
#define SL_CLOCK_MANAGER_TREE_CONFIG_H
#if defined(SL_COMPONENT_CATALOG_PRESENT)
#include "sl_component_catalog.h"
#endif
// Internal Defines: DO NOT MODIFY
// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE
// selection of each clock branch to the right HW register value.
#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF
#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE
#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD
#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC
#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB
#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA
#if defined(SL_CATALOG_RAIL_LIB_PRESENT)
#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO
#else
#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL
#endif
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Clock Tree Settings
// <o SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE> Default Clock Source Selection for HF clock branches
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO=> AUTO
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL=> HFRCODPLL
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO=> HFXO
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO=> FSRCO
// <i> Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value.
// <i> AUTO uses HFXO if a radio is used and HFRCODPLL otherwise
// <d> SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO
#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO
#endif
// <o SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE> Default Clock Source Selection for LF clock branches
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO=> LFRCO
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO=> LFXO
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO=> ULFRCO
// <i> Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value.
// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO
#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO
#endif
// <h> System Clock Branch Settings
// <o SL_CLOCK_MANAGER_SYSCLK_SOURCE> Clock Source Selection for SYSCLK branch
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE=> DEFAULT_HF
// <CMU_SYSCLKCTRL_CLKSEL_FSRCO=> FSRCO
// <CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL=> HFRCODPLL
// <CMU_SYSCLKCTRL_CLKSEL_HFXO=> HFXO
// <CMU_SYSCLKCTRL_CLKSEL_CLKIN0=> CLKIN0
// <i> Selection of the Clock source for SYSCLK
// <d> SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE
#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_HCLK_DIVIDER> HCLK branch divider
// <CMU_SYSCLKCTRL_HCLKPRESC_DIV1=> DIV1
// <CMU_SYSCLKCTRL_HCLKPRESC_DIV2=> DIV2
// <CMU_SYSCLKCTRL_HCLKPRESC_DIV4=> DIV4
// <CMU_SYSCLKCTRL_HCLKPRESC_DIV8=> DIV8
// <CMU_SYSCLKCTRL_HCLKPRESC_DIV16=> DIV16
// <i> HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface.
// <d> CMU_SYSCLKCTRL_HCLKPRESC_DIV1
#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER
#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1
#endif
// <o SL_CLOCK_MANAGER_PCLK_DIVIDER> PCLK branch divider
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV1=> DIV1
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV2=> DIV2
// <i> PCLK branch is derived from HCLK. This clock drives the APB bus interface.
// <d> CMU_SYSCLKCTRL_PCLKPRESC_DIV1
#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER
#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1
#endif
// </h>
// <h> Trace Clock Branches Settings
// <o SL_CLOCK_MANAGER_TRACECLK_SOURCE> Clock Source Selection for TRACECLK branch
// <CMU_TRACECLKCTRL_CLKSEL_DISABLE=> DISABLE
// <CMU_TRACECLKCTRL_CLKSEL_SYSCLK=> SYSCLK
// <CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
// <CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT=> HFRCODPLLRT
// <i> Selection of the Clock source for TRACECLK
// <d> CMU_TRACECLKCTRL_CLKSEL_SYSCLK
#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE
#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK
#endif
// <o SL_CLOCK_MANAGER_TRACECLK_DIVIDER> TRACECLK branch Divider
// <CMU_TRACECLKCTRL_PRESC_DIV1=> DIV1
// <CMU_TRACECLKCTRL_PRESC_DIV2=> DIV2
// <CMU_TRACECLKCTRL_PRESC_DIV3=> DIV3
// <CMU_TRACECLKCTRL_PRESC_DIV4=> DIV4
// <i> Selection of the divider value for TRACECLK branch
// <d> CMU_TRACECLKCTRL_PRESC_DIV1
#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER
#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1
#endif
// </h>
// <h> High Frequency Clock Branches Settings
// <i> Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible
// <i> EM01GRPACLK clock the Timer peripherals
// <o SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE> Clock Source Selection for EM01GRPACLK branch
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE=> DEFAULT_HF
// <CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL=> HFRCODPLL
// <CMU_EM01GRPACLKCTRL_CLKSEL_HFXO=> HFXO
// <CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO=> FSRCO
// <CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
// <CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT=> HFRCODPLLRT
// <CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT=> HFXORT
// <i> Selection of the Clock source for EM01GRPACLK
// <d> SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE
#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE> Clock Source Selection for EM01GRPCCLK branch
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE=> DEFAULT_HF
// <CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL=> HFRCODPLL
// <CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO=> HFXO
// <CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO=> FSRCO
// <CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
// <CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT=> HFRCODPLLRT
// <CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT=> HFXORT
// <i> Selection of the Clock source for EM01GRPCCLK
// <d> SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE
#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_IADCCLK_SOURCE> Clock Source Selection for IADCCLK branch
// <CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK=> EM01GRPACLK
// <CMU_IADCCLKCTRL_CLKSEL_FSRCO=> FSRCO
// <CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
// <i> Selection of the Clock source for IADCCLK
// <d> CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE
#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
#endif
// </h>
// <h> Low Frequency Clock Branches Settings
// <o SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE> Clock Source Selection for EM23GRPACLK branch
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
// <CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO=> LFRCO
// <CMU_EM23GRPACLKCTRL_CLKSEL_LFXO=> LFXO
// <CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO=> ULFRCO
// <i> Selection of the Clock source for EM23GRPACLK
// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE
#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE> Clock Source Selection for EM4GRPACLK branch
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
// <CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO=> LFRCO
// <CMU_EM4GRPACLKCTRL_CLKSEL_LFXO=> LFXO
// <CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO=> ULFRCO
// <i> Selection of the Clock source for EM4GRPACLK
// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE
#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE> Clock Source Selection for SYSRTCCLK branch
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
// <CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO=> LFRCO
// <CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO=> LFXO
// <CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO=> ULFRCO
// <i> Selection of the Clock source for SYSRTCCLK
// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE
#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_WDOG0CLK_SOURCE> Clock Source Selection for WDOG0CLK branch
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
// <CMU_WDOG0CLKCTRL_CLKSEL_LFRCO=> LFRCO
// <CMU_WDOG0CLKCTRL_CLKSEL_LFXO=> LFXO
// <CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO=> ULFRCO
// <CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024=> HCLKDIV1024
// <i> Selection of the Clock source for WDOG0CLK
// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE
#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_WDOG1CLK_SOURCE> Clock Source Selection for WDOG1CLK branch
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
// <CMU_WDOG1CLKCTRL_CLKSEL_LFRCO=> LFRCO
// <CMU_WDOG1CLKCTRL_CLKSEL_LFXO=> LFXO
// <CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO=> ULFRCO
// <CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024=> HCLKDIV1024
// <i> Selection of the Clock source for WDOG1CLK
// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE
#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_PCNT0CLK_SOURCE> Clock Source Selection for PCNT0CLK branch
// <CMU_PCNT0CLKCTRL_CLKSEL_DISABLED=> DISABLED
// <CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK=> EM23GRPACLK
// <CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0=> PCNTS0
// <i> Selection of the Clock source for PCNT0CLK
// <d> CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK
#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE
#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK
#endif
// </h>
// <h> Mixed Frequency Clock Branch Settings
// <o SL_CLOCK_MANAGER_EUSART0CLK_SOURCE> Clock Source Selection for EUSART0CLK branch
// <CMU_EUSART0CLKCTRL_CLKSEL_DISABLED=> DISABLED
// <CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK=> EM01GRPCCLK
// <CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
// <CMU_EUSART0CLKCTRL_CLKSEL_LFRCO=> LFRCO
// <CMU_EUSART0CLKCTRL_CLKSEL_LFXO=> LFXO
// <i> Selection of the Clock source for EUSART0CLK
// <d> CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK
#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE
#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK
#endif
// <o SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE> Clock Source Selection for SYSTICKCLK branch
// <0=> HCLK
// <1=> EM23GRPACLK
// <i> Selection of the Clock source for SYSTICKCLK
// <d> 0
#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE
#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0
#endif
// <o SL_CLOCK_MANAGER_VDAC0CLK_SOURCE> Clock Source Selection for VDAC0CLK branch
// <CMU_VDAC0CLKCTRL_CLKSEL_DISABLED=> DISABLED
// <CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK=> EM01GRPACLK
// <CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK=> EM23GRPACLK
// <CMU_VDAC0CLKCTRL_CLKSEL_FSRCO=> FSRCO
// <CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
// <i> Selection of the Clock source for VDAC0CLK
// <d> CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK
#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE
#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK
#endif
// <o SL_CLOCK_MANAGER_VDAC1CLK_SOURCE> Clock Source Selection for VDAC1CLK branch
// <CMU_VDAC1CLKCTRL_CLKSEL_DISABLED=> DISABLED
// <CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK=> EM01GRPACLK
// <CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK=> EM23GRPACLK
// <CMU_VDAC1CLKCTRL_CLKSEL_FSRCO=> FSRCO
// <CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
// <i> Selection of the Clock source for VDAC1CLK
// <d> CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK
#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE
#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK
#endif
// </h>
// </h>
#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */
// <<< end of configuration section >>>

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/***************************************************************************//**
* @file
* @brief sl_core Configuration
*******************************************************************************
* # License
* <b>Copyright 2023 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#ifndef SL_CORE_CONFIG_H
#define SL_CORE_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Core Abstraction Configuration
// <q SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING> Enables measurement of interrupt masking time for debugging purposes.
// <i> Default: 0
#define SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING 0
// </h>
// <<< end of configuration section >>>
#endif // SL_CORE_CONFIG_H

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/***************************************************************************//**
* @file
* @brief DEVICE_INIT_DCDC Config
*******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H
#define SL_DEVICE_INIT_DCDC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <q SL_DEVICE_INIT_DCDC_ENABLE> Enable DC/DC Converter
// <i>
// <i> Default: 1
#define SL_DEVICE_INIT_DCDC_ENABLE 1
// <q SL_DEVICE_INIT_DCDC_BYPASS> Set DC/DC Converter in Bypass Mode
// <i>
// <i> Default: 0
#define SL_DEVICE_INIT_DCDC_BYPASS 0
// <q SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE> Override for DCDC PFMX Mode Peak Current Setting
// <i>
// <i> Default: 1
#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1
// <o SL_DEVICE_INIT_DCDC_PFMX_IPKVAL> DCDC PFMX Mode Peak Current Setting <0-15>
// <i>
// <i> Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT
#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 12
// <<< end of configuration section >>>
#endif // SL_DEVICE_INIT_DCDC_CONFIG_H

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/***************************************************************************//**
* @file
* @brief HFXO Manager configuration file.
*******************************************************************************
* # License
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef SL_HFXO_MANAGER_CONFIG_H
#define SL_HFXO_MANAGER_CONFIG_H
// <h>HFXO Manager Configuration
// <q SL_HFXO_MANAGER_CUSTOM_HFXO_IRQ_HANDLER> Enable custom IRQ handler for crystal HF oscillator.
// <i> Enable if HFXO0_IRQHandler is needed from your application.
// <i> The HFXO IRQ priority must not be changed as the HFXO Manager module needs it to be high priority
// <i> and to stay enabled through atomic sections.
// <i> The function sl_hfxo_manager_irq_handler() will have to be called from you custom handler if this is enabled.
// <i> Default: 0
#define SL_HFXO_MANAGER_CUSTOM_HFXO_IRQ_HANDLER 0
// <q SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT> Enable support for Sleepy Crystals.
// <i> If Enabled and if HFXO fails to startup due to a sleepy crystal, HFXO Manager will retry the startup with more aggressive settings
// <i> before falling back to the configured settings.
// <i> Default: 0
#define SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT 0
// </h>
#endif /* SL_HFXO_MANAGER_CONFIG_H */
// <<< end of configuration section >>>

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/***************************************************************************//**
* @file
* @brief Interrupt Manager configuration file for series 2 devices.
*******************************************************************************
* # License
* <b>Copyright 2023 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef SL_INTERRUPT_MANAGER_S2_CONFIG_H
#define SL_INTERRUPT_MANAGER_S2_CONFIG_H
// <h>Interrupt Manager Configuration
// <q SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM> Put the interrupt vector table in RAM.
// <i> Set to 1 to put the vector table in RAM.
// <i> Default: 0
#define SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM 0
// </h>
#endif /* SSL_INTERRUPT_MANAGER_S2_CONFIG_H */
// <<< end of configuration section >>>

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/***************************************************************************//**
* @file
* @brief Memory Heap Allocator configuration file.
*******************************************************************************
* # License
* <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef SL_MEMORY_MANAGER_CONFIG_H
#define SL_MEMORY_MANAGER_CONFIG_H
// <h> Memory Manager Configuration
// <o SL_MEMORY_MANAGER_BLOCK_ALLOCATION_MIN_SIZE> Minimum block allocation size
// <32-128:8>
// <i> Minimum block allocation size to avoid creating a block too small while splitting up an allocated block.
// <i> Size expressed in bytes and can only be a multiple of 8 bytes for the proper data alignment management done by the dynamic allocator malloc() function.
// <i> Default: 32
#define SL_MEMORY_MANAGER_BLOCK_ALLOCATION_MIN_SIZE (32)
// </h>
// <<< end of configuration section >>>
#endif /* SL_MEMORY_MANAGER_CONFIG_H */

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/***************************************************************************//**
* @file
* @brief Memory Heap and stack size configuration file.
*******************************************************************************
* # License
* <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef SL_MEMORY_MANAGER_REGION_CONFIG_H
#define SL_MEMORY_MANAGER_REGION_CONFIG_H
// <h> Memory configuration
// <o SL_STACK_SIZE> Stack size for the application.
// <i> Default: 4096
// <i> The stack size configured here will be used by the stack that the
// <i> application uses when coming out of a reset.
#ifndef SL_STACK_SIZE
#define SL_STACK_SIZE 4608
#endif
// </h>
// <<< end of configuration section >>>
#endif /* SL_MEMORY_MANAGER_REGION_CONFIG_H */

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/***************************************************************************//**
* @file
* @brief Power Manager configuration file.
*******************************************************************************
* # License
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef SL_POWER_MANAGER_CONFIG_H
#define SL_POWER_MANAGER_CONFIG_H
// <h>Power Manager Configuration
// <q SL_POWER_MANAGER_CUSTOM_HF_OSCILLATOR_IRQ_HANDLER> Enable custom IRQ handler for external HF oscillator.
// <i> Enable if CMU_IRQHandler/HFXO0_IRQHandler is needed from your application.
// <i> The function sl_power_manager_irq_handler() will have to be called from you custom handler if this is enabled.
// <i> Default: 0
#define SL_POWER_MANAGER_CUSTOM_HF_OSCILLATOR_IRQ_HANDLER 0
// <q SL_POWER_MANAGER_CONFIG_VOLTAGE_SCALING_FAST_WAKEUP> Enable fast wakeup (disable voltage scaling in EM2/3 mode)
// <i> Enable or disable voltage scaling in EM2/3 modes (when available). This decreases wakeup time by about 30 us.
// <i> Deprecated. It is replaced by the function sl_power_manager_em23_voltage_scaling_enable_fast_wakeup()
// <i> Default: 0
#define SL_POWER_MANAGER_CONFIG_VOLTAGE_SCALING_FAST_WAKEUP 0
// <e SL_POWER_MANAGER_DEBUG> Enable debugging feature
// <i> Enable or disable debugging features (trace the different modules that have requirements).
// <i> Default: 0
#define SL_POWER_MANAGER_DEBUG 0
// <o SL_POWER_MANAGER_DEBUG_POOL_SIZE> Maximum numbers of requirements that can be logged
// <i> Default: 10
#define SL_POWER_MANAGER_DEBUG_POOL_SIZE 10
// </e>
// <o SL_POWER_MANAGER_INIT_EMU_EM4_PIN_RETENTION_MODE> Pin retention mode
// <i>
// <EMU_EM4CTRL_EM4IORETMODE_DISABLE=> No retention
// <EMU_EM4CTRL_EM4IORETMODE_EM4EXIT=> Retention through EM4
// <EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH=> Retention through EM4 and wakeup
// <d> power_manager_pin_retention_disable
#define SL_POWER_MANAGER_INIT_EMU_EM4_PIN_RETENTION_MODE EMU_EM4CTRL_EM4IORETMODE_DISABLE
// <e SL_POWER_MANAGER_INIT_EMU_EM2_DEBUG_ENABLE > Enable EM2 debugging feature
// <i> Enable or disable debugging features.
// <i> Default: 1
#define SL_POWER_MANAGER_INIT_EMU_EM2_DEBUG_ENABLE 1
// </e>
// </h>
#endif /* SL_POWER_MANAGER_CONFIG_H */
// <<< end of configuration section >>>

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/***************************************************************************//**
* @file
* @brief Simple Button Driver Configuration
*******************************************************************************
* # License
* <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#ifndef SL_SIMPLE_BUTTON_CONFIG_H
#define SL_SIMPLE_BUTTON_CONFIG_H
#include "sl_gpio.h"
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Simple Button Driver Configuration
// <o SL_SIMPLE_BUTTON_DEBOUNCE_BITS> Number of bits <1-15>
// <i> Default: 5
// <i> Defines the number of calls to sl_simple_button_poll_step wherein the button
// <i> state must remain the same before the button state is considered debounced
#define SL_SIMPLE_BUTTON_DEBOUNCE_BITS 5U
// <o SL_SIMPLE_BUTTON_GPIO_MODE>
// <SL_GPIO_MODE_INPUT=> GPIO Input
// <SL_GPIO_MODE_INPUT_PULL=> GPIO Input Pull
// <SL_GPIO_MODE_INPUT_PULL_FILTER=> GPIO Input Pull Filter
// <i> Default: gpioModeInput
#define SL_SIMPLE_BUTTON_GPIO_MODE SL_GPIO_MODE_INPUT
// <q SL_SIMPLE_BUTTON_GPIO_DOUT>
// <i> SL_SIMPLE_BUTTON_GPIO_MODE == SL_GPIO_MODE_INPUT, Filter if DOUT is set
// <i> SL_SIMPLE_BUTTON_GPIO_MODE == SL_GPIO_MODE_INPUT_PULL, DOUT determines pull direction
#define SL_SIMPLE_BUTTON_GPIO_DOUT 0U
// <q SL_SIMPLE_BUTTON_POLARITY>
// <i> 0 Active Low
// <i> 1 Active High
// <i> Default: 0
#define SL_SIMPLE_BUTTON_POLARITY 0U
// <q SL_SIMPLE_BUTTON_ALLOW_LED_CONFLICT> Allow the app to manage Buttons and LEDs on the same pin
// <i> 0 Error if Buttons and LEDs are on the same pin
// <i> 1 Do not error if Buttons and LEDs are on the same pin
// <i> Default: 0
#define SL_SIMPLE_BUTTON_ALLOW_LED_CONFLICT 0U
// </h>
// <<< end of configuration section >>>
#endif // SL_SIMPLE_BUTTON_CONFIG_H

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/***************************************************************************//**
* @file
* @brief Sleep Timer configuration file.
*******************************************************************************
* # License
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef SL_SLEEPTIMER_CONFIG_H
#define SL_SLEEPTIMER_CONFIG_H
#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0
#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1
#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2
#define SL_SLEEPTIMER_PERIPHERAL_RTC 3
#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4
#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5
#define SL_SLEEPTIMER_PERIPHERAL_WTIMER 6
#define SL_SLEEPTIMER_PERIPHERAL_TIMER 7
// <o SL_SLEEPTIMER_PERIPHERAL> Timer Peripheral Used by Sleeptimer
// <SL_SLEEPTIMER_PERIPHERAL_DEFAULT=> Default (auto select)
// <SL_SLEEPTIMER_PERIPHERAL_RTCC=> RTCC
// <SL_SLEEPTIMER_PERIPHERAL_PRORTC=> Radio internal RTC (PRORTC)
// <SL_SLEEPTIMER_PERIPHERAL_RTC=> RTC
// <SL_SLEEPTIMER_PERIPHERAL_SYSRTC=> SYSRTC
// <SL_SLEEPTIMER_PERIPHERAL_BURTC=> Back-Up RTC (BURTC)
// <SL_SLEEPTIMER_PERIPHERAL_WTIMER=> WTIMER
// <SL_SLEEPTIMER_PERIPHERAL_TIMER=> TIMER
// <i> Selection of the Timer Peripheral Used by the Sleeptimer
#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT
// <o SL_SLEEPTIMER_TIMER_INSTANCE> TIMER/WTIMER Instance Used by Sleeptimer (not applicable for other peripherals)
// <i> Make sure TIMER instance size is 32bits. Check datasheet for 32bits TIMERs.
// <i> Default: 0
#define SL_SLEEPTIMER_TIMER_INSTANCE 0
// <q SL_SLEEPTIMER_WALLCLOCK_CONFIG> Enable wallclock functionality
// <i> Enable or disable wallclock functionalities (get_time, get_date, etc).
// <i> Default: 0
#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0
// <o SL_SLEEPTIMER_FREQ_DIVIDER> Timer frequency divider (not applicable for WTIMER/TIMER)
// <i> WTIMER/TIMER peripherals are always prescaled to 1024.
// <i> Default: 1
#define SL_SLEEPTIMER_FREQ_DIVIDER 1
// <q SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER> If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used.
// <i> Default: 0
#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0
// <q SL_SLEEPTIMER_DEBUGRUN> Enable DEBUGRUN functionality on hardware RTC.
// <i> Default: 0
#define SL_SLEEPTIMER_DEBUGRUN 0
#endif /* SLEEPTIMER_CONFIG_H */
// <<< end of configuration section >>>