Initial commit of firmware
This commit is contained in:
308
config/sl_clock_manager_tree_config.h
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308
config/sl_clock_manager_tree_config.h
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/***************************************************************************//**
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* @file
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* @brief Clock Manager - Clock Tree configuration file.
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*******************************************************************************
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* # License
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* <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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******************************************************************************/
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#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H
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#define SL_CLOCK_MANAGER_TREE_CONFIG_H
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#if defined(SL_COMPONENT_CATALOG_PRESENT)
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#include "sl_component_catalog.h"
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#endif
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// Internal Defines: DO NOT MODIFY
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// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE
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// selection of each clock branch to the right HW register value.
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#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF
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#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE
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#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD
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#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC
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#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB
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#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA
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#if defined(SL_CATALOG_RAIL_LIB_PRESENT)
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#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO
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#else
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#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL
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#endif
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Clock Tree Settings
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// <o SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE> Default Clock Source Selection for HF clock branches
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// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO=> AUTO
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// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL=> HFRCODPLL
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// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO=> HFXO
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// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO=> FSRCO
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// <i> Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value.
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// <i> AUTO uses HFXO if a radio is used and HFRCODPLL otherwise
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// <d> SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO
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#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
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#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO
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#endif
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// <o SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE> Default Clock Source Selection for LF clock branches
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// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO=> LFRCO
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// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO=> LFXO
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// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO=> ULFRCO
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// <i> Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value.
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// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO
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#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
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#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO
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#endif
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// <h> System Clock Branch Settings
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// <o SL_CLOCK_MANAGER_SYSCLK_SOURCE> Clock Source Selection for SYSCLK branch
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// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE=> DEFAULT_HF
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// <CMU_SYSCLKCTRL_CLKSEL_FSRCO=> FSRCO
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// <CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL=> HFRCODPLL
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// <CMU_SYSCLKCTRL_CLKSEL_HFXO=> HFXO
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// <CMU_SYSCLKCTRL_CLKSEL_CLKIN0=> CLKIN0
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// <i> Selection of the Clock source for SYSCLK
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// <d> SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
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#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE
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#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
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#endif
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// <o SL_CLOCK_MANAGER_HCLK_DIVIDER> HCLK branch divider
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// <CMU_SYSCLKCTRL_HCLKPRESC_DIV1=> DIV1
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// <CMU_SYSCLKCTRL_HCLKPRESC_DIV2=> DIV2
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// <CMU_SYSCLKCTRL_HCLKPRESC_DIV4=> DIV4
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// <CMU_SYSCLKCTRL_HCLKPRESC_DIV8=> DIV8
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// <CMU_SYSCLKCTRL_HCLKPRESC_DIV16=> DIV16
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// <i> HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface.
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// <d> CMU_SYSCLKCTRL_HCLKPRESC_DIV1
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#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER
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#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1
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#endif
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// <o SL_CLOCK_MANAGER_PCLK_DIVIDER> PCLK branch divider
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// <CMU_SYSCLKCTRL_PCLKPRESC_DIV1=> DIV1
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// <CMU_SYSCLKCTRL_PCLKPRESC_DIV2=> DIV2
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// <i> PCLK branch is derived from HCLK. This clock drives the APB bus interface.
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// <d> CMU_SYSCLKCTRL_PCLKPRESC_DIV1
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#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER
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#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1
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#endif
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// </h>
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// <h> Trace Clock Branches Settings
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// <o SL_CLOCK_MANAGER_TRACECLK_SOURCE> Clock Source Selection for TRACECLK branch
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// <CMU_TRACECLKCTRL_CLKSEL_DISABLE=> DISABLE
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// <CMU_TRACECLKCTRL_CLKSEL_SYSCLK=> SYSCLK
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// <CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
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// <CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT=> HFRCODPLLRT
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// <i> Selection of the Clock source for TRACECLK
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// <d> CMU_TRACECLKCTRL_CLKSEL_SYSCLK
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#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE
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#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK
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#endif
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// <o SL_CLOCK_MANAGER_TRACECLK_DIVIDER> TRACECLK branch Divider
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// <CMU_TRACECLKCTRL_PRESC_DIV1=> DIV1
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// <CMU_TRACECLKCTRL_PRESC_DIV2=> DIV2
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// <CMU_TRACECLKCTRL_PRESC_DIV3=> DIV3
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// <CMU_TRACECLKCTRL_PRESC_DIV4=> DIV4
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// <i> Selection of the divider value for TRACECLK branch
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// <d> CMU_TRACECLKCTRL_PRESC_DIV1
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#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER
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#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1
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#endif
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// </h>
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// <h> High Frequency Clock Branches Settings
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// <i> Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible
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// <i> EM01GRPACLK clock the Timer peripherals
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// <o SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE> Clock Source Selection for EM01GRPACLK branch
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// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE=> DEFAULT_HF
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// <CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL=> HFRCODPLL
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// <CMU_EM01GRPACLKCTRL_CLKSEL_HFXO=> HFXO
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// <CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO=> FSRCO
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// <CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
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// <CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT=> HFRCODPLLRT
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// <CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT=> HFXORT
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// <i> Selection of the Clock source for EM01GRPACLK
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// <d> SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
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#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE
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#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
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#endif
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// <o SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE> Clock Source Selection for EM01GRPCCLK branch
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// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE=> DEFAULT_HF
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// <CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL=> HFRCODPLL
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// <CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO=> HFXO
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// <CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO=> FSRCO
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// <CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
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// <CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT=> HFRCODPLLRT
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// <CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT=> HFXORT
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// <i> Selection of the Clock source for EM01GRPCCLK
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// <d> SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
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#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE
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#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
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#endif
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// <o SL_CLOCK_MANAGER_IADCCLK_SOURCE> Clock Source Selection for IADCCLK branch
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// <CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK=> EM01GRPACLK
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// <CMU_IADCCLKCTRL_CLKSEL_FSRCO=> FSRCO
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// <CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
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// <i> Selection of the Clock source for IADCCLK
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// <d> CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
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#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE
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#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
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#endif
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// </h>
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// <h> Low Frequency Clock Branches Settings
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// <o SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE> Clock Source Selection for EM23GRPACLK branch
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// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
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// <CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO=> LFRCO
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// <CMU_EM23GRPACLKCTRL_CLKSEL_LFXO=> LFXO
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// <CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO=> ULFRCO
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// <i> Selection of the Clock source for EM23GRPACLK
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// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
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#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE
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#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
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#endif
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// <o SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE> Clock Source Selection for EM4GRPACLK branch
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// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
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// <CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO=> LFRCO
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// <CMU_EM4GRPACLKCTRL_CLKSEL_LFXO=> LFXO
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// <CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO=> ULFRCO
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// <i> Selection of the Clock source for EM4GRPACLK
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// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
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#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE
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#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
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#endif
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// <o SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE> Clock Source Selection for SYSRTCCLK branch
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// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
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// <CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO=> LFRCO
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// <CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO=> LFXO
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// <CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO=> ULFRCO
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// <i> Selection of the Clock source for SYSRTCCLK
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// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
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#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE
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#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
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#endif
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// <o SL_CLOCK_MANAGER_WDOG0CLK_SOURCE> Clock Source Selection for WDOG0CLK branch
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// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
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// <CMU_WDOG0CLKCTRL_CLKSEL_LFRCO=> LFRCO
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// <CMU_WDOG0CLKCTRL_CLKSEL_LFXO=> LFXO
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// <CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO=> ULFRCO
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// <CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024=> HCLKDIV1024
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// <i> Selection of the Clock source for WDOG0CLK
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// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
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#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE
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#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
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#endif
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// <o SL_CLOCK_MANAGER_WDOG1CLK_SOURCE> Clock Source Selection for WDOG1CLK branch
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// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
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// <CMU_WDOG1CLKCTRL_CLKSEL_LFRCO=> LFRCO
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// <CMU_WDOG1CLKCTRL_CLKSEL_LFXO=> LFXO
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// <CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO=> ULFRCO
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// <CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024=> HCLKDIV1024
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// <i> Selection of the Clock source for WDOG1CLK
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// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
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#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE
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#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
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#endif
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// <o SL_CLOCK_MANAGER_PCNT0CLK_SOURCE> Clock Source Selection for PCNT0CLK branch
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// <CMU_PCNT0CLKCTRL_CLKSEL_DISABLED=> DISABLED
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// <CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK=> EM23GRPACLK
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// <CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0=> PCNTS0
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// <i> Selection of the Clock source for PCNT0CLK
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// <d> CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK
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#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE
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#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK
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#endif
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// </h>
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// <h> Mixed Frequency Clock Branch Settings
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// <o SL_CLOCK_MANAGER_EUSART0CLK_SOURCE> Clock Source Selection for EUSART0CLK branch
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// <CMU_EUSART0CLKCTRL_CLKSEL_DISABLED=> DISABLED
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// <CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK=> EM01GRPCCLK
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// <CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
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// <CMU_EUSART0CLKCTRL_CLKSEL_LFRCO=> LFRCO
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// <CMU_EUSART0CLKCTRL_CLKSEL_LFXO=> LFXO
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// <i> Selection of the Clock source for EUSART0CLK
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// <d> CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK
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#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE
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#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK
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#endif
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// <o SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE> Clock Source Selection for SYSTICKCLK branch
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// <0=> HCLK
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// <1=> EM23GRPACLK
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// <i> Selection of the Clock source for SYSTICKCLK
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// <d> 0
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#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE
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#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0
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#endif
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// <o SL_CLOCK_MANAGER_VDAC0CLK_SOURCE> Clock Source Selection for VDAC0CLK branch
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// <CMU_VDAC0CLKCTRL_CLKSEL_DISABLED=> DISABLED
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// <CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK=> EM01GRPACLK
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// <CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK=> EM23GRPACLK
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// <CMU_VDAC0CLKCTRL_CLKSEL_FSRCO=> FSRCO
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// <CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
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// <i> Selection of the Clock source for VDAC0CLK
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// <d> CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK
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#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE
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#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK
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#endif
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// <o SL_CLOCK_MANAGER_VDAC1CLK_SOURCE> Clock Source Selection for VDAC1CLK branch
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// <CMU_VDAC1CLKCTRL_CLKSEL_DISABLED=> DISABLED
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// <CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK=> EM01GRPACLK
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// <CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK=> EM23GRPACLK
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// <CMU_VDAC1CLKCTRL_CLKSEL_FSRCO=> FSRCO
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// <CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
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// <i> Selection of the Clock source for VDAC1CLK
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// <d> CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK
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#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE
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#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK
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#endif
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// </h>
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// </h>
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#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */
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// <<< end of configuration section >>>
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